Lecture 15 Etching. Chapters 15 & 16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/76

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "Lecture 15 Etching. Chapters 15 & 16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/76"

Transcription

1 Lecture 15 Etching Chapters 15 & 16 Wolf and Tauber 1/76

2 Announcements Term Paper: You are expected to produce a 4-5 page term paper on a selected topic (from a list). Term paper contributes 25% of course grade. You should have all been assigned your first-choice topic. The term paper should be handed in at the start of class on Tuesday 21 st November. Details / regulations are on the course website. The term paper will be returned to you in class on Tuesday 28 th November. 2/76

3 Announcements Homework 4/4: Will be set on Tuesday 21 st. It will be a normal length homework (like HW 1 & 2). 25 marks. Due Tuesday 28 th November. I will return it after the final exam. I will post the solutions immediately after I receive all the homeworks. 3/76

4 Announcements Final Exam: Gleeson 100. Tuesday December 5 th Scheduled: 14:00 to 15: minutes (1 hour 50 minutes). 3 out 4 questions. Otherwise format will be the same as midterm. Closed book and closed notes. All constants and most formulae will be given. Review lecture November 28 th will go through examples. No lecture November 30 th I will upload some sample questions. 4/76

5 Useful Links MIT: cture12.pdf Berkeley: Georgia Tech: Etching%20especially%20Plasma%20Etching.pdf 5/76

6 Lecture 15 Etching Overview / Review. Figures of Merit for Etching. Etching Non-Uniform Features. Wet Etching. Dry Etching. 6/76

7 Etching Overview 7/76

8 Etching Etching is the removal of regions of deposited films or substrates. The overall goal of the etch process for VLSI fabrication is to be able to reproduce the features on the mask with fidelity We want to be able to control the slope of the features we etch. Anisotropic etching Isotropic etching Photoresist SiO 2 Substrate: Si Photoresist SiO 2 Substrate: Si 8/76

9 Dry Etch vs Wet Etch Wet etch: E.g. HF etch (see Lecture 4): SiO 2 + 6HF L H 2 SiF 6 L + 2H 2 O(L) Photoresist SiO 2 Substrate: Si Typically isotropic. Poor control over feature size. High selectivity. 9/76

10 Dry Etch vs Wet Etch Dry etch: Ions in plasma are applied directionally. Photoresist SiO 2 Substrate: Si Can achieve anisotropic etching. Necessary for small features. Can have poor selectivity. 10/76

11 Figures of Merit for Etching 11/76

12 Selectivity Etch selectivity is defined as follows: Selectivity of A on B Pre-Etch S AB = R A R B = Etch rate of Material to be removed Etch rate of Material to remain Low Selectivity Vertical etch rate of material B Vertical etch rate of material A High Selectivity Photoresist Photoresist Photoresist Film Film Film Substrate Substrate Substrate 12/76

13 Selectivity In wet etching selectivity is controlled by: Chemicals employed. Concentration. Temperature. In dry etching selectivity is controlled by: Plasma chemistry. Gas Pressure. Flow rate. Applied voltage. Temperature. In dry etching S ~ 10. In wet etching S can be ~. 13/76

14 Selectivity We often want to etch all the way to the substrate: But we don t want to etch the substrate itself. Photoresist Film Photoresist Substrate Film Photoresist Substrate Film Substrate 14/76

15 Selectivity So we need to define two types of selectivity: Film-mask selectivity S fm = R f R m Photoresist Photoresist Film Substrate Film-substrate selectivity S fs = R f R s Film Where: Substrate R f = Vertical etch rate in film. R f = Vertical etch rate in mask (photoresist). R s = Vertical etch rate in substrate. 15/76

16 Selectivity of Si/SiO 2 Si/SiO 2 etched by HF solution: S SiO2,Si ~ Si/SiO 2 etched by reactive ion-etching (RIE): S SiO2,Si ~10 SiO 2 Si 16/76

17 Example Consider a simple etch of SiO 2 on Si, where S fs = 25, and the thickness of SiO 2 is 1μm. Carry out an etch for 3 minutes with R f = R SiO2 = 4000 Å/min. SiO 2 1 μm How much Si is etched? First, determine the amount of time to etch the SiO 2. Si t f = 10, = 2.5 mins After the 2.5 minutes, the Si is exposed. So, the silicon is exposed for t s = = 0.5 minutes. 17/76

18 Example The silicon is exposed for 0.5 minutes. Now determine the etch rate in the Si. R Si = R SiO 2 S fs = 4000 Ås 1 25 = 160 Ås 1 The thickness etched is then: Si x = t s R Si = = 80Å 18/76

19 Bias Bias is a way of quantifying etch anisotropy. d m Bias Photoresist Film B = d f d m Substrate Largest length etched Target etch length d f Bias has dimensions of length. In this example, the bias is positive. 19/76

20 Bias We can have negative bias: d m Bias Photoresist Film B = d f d m Substrate Smallest length of film remaining Target etch length d f In this case d f is the smallest length of the film remaining. Bias quantifies how far off our target etch we are. 20/76

21 Anisotropy Dimensionless variable used to quantify how anisotropic an etch is: Photoresist Film R v Substrate R l Anisotropy A = 1 R l R v 0 A 1 Lateral etch rate Vertical etch rate Completely isotropic (wet etch) Completely anisotropic (ions) 21/76

22 Mask Erosion The mask (photoresist) will also etch laterally as well. We quantify this just by the change size in mask laterally. This is important if we wish to do multiple process steps with one mask. E.g. etch then ion implant. Photoresist Film Substrate m Photoresist Film Substrate 22/76

23 Example Let s say we want to etch 100nm SiO 2 from the surface of an Si substrate, then immediately implant the Si with a dopant. Say the feature size is 50nm. If the etch which has an anisotropy of 0.5 and a film-mask selectivity of 10, what size will be the region we implant ions over? Assume the filmsubstrate selectivity is ~, and the photoresist is 1μm thick. Photoresist SiO 2 Si 50 nm 1 μm 100 nm 23/76

24 Example Since the film-substrate (R fs ) selectivity is ~, we know the etch rate in the silicon will be zero, and hence don t have to worry about etching the Si unintentionally. Also, since the photoresist is 1μm thick, we can easily show that the photoresist will not be depleted when etching all the SiO 2 (100nm): Film-mask selectivity S fm = R f R m = 10 If in time t 100nm of SiO 2 is etched, then the etched PR will be only: 100nm = 10nm S fm 24/76

25 Example Now look at the anisotropy: Anisotropy So we can say: A = 1 R l R v R l = 0.5R v Lateral etch rate = 0.5 Vertical etch rate I.e. the lateral etch rate is half the vertical etch rate. We can assume that A is the same in the resist and the film. 25/76

26 Example Now look at the selectivity: Film-mask selectivity S fm = R f R m = 10 R f = 10R m I.e. the film (SiO 2 ) we be etched 10 as fast as the mask. Combined with the anisotropy (R l = 0.5R v ), we can hence say the film will be etched vertically 20 as fast as the mask is etched laterally. Hence if it takes a time t to etch 100nm of SiO 2, then the mask erosion will be: m = = 5nm 26/76

27 Example The mask erosion is m = 5nm. Recall, the erosion takes place on either side. Hence the gap is now 50nm + 2 5nm = 60nm. So when we dope the wafer, it will now be over a length of 60nm. This is important, when we anneal the wafer, then apply the diffusion equation to determine the final dopant distribution. 50 nm m Photoresist Film Substrate 27/76

28 Etching Non-Uniform Features 28/76

29 Etching a Step In multi-layer VLSI, we are often etching non-uniform features. Film R v Vertical etch rate R l Lateral etch rate As we mentioned previously, the etch rate can be different in the vertical and lateral directions. The relative etch rates are given by the anisotropy parameter: Substrate A = 1 R l R v 0 A 1 29/76

30 Steps With a Slope Often the features have some sort of slope. How do we determine the film dimensions after a certain amount of time (t)? The thickness change will Vertical etch rate R still just be determined by v R v. Film R v t For the lateral etch, we have two contributions. Substrate x = x 1 + x 2 30/76

31 Steps With a Slope For the lateral etch, we have two contributions. Film θ R v Vertical etch rate x = x 1 + x 2 R l R l t Lateral etch rate There is the contribution from the lateral etch rate: x 1 = R l t Substrate The total etched distance in time t is then: x = R v cot θ + R l t The contribution from the vertical etch rate is: x 2 = R vt tan θ = R vt cot θ 31/76

32 Uniformity The etch rate is not always uniform across the wafer. Film Substrate This is quantified with the uniformity parameter: Maximum etch rate U = R max R min R max + R min If R max = R min, i.e. the etch is completely uniform: U = 0 If we have a high film-substrate selectivity (S fs ), then U > 0 isn t necessarily a problem. Minimum etch rate 32/76

33 Uniformity The starting film is also likely to have some non-uniformity. Film h f This is quantified by the thickness variation parameter: δ 0 δ 1 Substrate If the mean film thickness is h f, the maximum thickness is given approximated by: h f max = h f 1 + δ Run-to-run variation of thickness data are recorded. Once the deposition process is under control, the maximum / minimum values will be used to define δ. 33/76

34 Uniformity The variation in etch rate can also be quantified by the rate variation parameter: φ 0 φ 1 Film If the mean etch rate of the film is R f, the minimum etch rate is then: Substrate R f min = R f 1 φ In order to ensure that we etch everything (worst case scenario), we then know the time is therefore: t max = h f max R f min = h f 1 + δ R f 1 φ 34/76

35 Example Consider again an etch of SiO 2 on Si, where: S fs = 25. S fs = 25. h f = 1μm. R f = R SiO2 = 4000 Å/min. But now consider finite variations in film and etch rate: δ = φ = 0.1. SiO 2 If we carry out an etch to ensure that all SiO 2 is removed, what is the maximum depth of Si that will be etch? Si 1 μm 35/76

36 Example First, determine the etch time to ensure that all the SiO 2 is removed (accounting for variations in rate and film thickness): Average film thickness Average SiO 2 etch rate Work in Å/min: t max = t max = h f 1 + δ R f 1 φ = 2.92 min Thickness variation parameter Etch rate variation parameter This is the time required under worst case scenario (maximum thickness and slowest rate). Hence we must carry out the etch for 2.92 min. 36/76

37 Example t max = 2.92 min Now, to determine the maximum amount of silicon removed, we must consider best-case conditions. I.e. we must assume that at certain positions the rate is higher than average, and the SiO 2 thickness is lower than average. The maximum time to etch the SiO 2 was given by: t max = h f 1 + δ R f 1 φ The minimum time to etch the SiO 2 is hence: t min = h f 1 δ R f 1 + φ 37/76

38 Example t min = h f 1 δ R f 1 + φ Use this equation to determine the time to reach Si in the best-case scenario (thinnest part of film and fastest etch rate): t min = = 2.16 min Now determine the amount of time this bare Si is exposed during the etch: t Si = t max t min = = 0.76 min So we just need to the maximum amount of Si is etched in this amount of time. 38/76

39 Example t Si = 0.76 min This is the amount of time Si is exposed in the position where Si is first exposed. Recall, we are after the worst case scenario (i.e. maximum Si etched). So we again must consider the fastest etch rate: R Si max = R Si 1 + φ We can get the etch rate of silicon from the selectivity: R Si = R SiO 2 S fs = = 160Å/min R Si max = R Si 1 + φ = = 176Å/min 39/76

40 Example R Si max = 176Å/min Now we can work how much Si is etched in 0.76: x = = 134 Å 40/76

41 Wet Etching 41/76

42 Wet Etching The solution etches the film but not the mask: Diffusion PR Film Reactants Substrate Reaction Reaction products Boundary layer Diffusion Mass transport of reactants through boundary layer. Reaction between reactants and the film. Mass transport of reaction products away from the surface through the boundary layer. Wafer is just immersed in a solution containing the reactants. 42/76

43 Wet Etching Advantages: High selectivity due to the chemical reactions. Cheap. Bulk processing possible. Disadvantages: Usually isotropic. Poor process control transport or reaction rate limited. Stong T-dependence. Large amounts of chemical waste. 43/76

44 Wet Etching of Silicon Common silicon wet etch involves hydrofluoric acid: Si S + HNO 3 L + 6HF L H 2 SiF 6 L + 2H 2 O L + HNO 2 L + H 2 Nitric acid Hydrofluoric acid Hexafluorosilicic acid Nitrous acid Buffered HF etch: Use acetic acid (HC 2 H 3 O 3 ) instead of water. NH 4 F added to prevent depletion of F and retard etch of photoresist. Ammonium fluoride 44/76

45 Wet Etching of Silicon The rate of etch depends on the relative concentration of acids: The lines indicate etch rates for a given composition. The percentages refer to the concentration of the acids in water. HF(50%) = HF:H 2 O (1:1 volume %) HNO 3 (70%) = HNO 3 :H 2 O (7:3 volume %) 45/76

46 Example Determine the etch rate of a solution consisting of 2 parts HNO3 (70%), 6 parts HF (49%) and 2 parts HC 2 H 3 O 3. Etch rate = 165μm/min. 46/76

47 Wet Etching of Si 3 N 4 Silicon nitride (Si 3 N 4 ) is etched very slowly by HF solutions at room temperature. For example, using a buffered oxide etch with a volume ratio of 20:1 (NH 4 F:HF): R SiO2 = 300 Å/min. R Si3 N 4 = 5-15 Å/min. S SiO2,Si 3 N 4 = At room temperature is just HF (49%): R Si3 N 4 = 500 Å/min. 47/76

48 Wet Etching of Si 3 N 4 Silicon nitride (Si 3 N 4 ) is typically etched with phosphoric acid: R Si3 N 4 = 100 Å/min. R SiO2 = 10 Å/min. R Si = 3 Å/min. Selectivity: S Si3 N 4,SiO 2 = 10. S Si3 N 4,Si = /76

49 Wet Etching of Aluminum Aluminum etches in a mixture of phosphoric acid, water, nitric acid, and acetic acid: 50H 3 PO 4 : 20H 2 O : 1HNO 3 : 1HC 2 H 3 O 3 Phosphoric acid Water Nitric acid Acetic acid Al converts to Al 2 O 3. Dissolve Al 2 O 3. in phosphoric acid. Gas evolution leading to bubbles. Local etch rate is reduced in vicinity of bubbles. Non-uniformity. 49/76

50 Wet Etching of Photoresist Photoresist are generally formed of organic polymers (C,H containing molecules). Piranha solution is typically used: H 2 SO 4 and H 2 O 2. Wafers Solution of reactants Sulphuric acid Hydrogen peroxide H 2 SO 4 dissolves the polymer. H 2 O 2 oxidized the polymer: CH polymer S + H 2 O 2 L CO 2 G + H 2 O L 50/76

51 Common Wet Etches 51/76

52 Dry Etching 52/76

53 Plasma Etching Tetrafluoromethane We covered plasma pretty extensively in lecture 6. Overview of way to plasma etch: Use a molecular gas (often inert) e.g. CF 4. Establish a glow discharge and create reactive gas species by dissociation. E.g.: CF 4 + e CF 3 + F + e Choose chemistry so that the reactive species reacts with the solid to form a volatile product Si + 4F SiF 4 Pump away volatile product. 53/76

54 Plasma Etching Plasma energy makes ions and free radicals. Energy Ion Free Radicals Energy V V(x) V f sheath bulk V P, plasma potential X 54/76

55 Etching: Free Radicals Chemical Process Free radicals react with substrate to form products 55/76

56 Etching: Ion Bombardment Ions bombard the surface. The surface gets damaged (weakened). Physical Process Surface damage Sidewall passivation 56/76

57 Etching: Gas Products The gas products then escape from the surface. Etch chemistries are carefully selected to form volatile products. Chemical Process Material removed from under exposed surface Gas products High Vapor Pressure: Low Vapor Pressure: SiF 4 AlCl 3 CuCl BP at 1 atm -86 o C Gas products leave surface with atoms from the substrate. The desired shape is obtained. 57/76

58 Etch Chemistry of Si Carbon-fluorine gases are commonly employed in dry etching. H 2 Addition H + F HF O 2 Addition CF x + 2O CO 2 + xf CF x forms polymer F etches Si + 4F SiF 4 CF x + F CF x+1 Isotropic Etching Kay et al., Topics in Current Chemistry, Springer-Verlag, NY (1980). 58/76

59 Sidewall Passivation Depending on the process gas composition, SiO x F x functional groups can condense into polymers. These polymers forms on all surfaces. Ions preferentially remove polymer from bottom. A film on the sidewall protects them from free radicals. A strategy to enable high selectivity and high anisotropy. Photoresist SiO 2 Substrate: Si 59/76

60 Neutral CF 4 CF 4 is not hugely selective. Tetrafluoromethane Photoresist etches too quickly. Photoresist SiO 2 Substrate Substrate etches too quickly. Photoresist SiO 2 Substrate Can tune rate, by mixing with H 2. 60/76

61 Etching with CF 4 Silicon can be removed from selected regions of a substrate by etching using a CF 4 plasma. CF 4+ ions bombard and damage the surface. The plasma dissociates CF 4. F free radicals are produced. The free radicals react with the weakened silicon atoms on the surface. SiF 4 and SiF 2 are the reaction products. These molecules escape from the surface. F does not react with the photoresist. 61/76

62 Ionization of CF 4 High Speed Electron e - + CF 4 CF 4+ + e - + e - Neutral Molecule ( CF 4 ) Ion (CF 4+ ) 62/76

63 Ion Bombardment Ion bombardment damages surface (Physical process) Free radical does not react with photoresist Bulk Sheath Silicon Polymer Free radical ( F ) moving around Reaction product escapes from surface Free radical reacts with weakened silicon (Chemical process) 63/76

64 Dissociation of CF 4 High speed Electron e - + CF 4 CF 2 + F + F + e - 64/76

65 Selectivity of CF 2 Free radicals react selectively with the films Photoresist: CF 2 does not make a gas product. Oxide: CF 2 (G) + SiO 2 (S) CO 2 (G) + SiF 2 G Two gas products are made, so the film etches. Substrate: CF 2 (G) + Si (S) C(S) + SiF 2 G One product is solid, so the film does not etch (but will be contaminated). Photoresist SiO 2 Si 65/76

66 End Point Detection At the end of an etch the underlying film or substrate becomes exposed. This is known as the end point. End Point Detection: Products from the reaction of free radicals and the etched film (SiO 2 ) give color to the plasma. Products from the reaction of free radicals and the underlying film (Si) give a different color to the plasma. This color change indicates the end point. PR SiO 2 Si PR SiO 2 Si 66/76

67 End Point: Overetch When the end point is reached, the etch process is often continued for a set time. This is called overetch. Overetch makes sure that the etch is complete at every feature and no residue is left. PR RIE lag: Variation in depth with feature size SiO 2 Si (1) (2) 67/76

68 Materials Etched Various materials that are etched are shown below: Etch Silicon Insulators Metals Polymers poly-si (conductor) Si- wafer (semiconductor) Oxide (SiO 2 / BPSG) Nitride (Si 3 N 4 ) TiN / Al-Cu / TiN Stack Photoresist BARC 68/76

69 Silicon: poly-si Gases used: Cl 2 /HBr/O 2 Role of gases: Hydrogen bromide Cl 2 makes Cl free radicals which etch Si: Si S + 2Cl(G) SiCl 2 (G) HBr helps sidewall passivation (anisotropy). O 2 helps plasma generate Cl poly-si (conductor) Si- wafer (semiconductor) Etch Silicon Insulators Metals Polymers Oxide (SiO 2 / BPSG) Nitride (Si 3 N 4 ) T in / Al-Cu / T in Stack Photoresist BARC 69/76

70 Silicon: Si-wafer (Crystalline) Gases used: CF 4 /CHF 3 /O 2 Role of gases: Fluoroform CF 4 makes F free radicals which etch Si: Si S + 2F(G) SiF 2 (G) F is more reactive than Cl (used for poly-si). O 2 helps plasma generate Cl poly-si (conductor) Si- wafer (semiconductor) Etch Silicon Insulators Metals Polymers Oxide (SiO 2 / BPSG) Nitride (Si 3 N 4 ) T in / Al-Cu / T in Stack Photoresist BARC More isotropic higher etch rate, decreased anisotropy CHF 3 increases film formation. Sidewall passivation (anisotropy), Selectivity. 70/76

71 Insulators: Oxide Gases used: CF 4 /CHF 3 /CO/Ar or CF 4 /CHF 3 /Ar Role of gases: If CO is used: poly-si (conductor) Si- wafer (semiconductor) Etch Silicon Insulators Metals Polymers Oxide (SiO 2 / BPSG) Nitride (Si 3 N 4 ) T in / Al-Cu / T in Stack Photoresist BARC CF 4 makes CF 2 free radicals which etch SiO 2 SiO 2 S + 2F 2 G SiF 2 G + CO 2 If CO is not used: CF 4 makes F free radicals which etch SiO 2 Si S + 2F G SiF 2 G + O 2 G 71/76

72 Insulators: Nitride Etch process of nitrides (e.g. Si 3 N 4 ) is very similar to Oxides Gases used: CF 4 /CHF 3 /Ar Role of gases: poly-si (conductor) Si- wafer (semiconductor) Etch Silicon Insulators Metals Polymers Oxide (SiO 2 / BPSG) Nitride (Si 3 N 4 ) T in / Al-Cu / T in Stack Photoresist BARC CF 4 makes CF 2 and F free radicals which etch Si 3 N 4 Si 3 N 4 S + 3CF 2 G 3SiF 2 G + N 2 G + CN Si 3 N 4 S + 6F G 3SiF 2 G + 2N 2 G Roles of other gases are the same as for SiO 2. 72/76

73 Metal: TiN/Al-Cu/ TiN Stack Gases used: Boron trichloride Etch BCl 3 /Cl 2 Role of gases: Cl 2 makes Cl free radicals which etch Al (AlF 3 is not volatile): poly-si (conductor) Si- wafer (semiconductor) Silicon Insulators Metals Polymers Oxide (SiO 2 / BPSG) Nitride (Si 3 N 4 ) T in / Al-Cu / T in Stack Photoresist BARC Al S + 3Cl(G) AlCl 3 (G) BCl 3 provides large ions for ion bombardment. Increases anisotropy. Bombards photoresist, makes polymer film. Removes film at bottom Sputters CuCl which is not a gas. 73/76

74 Photoresist & BARC Dry etching: Plasma ashing Gases Used: O 2 Role of gases: Bottom Anti- Reflective Coating poly-si (conductor) Si- wafer (semiconductor) O 2 makes O free radicals which etch the C-H polymer Etch Silicon Insulators Metals Polymers Oxide (SiO 2 / BPSG) Nitride (Si 3 N 4 ) CH polymer S + O G CO 2 G + H 2 O G T in / Al-Cu / T in Stack Photoresist BARC 74/76

75 Gas-Solid Systems Solid Etch Gas Etch Product Si CF 4, Cl 2, NF 3, HBr SiF 4, SiCl 4, SiCl 2, SiBr 4 SiO 2 CF 4, SF 6, NF 3 SiF 4 Al BCl 3 /Cl 2 Al 2 Cl 6, AlCl 3 W, Ta, Nb, Mo SF 6, CF 4 WF 6, TaF 6 Ti, TiN Cl 2 TiCl 4 Organics, C O 2, O 2 /CF 4 CO, CO 2, HF, H 2, H 2 O GaAs Cl 2, BCl 3 Ga 2 Cl 6, AsCl 3 HgCdTe, InP CH 4 /H 2 In(CH 3 ) 3, PH 3, Cd(CH 3 ) 2 Cr O 2 /Cl 2 CrO 2 Cl 2 75/76

Section 3: Etching. Jaeger Chapter 2 Reader

Section 3: Etching. Jaeger Chapter 2 Reader Section 3: Etching Jaeger Chapter 2 Reader Etch rate Etch Process - Figures of Merit Etch rate uniformity Selectivity Anisotropy d m Bias and anisotropy etching mask h f substrate d f d m substrate d f

More information

Lecture 6 Plasmas. Chapters 10 &16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/68

Lecture 6 Plasmas. Chapters 10 &16 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/68 Lecture 6 Plasmas Chapters 10 &16 Wolf and Tauber 1/68 Announcements Homework: Homework will be returned to you on Thursday (12 th October). Solutions will be also posted online on Thursday (12 th October)

More information

4FNJDPOEVDUPS 'BCSJDBUJPO &UDI

4FNJDPOEVDUPS 'BCSJDBUJPO &UDI 2010.5.4 1 Major Fabrication Steps in CMOS Process Flow UV light oxygen Silicon dioxide Silicon substrate Oxidation (Field oxide) photoresist Photoresist Coating Mask exposed photoresist Mask-Wafer Exposed

More information

Reactive Ion Etching (RIE)

Reactive Ion Etching (RIE) Reactive Ion Etching (RIE) RF 13.56 ~ MHz plasma Parallel-Plate Reactor wafers Sputtering Plasma generates (1) Ions (2) Activated neutrals Enhance chemical reaction 1 2 Remote Plasma Reactors Plasma Sources

More information

Device Fabrication: Etch

Device Fabrication: Etch Device Fabrication: Etch 1 Objectives Upon finishing this course, you should able to: Familiar with etch terminology Compare wet and dry etch processes processing and list the main dry etch etchants Become

More information

Etching: Basic Terminology

Etching: Basic Terminology Lecture 7 Etching Etching: Basic Terminology Introduction : Etching of thin films and sometimes the silicon substrate are very common process steps. Usually selectivity, and directionality are the first

More information

CHAPTER 6: Etching. Chapter 6 1

CHAPTER 6: Etching. Chapter 6 1 Chapter 6 1 CHAPTER 6: Etching Different etching processes are selected depending upon the particular material to be removed. As shown in Figure 6.1, wet chemical processes result in isotropic etching

More information

ETCHING Chapter 10. Mask. Photoresist

ETCHING Chapter 10. Mask. Photoresist ETCHING Chapter 10 Mask Light Deposited Substrate Photoresist Etch mask deposition Photoresist application Exposure Development Etching Resist removal Etching of thin films and sometimes the silicon substrate

More information

Lecture 11. Etching Techniques Reading: Chapter 11. ECE Dr. Alan Doolittle

Lecture 11. Etching Techniques Reading: Chapter 11. ECE Dr. Alan Doolittle Lecture 11 Etching Techniques Reading: Chapter 11 Etching Techniques Characterized by: 1.) Etch rate (A/minute) 2.) Selectivity: S=etch rate material 1 / etch rate material 2 is said to have a selectivity

More information

EE 527 MICROFABRICATION. Lecture 25 Tai-Chang Chen University of Washington

EE 527 MICROFABRICATION. Lecture 25 Tai-Chang Chen University of Washington EE 527 MICROFABRICATION Lecture 25 Tai-Chang Chen University of Washington ION MILLING SYSTEM Kaufmann source Use e-beam to strike plasma A magnetic field applied to increase ion density Drawback Low etch

More information

UNIT 3. By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun

UNIT 3. By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun UNIT 3 By: Ajay Kumar Gautam Asst. Prof. Dev Bhoomi Institute of Technology & Engineering, Dehradun 1 Syllabus Lithography: photolithography and pattern transfer, Optical and non optical lithography, electron,

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Fall Exam 1

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Fall Exam 1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 143 Fall 2008 Exam 1 Professor Ali Javey Answer Key Name: SID: 1337 Closed book. One sheet

More information

Etching Issues - Anisotropy. Dry Etching. Dry Etching Overview. Etching Issues - Selectivity

Etching Issues - Anisotropy. Dry Etching. Dry Etching Overview. Etching Issues - Selectivity Etching Issues - Anisotropy Dry Etching Dr. Bruce K. Gale Fundamentals of Micromachining BIOEN 6421 EL EN 5221 and 6221 ME EN 5960 and 6960 Isotropic etchants etch at the same rate in every direction mask

More information

Etching. Etching Terminology. Etching Considerations for ICs. Wet Etching. Reactive Ion Etching (plasma etching) Professor N Cheung, U.C.

Etching. Etching Terminology. Etching Considerations for ICs. Wet Etching. Reactive Ion Etching (plasma etching) Professor N Cheung, U.C. Etching Etching Terminology Etching Considerations or ICs Wet Etching Reactie Ion Etching (plasma etching) 1 Etch Process - Figures o Merit Etch rate Etch rate uniormity Selectiity Anisotropy 2 (1) Bias

More information

Dry Etching Zheng Yang ERF 3017, MW 5:15-6:00 pm

Dry Etching Zheng Yang ERF 3017,   MW 5:15-6:00 pm Dry Etching Zheng Yang ERF 3017, email: yangzhen@uic.edu, MW 5:15-6:00 pm Page 1 Page 2 Dry Etching Why dry etching? - WE is limited to pattern sizes above 3mm - WE is isotropic causing underetching -

More information

EE 527 MICROFABRICATION. Lecture 24 Tai-Chang Chen University of Washington

EE 527 MICROFABRICATION. Lecture 24 Tai-Chang Chen University of Washington EE 527 MICROFABRICATION Lecture 24 Tai-Chang Chen University of Washington EDP ETCHING OF SILICON - 1 Ethylene Diamine Pyrocatechol Anisotropy: (100):(111) ~ 35:1 EDP is very corrosive, very carcinogenic,

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction q Integrated circuits: many transistors on one chip q Very Large Scale Integration (VLSI): bucketloads! q Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

LECTURE 5 SUMMARY OF KEY IDEAS

LECTURE 5 SUMMARY OF KEY IDEAS LECTURE 5 SUMMARY OF KEY IDEAS Etching is a processing step following lithography: it transfers a circuit image from the photoresist to materials form which devices are made or to hard masking or sacrificial

More information

Plasma etching. Bibliography

Plasma etching. Bibliography Plasma etching Bibliography 1. B. Chapman, Glow discharge processes, (Wiley, New York, 1980). - Classical plasma processing of etching and sputtering 2. D. M. Manos and D. L. Flamm, Plasma etching; An

More information

Plasma Deposition (Overview) Lecture 1

Plasma Deposition (Overview) Lecture 1 Plasma Deposition (Overview) Lecture 1 Material Processes Plasma Processing Plasma-assisted Deposition Implantation Surface Modification Development of Plasma-based processing Microelectronics needs (fabrication

More information

Plasma etching. Bibliography

Plasma etching. Bibliography Plasma etching Bibliography 1. B. Chapman, Glow discharge processes, (Wiley, New York, 1980). - Classical plasma processing of etching and sputtering 2. D. M. Manos and D. L. Flamm, Plasma etching; An

More information

E SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam

E SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam E SC 412 Nanotechnology: Materials, Infrastructure, and Safety Wook Jun Nam Lecture 10 Outline 1. Wet Etching/Vapor Phase Etching 2. Dry Etching DC/RF Plasma Plasma Reactors Materials/Gases Etching Parameters

More information

Wet and Dry Etching. Theory

Wet and Dry Etching. Theory Wet and Dry Etching Theory 1. Introduction Etching techniques are commonly used in the fabrication processes of semiconductor devices to remove selected layers for the purposes of pattern transfer, wafer

More information

Chapter 9, Etch. Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm

Chapter 9, Etch. Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Chapter 9, Etch Hong Xiao, Ph. D. hxiao89@hotmail.com www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Upon finishing this course, you should

More information

課程名稱 : 微製造技術 Microfabrication Technology. 授課教師 : 王東安 Lecture 6 Etching

課程名稱 : 微製造技術 Microfabrication Technology. 授課教師 : 王東安 Lecture 6 Etching 課程名稱 : 微製造技術 Microfabrication Technology 授課教師 : 王東安 Lecture 6 Etching 1 Lecture Outline Reading Campbell: Chapter 11 Today s lecture Wet etching Chemical mechanical polishing Plasma etching Ion milling

More information

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #7. Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #7. Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory Issued: Tuesday, Oct. 14, 2014 PROBLEM SET #7 Due: Friday, Oct. 24, 2014, 8:00 a.m. in the EE 143 homework box near 140 Cory Electroplating 1. Suppose you want to fabricate MEMS clamped-clamped beam structures

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2010

EE C245 ME C218 Introduction to MEMS Design Fall 2010 Lecture Outline EE C245 ME C28 Introduction to MEMS Design Fall 200 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720

More information

Lecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen

Lecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen Lecture 150 Basic IC Processes (10/10/01) Page 1501 LECTURE 150 BASIC IC PROCESSES (READING: TextSec. 2.2) INTRODUCTION Objective The objective of this presentation is: 1.) Introduce the fabrication of

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2007

EE C245 ME C218 Introduction to MEMS Design Fall 2007 EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 4: Film

More information

Chapter 7 Plasma Basic

Chapter 7 Plasma Basic Chapter 7 Plasma Basic Hong Xiao, Ph. D. hxiao89@hotmail.com www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives List at least three IC processes

More information

Regents of the University of California

Regents of the University of California Deep Reactive-Ion Etching (DRIE) DRIE Issues: Etch Rate Variance The Bosch process: Inductively-coupled plasma Etch Rate: 1.5-4 μm/min Two main cycles in the etch: Etch cycle (5-15 s): SF 6 (SF x+ ) etches

More information

Lecture 7 Oxidation. Chapter 7 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/82

Lecture 7 Oxidation. Chapter 7 Wolf and Tauber. ECE611 / CHE611 Electronic Materials Processing Fall John Labram 1/82 Lecture 7 Oxidation Chapter 7 Wolf and Tauber 1/82 Announcements Homework: Homework will be returned to you today (please collect from me at front of class). Solutions will be also posted online on today

More information

Lithography and Etching

Lithography and Etching Lithography and Etching Victor Ovchinnikov Chapters 8.1, 8.4, 9, 11 Previous lecture Microdevices Main processes: Thin film deposition Patterning (lithography) Doping Materials: Single crystal (monocrystal)

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2007

EE C245 ME C218 Introduction to MEMS Design Fall 2007 EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 12: Mechanics

More information

The Stanford Nanofabrication Facility. Etch Area Overview. May 21, 2013

The Stanford Nanofabrication Facility. Etch Area Overview. May 21, 2013 The Stanford Nanofabrication Facility Etch Area Overview May 21, 2013 High Density Plasma Systems Etcher Materials Etched Gases available Wafer Size Applied Materials P5000 MRIE ChA Applied Materials P5000

More information

EE C245 ME C218 Introduction to MEMS Design Fall 2007

EE C245 ME C218 Introduction to MEMS Design Fall 2007 EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 11: Bulk

More information

CVD: General considerations.

CVD: General considerations. CVD: General considerations. PVD: Move material from bulk to thin film form. Limited primarily to metals or simple materials. Limited by thermal stability/vapor pressure considerations. Typically requires

More information

EE-612: Lecture 22: CMOS Process Steps

EE-612: Lecture 22: CMOS Process Steps EE-612: Lecture 22: CMOS Process Steps Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN www.nanohub.org Lundstrom EE-612 F06 1 outline 1) Unit Process

More information

Fabrication Technology, Part I

Fabrication Technology, Part I EEL5225: Principles of MEMS Transducers (Fall 2004) Fabrication Technology, Part I Agenda: Microfabrication Overview Basic semiconductor devices Materials Key processes Oxidation Thin-film Deposition Reading:

More information

UNIVERSITY OF CALIFORNIA. College of Engineering. Department of Electrical Engineering and Computer Sciences. Professor Ali Javey.

UNIVERSITY OF CALIFORNIA. College of Engineering. Department of Electrical Engineering and Computer Sciences. Professor Ali Javey. UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE 143 Professor Ali Javey Spring 2009 Exam 2 Name: SID: Closed book. One sheet of notes is allowed.

More information

Chapter 7. Plasma Basics

Chapter 7. Plasma Basics Chapter 7 Plasma Basics 2006/4/12 1 Objectives List at least three IC processes using plasma Name three important collisions in plasma Describe mean free path Explain how plasma enhance etch and CVD processes

More information

DEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD

DEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD Chapter 4 DEPOSITION OF THIN TiO 2 FILMS BY DC MAGNETRON SPUTTERING METHOD 4.1 INTRODUCTION Sputter deposition process is another old technique being used in modern semiconductor industries. Sputtering

More information

Introduction to Photolithography

Introduction to Photolithography http://www.ichaus.de/news/72 Introduction to Photolithography Photolithography The following slides present an outline of the process by which integrated circuits are made, of which photolithography is

More information

EE C247B / ME C218 INTRODUCTION TO MEMS DESIGN SPRING 2016 C. NGUYEN PROBLEM SET #4

EE C247B / ME C218 INTRODUCTION TO MEMS DESIGN SPRING 2016 C. NGUYEN PROBLEM SET #4 Issued: Wednesday, March 4, 2016 PROBLEM SET #4 Due: Monday, March 14, 2016, 8:00 a.m. in the EE C247B homework box near 125 Cory. 1. This problem considers bending of a simple cantilever and several methods

More information

Outline. 1 Introduction. 2 Basic IC fabrication processes. 3 Fabrication techniques for MEMS. 4 Applications. 5 Mechanics issues on MEMS 1 MDL NTHU

Outline. 1 Introduction. 2 Basic IC fabrication processes. 3 Fabrication techniques for MEMS. 4 Applications. 5 Mechanics issues on MEMS 1 MDL NTHU Outline 1 Introduction 2 Basic IC fabrication processes 3 Fabrication techniques for MEMS 4 Applications 5 Mechanics issues on MEMS 1 MDL 2. Basic IC fabrication processes 2.1 Deposition and growth 2.2

More information

ELEC 7364 Lecture Notes Summer Etching. by STELLA W. PANG. from The University of Michigan, Ann Arbor, MI, USA

ELEC 7364 Lecture Notes Summer Etching. by STELLA W. PANG. from The University of Michigan, Ann Arbor, MI, USA ELEC 7364 Lecture Notes Summer 2008 Etching by STELLA W. PANG from The University of Michigan, Ann Arbor, MI, USA Visiting Professor at The University of Hong Kong The University of Michigan on Visiting

More information

3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004

3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004 3.155J/6.152J Microelectronic Processing Technology Fall Term, 2004 Bob O'Handley Martin Schmidt Quiz Nov. 17, 2004 Ion implantation, diffusion [15] 1. a) Two identical p-type Si wafers (N a = 10 17 cm

More information

SILICON DIOXIDE TO POLYSILICON SELECTIVITY OF A C2F6/CHF3 DRY ETCH PROCESS

SILICON DIOXIDE TO POLYSILICON SELECTIVITY OF A C2F6/CHF3 DRY ETCH PROCESS SLCON DOXDE TO POLYSLCON SELECTVTY OF A C2F6/CHF3 DRY ETCH PROCESS Craig L. Kuhi 5th Year Microelectronic Engineering Student Rochester nstitute of Technology ABSTRACT The etch rates and selectivity of

More information

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Chenming Hu.

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Chenming Hu. UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Spring 2009 Professor Chenming Hu Midterm I Name: Closed book. One sheet of notes is

More information

nmos IC Design Report Module: EEE 112

nmos IC Design Report Module: EEE 112 nmos IC Design Report Author: 1302509 Zhao Ruimin Module: EEE 112 Lecturer: Date: Dr.Zhao Ce Zhou June/5/2015 Abstract This lab intended to train the experimental skills of the layout designing of the

More information

Thin Film Deposition. Reading Assignments: Plummer, Chap 9.1~9.4

Thin Film Deposition. Reading Assignments: Plummer, Chap 9.1~9.4 Thin Film Deposition Reading Assignments: Plummer, Chap 9.1~9.4 Thermally grown Deposition Thin Film Formation Thermally grown SiO 2 Deposition SiO 2 Oxygen is from gas phase Silicon from substrate Oxide

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Ali Javey. Spring 2009.

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Ali Javey. Spring 2009. UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE143 Professor Ali Javey Spring 2009 Exam 1 Name: SID: Closed book. One sheet of notes is allowed.

More information

EE143 Fall 2016 Microfabrication Technologies. Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6

EE143 Fall 2016 Microfabrication Technologies. Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6 EE143 Fall 2016 Microfabrication Technologies Lecture 6: Thin Film Deposition Reading: Jaeger Chapter 6 Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 Vacuum Basics Units 1 atmosphere

More information

Clean-Room microfabrication techniques. Francesco Rizzi Italian Institute of Technology

Clean-Room microfabrication techniques. Francesco Rizzi Italian Institute of Technology Clean-Room microfabrication techniques Francesco Rizzi Italian Institute of Technology Miniaturization The first transistor Miniaturization The first transistor Miniaturization The first transistor Miniaturization

More information

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C245 ME C218 Introduction to MEMS Design Fall 2008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 6: Process

More information

Figure 1: Graphene release, transfer and stacking processes. The graphene stacking began with CVD

Figure 1: Graphene release, transfer and stacking processes. The graphene stacking began with CVD Supplementary figure 1 Graphene Growth and Transfer Graphene PMMA FeCl 3 DI water Copper foil CVD growth Back side etch PMMA coating Copper etch in 0.25M FeCl 3 DI water rinse 1 st transfer DI water 1:10

More information

Inorganic Nomenclature

Inorganic Nomenclature Inorganic Nomenclature A. The Chemical Elements 1. The term INORGANIC NOMENCLATURE refers to the naming of elements and inorganic compounds. Recall that ELEMENTS are the simplest form of matter that cannot

More information

Etching Capabilities at Harvard CNS. March 2008

Etching Capabilities at Harvard CNS. March 2008 Etching Capabilities at Harvard CNS March 2008 CNS: A shared use facility for the Harvard Community and New England CNS Provides technical support, equipment and staff. Explicitly multi-disciplinary w/

More information

Film Deposition Part 1

Film Deposition Part 1 1 Film Deposition Part 1 Chapter 11 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Spring Semester 2013 Saroj Kumar Patra Semidonductor Manufacturing Technology, Norwegian University of

More information

Introduction to Plasma

Introduction to Plasma What is a plasma? The fourth state of matter A partially ionized gas How is a plasma created? Energy must be added to a gas in the form of: Heat: Temperatures must be in excess of 4000 O C Radiation Electric

More information

Copyright Warning & Restrictions

Copyright Warning & Restrictions Copyright Warning & Restrictions The copyright law of the United States (Title 17, United States Code) governs the making of photocopies or other reproductions of copyrighted material. Under certain conditions

More information

UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices

UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices 1 UHF-ECR Plasma Etching System for Dielectric Films of Next-generation Semiconductor Devices Katsuya Watanabe

More information

Equipment Innovation Team, Memory Fab. Center, Samsung Electronics Co. Ltd. San#16, Banwol, Taean, Hwansung, Kyungki, , Republic of Korea

Equipment Innovation Team, Memory Fab. Center, Samsung Electronics Co. Ltd. San#16, Banwol, Taean, Hwansung, Kyungki, , Republic of Korea Solid State Phenomena Vols. 103-104 (2005) pp 63-66 Online available since 2005/Apr/01 at www.scientific.net (2005) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/ssp.103-104.63 Development

More information

Plasma-Surface Interactions in Patterning High-k k Dielectric Materials

Plasma-Surface Interactions in Patterning High-k k Dielectric Materials Plasma-Surface Interactions in Patterning High-k k Dielectric Materials October 11, 4 Feature Level Compensation and Control Seminar Jane P. Chang Department of Chemical Engineering University of California,

More information

Section 5: Thin Film Deposition part 1 : sputtering and evaporation. Jaeger Chapter 6. EE143 Ali Javey

Section 5: Thin Film Deposition part 1 : sputtering and evaporation. Jaeger Chapter 6. EE143 Ali Javey Section 5: Thin Film Deposition part 1 : sputtering and evaporation Jaeger Chapter 6 Vacuum Basics 1. Units 1 atmosphere = 760 torr = 1.013x10 5 Pa 1 bar = 10 5 Pa = 750 torr 1 torr = 1 mm Hg 1 mtorr =

More information

A semiconductor is an almost insulating material, in which by contamination (doping) positive or negative charge carriers can be introduced.

A semiconductor is an almost insulating material, in which by contamination (doping) positive or negative charge carriers can be introduced. Semiconductor A semiconductor is an almost insulating material, in which by contamination (doping) positive or negative charge carriers can be introduced. Page 2 Semiconductor materials Page 3 Energy levels

More information

DEPOSITION AND COMPOSITION OF POLYMER FILMS IN FLUOROCARBON PLASMAS*

DEPOSITION AND COMPOSITION OF POLYMER FILMS IN FLUOROCARBON PLASMAS* DEPOSITION AND COMPOSITION OF POLYMER FILMS IN FLUOROCARBON PLASMAS* Kapil Rajaraman and Mark J. Kushner 1406 W. Green St. Urbana, IL 61801 rajaramn@uiuc.edu mjk@uiuc.edu http://uigelz.ece.uiuc.edu November

More information

ECE611 / CHE611: Electronic Materials Processing Fall 2017 John Labram Solutions to Homework 2 Due at the beginning of class Thursday October 19 th

ECE611 / CHE611: Electronic Materials Processing Fall 2017 John Labram Solutions to Homework 2 Due at the beginning of class Thursday October 19 th ECE611 / CHE611: Electronic Materials Processing Fall 017 John Labram Solutions to Homework Due at the beginning of class Thursday October 19 th Question 1 [3 marks]: a) Piranha solution consists of a

More information

SUPPLEMENTARY NOTES Supplementary Note 1: Fabrication of Scanning Thermal Microscopy Probes

SUPPLEMENTARY NOTES Supplementary Note 1: Fabrication of Scanning Thermal Microscopy Probes SUPPLEMENTARY NOTES Supplementary Note 1: Fabrication of Scanning Thermal Microscopy Probes Fabrication of the scanning thermal microscopy (SThM) probes is summarized in Supplementary Fig. 1 and proceeds

More information

Characteristics of Neutral Beam Generated by a Low Angle Reflection and Its Etch Characteristics by Halogen-Based Gases

Characteristics of Neutral Beam Generated by a Low Angle Reflection and Its Etch Characteristics by Halogen-Based Gases Characteristics of Neutral Beam Generated by a Low Angle Reflection and Its Etch Characteristics by Halogen-Based Gases Geun-Young Yeom SungKyunKwan University Problems of Current Etch Technology Scaling

More information

DO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT

DO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT DO NOT WRITE YOUR NAME OR KAUST ID NUMBER ON THIS PAGE OR ANY OTHER PAGE PUT YOUR EXAM ID NUMBER ON THIS PAGE AND EVERY OTHER PAGE YOU SUBMIT WRITE YOUR SOLUTIONS ON ONLY ONE SIDE OF EMPTY SOLUTION SHEETS

More information

Lecture 16 Chemical Mechanical Planarization

Lecture 16 Chemical Mechanical Planarization Lecture 16 Chemical Mechanical Planarization 1/75 Announcements Term Paper: The term paper should be handed in today: Tuesday 21 st November. The term paper will be returned to you in class on Tuesday

More information

Feature Profile Evolution during Shallow Trench Isolation (STI) Etch in Chlorine-based Plasmas

Feature Profile Evolution during Shallow Trench Isolation (STI) Etch in Chlorine-based Plasmas 1 Feature Profile Evolution during Shallow Trench Isolation (STI) Etch in Chlorine-based Plasmas Presentation November 14, 2005 Jane P. Chang and John Hoang Department of Chemical and Biomolecular Engineering

More information

Chapter 3 Engineering Science for Microsystems Design and Fabrication

Chapter 3 Engineering Science for Microsystems Design and Fabrication Lectures on MEMS and MICROSYSTEMS DESIGN and MANUFACTURE Chapter 3 Engineering Science for Microsystems Design and Fabrication In this Chapter, we will present overviews of the principles of physical and

More information

Ion Implantation. alternative to diffusion for the introduction of dopants essentially a physical process, rather than chemical advantages:

Ion Implantation. alternative to diffusion for the introduction of dopants essentially a physical process, rather than chemical advantages: Ion Implantation alternative to diffusion for the introduction of dopants essentially a physical process, rather than chemical advantages: mass separation allows wide varies of dopants dose control: diffusion

More information

Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications

Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications D. Tsoukalas, S. Kolliopoulou, P. Dimitrakis, P. Normand Institute of Microelectronics, NCSR Demokritos, Athens, Greece S. Paul,

More information

Introduction to Thin Film Processing

Introduction to Thin Film Processing Introduction to Thin Film Processing Deposition Methods Many diverse techniques available Typically based on three different methods for providing a flux of atomic or molecular material Evaporation Sputtering

More information

Inorganic Nomenclature

Inorganic Nomenclature Inorganic Nomenclature http://www.msu.edu/user/dynicrai/physics/h2o.htm A. The Chemical Elements 1. The term INORGANIC NOMENCLATURE refers to the naming of elements and inorganic compounds. Recall that

More information

Q1. The table below shows the boiling points of some hydrogen compounds formed by Group 6 elements. S H 2 O H 2. Boiling point / K

Q1. The table below shows the boiling points of some hydrogen compounds formed by Group 6 elements. S H 2 O H 2. Boiling point / K Q1. The table below shows the boiling points of some hydrogen compounds formed by Group 6 elements. H O H S H Se H Te Boiling point / K 373 1 3 71 (a) State the strongest type of intermolecular force in

More information

Chapter 6. Chemical Reactions. Sodium reacts violently with bromine to form sodium bromide.

Chapter 6. Chemical Reactions. Sodium reacts violently with bromine to form sodium bromide. Chapter 6 Chemical Reactions Sodium reacts violently with bromine to form sodium bromide. Evidence of Chemical Reactions Chemical Equations Reactants Products Reactant(s): Substance(s) present before the

More information

OPTI510R: Photonics. Khanh Kieu College of Optical Sciences, University of Arizona Meinel building R.626

OPTI510R: Photonics. Khanh Kieu College of Optical Sciences, University of Arizona Meinel building R.626 OPTI510R: Photonics Khanh Kieu College of Optical Sciences, University of Arizona kkieu@optics.arizona.edu Meinel building R.626 Announcements HW#3 is assigned due Feb. 20 st Mid-term exam Feb 27, 2PM

More information

Chapter 3 Basics Semiconductor Devices and Processing

Chapter 3 Basics Semiconductor Devices and Processing Chapter 3 Basics Semiconductor Devices and Processing Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Identify at least two

More information

Chapter 8 Ion Implantation

Chapter 8 Ion Implantation Chapter 8 Ion Implantation 2006/5/23 1 Wafer Process Flow Materials IC Fab Metalization CMP Dielectric deposition Test Wafers Masks Thermal Processes Implant PR strip Etch PR strip Packaging Photolithography

More information

NNCI Dry Etch Capabilities

NNCI Dry Etch Capabilities NNCI Site Tool Type Gases Application Wafer size Cornell Plasmatherm SF6, C4F8, O2, Ar Deep silicon etch 100mm Versaline ICP Deep Ge etch DSEIII SOI Cornell Unaxis 770 ICP SF6, C4F8, O2, Ar Deep silicon

More information

Removal of Cu Impurities on a Si Substrate by Using (H 2 O 2 +HF) and (UV/O 3 +HF)

Removal of Cu Impurities on a Si Substrate by Using (H 2 O 2 +HF) and (UV/O 3 +HF) Journal of the Korean Physical Society, Vol. 33, No. 5, November 1998, pp. 579 583 Removal of Cu Impurities on a Si Substrate by Using (H 2 O 2 +HF) and (UV/O 3 +HF) Baikil Choi and Hyeongtag Jeon School

More information

MICROCHIP MANUFACTURING by S. Wolf

MICROCHIP MANUFACTURING by S. Wolf by S. Wolf Chapter 15 ALUMINUM THIN-FILMS and SPUTTER-DEPOSITION 2004 by LATTICE PRESS CHAPTER 15 - CONTENTS Aluminum Thin-Films Sputter-Deposition Process Steps Physics of Sputter-Deposition Magnetron-Sputtering

More information

NAMING BINARY MOLECULAR COMPOUNDS

NAMING BINARY MOLECULAR COMPOUNDS CH 11 TOPIC 21 NAMING & WRITING MOLECULAR & ACIDS FORMULAE 1 You have mastered this topic when you can: 1) name and write formulae for simple MOLECULAR COMPOUNDS and ACIDS NAMING BINARY MOLECULAR COMPOUNDS

More information

Plasma Chemistry Study in an Inductively Coupled Dielectric Etcher

Plasma Chemistry Study in an Inductively Coupled Dielectric Etcher Plasma Chemistry Study in an Inductively Coupled Dielectric Etcher Chunshi Cui, John Trow, Ken Collins, Betty Tang, Luke Zhang, Steve Shannon, and Yan Ye Applied Materials, Inc. October 26, 2000 10/28/2008

More information

Semiconductor Technology

Semiconductor Technology Semiconductor Technology from A to Z Deposition www.halbleiter.org Contents Contents List of Figures II 1 Deposition 1 1.1 Plasma, the fourth aggregation state of a material............. 1 1.1.1 Plasma

More information

Supplementary Figure 1 Detailed illustration on the fabrication process of templatestripped

Supplementary Figure 1 Detailed illustration on the fabrication process of templatestripped Supplementary Figure 1 Detailed illustration on the fabrication process of templatestripped gold substrate. (a) Spin coating of hydrogen silsesquioxane (HSQ) resist onto the silicon substrate with a thickness

More information

Chemistry 112 Name Final Exam Form A Section December 17,

Chemistry 112 Name Final Exam Form A Section December 17, Chemistry 112 Name Final Exam Form A Section December 17, 2012 email IMPORTANT: On the scantron (answer sheet), you MUST clearly fill your name, your student number, section number, and test form (white

More information

IC Fabrication Technology

IC Fabrication Technology IC Fabrication Technology * History: 1958-59: J. Kilby, Texas Instruments and R. Noyce, Fairchild * Key Idea: batch fabrication of electronic circuits n entire circuit, say 10 7 transistors and 5 levels

More information

DQN Positive Photoresist

DQN Positive Photoresist UNIVESITY OF CALIFONIA, BEKELEY BEKELEY DAVIS IVINE LOS ANGELES IVESIDE SAN DIEGO SAN FANCISCO SANTA BABAA SANTA CUZ DEPATMENT OF BIOENGINEEING 94720-1762 BioE 121 Midterm #1 Solutions BEKELEY, CALIFONIA

More information

Make sure the exam paper has 9 pages (including cover page) + 3 pages of data for reference

Make sure the exam paper has 9 pages (including cover page) + 3 pages of data for reference UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Spring 2006 EE143 Midterm Exam #1 Family Name First name SID Signature Make sure the exam paper

More information

Semiconductor Integrated Process Design (MS 635)

Semiconductor Integrated Process Design (MS 635) Semiconductor Integrated Process Design (MS 635) Instructor: Prof. Keon Jae Lee - Office: 응용공학동 #4306, Tel: #3343 - Email: keonlee@kaist.ac.kr Lecture: (Tu, Th), 1:00-2:15 #2425 Office hour: Tues & Thur

More information

Patterning Challenges and Opportunities: Etch and Film

Patterning Challenges and Opportunities: Etch and Film Patterning Challenges and Opportunities: Etch and Film Ying Zhang, Shahid Rauf, Ajay Ahatnagar, David Chu, Amulya Athayde, and Terry Y. Lee Applied Materials, Inc. SEMICON, Taiwan 2016 Sept. 07-09, 2016,

More information

Etching terminology. d mask. h film. film substrate. d film. bias B. anisotropy A. etch mask. B d f - d m (i.e., twice the undercut) A film

Etching terminology. d mask. h film. film substrate. d film. bias B. anisotropy A. etch mask. B d f - d m (i.e., twice the undercut) A film Etching terminology h ilm d mask etch mask ilm substrate d mask bias B B d - d m (i.e., twice the undercut) anisotropy A d ilm d ilm A ilm 1 - v l / v v v l lateral etch rate v v vertical etch rate or

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

Ion Implant Part 1. Saroj Kumar Patra, TFE4180 Semiconductor Manufacturing Technology. Norwegian University of Science and Technology ( NTNU )

Ion Implant Part 1. Saroj Kumar Patra, TFE4180 Semiconductor Manufacturing Technology. Norwegian University of Science and Technology ( NTNU ) 1 Ion Implant Part 1 Chapter 17: Semiconductor Manufacturing Technology by M. Quirk & J. Serda Spring Semester 2014 Saroj Kumar Patra,, Norwegian University of Science and Technology ( NTNU ) 2 Objectives

More information