EE 505 Lecture 11. Statistical Circuit Modeling. R-string Example Offset Voltages
|
|
|
- Marcus Rogers
- 5 years ago
- Views:
Transcription
1 EE 505 Lecture 11 Statistical Circuit Modeling -string Example Offset oltages
2 eview from previous lecture: Current Steering DAC Statistical Characterization Binary Weighted IL b=< > 1 1 IGk 1 1 I LSBX FF XI n I1 S1 I S I3 S3 In Sn OUT ILMAX ILb=<1,0,...0> I I G LSBX ote this is the same result as obtained for the unary DAC But closed form expressions do not exist for the IL of this DAC since the IL is an order statistic
3 eview from previous lecture: Statistical Modeling of Current Sources I D I X GS Simple Square-Law MOSFET Model Usually Adequate for static Statistical Modeling Assumption: Layout used to eliminate gradient effects, contact resistance and drain/source resistance neglected μc W I = - L OX D GS TH andom ariables: µ, C OX, TH, W,L eed: I I D D Thus I D is a random variable
4 eview from previous lecture: Statistical Modeling of Current Sources 4 TH ID μ C I μ C GS TH D OX TH OX TH or I D μ C I μ C GS TH D OX TH OX It will be argued that μ μ C C OX OX T 0 TH A WL ACox WL A WL A µ,a Cox,A T0 are process parameters 1 4 A A A ID Cox T 0 I WL EB D Define A A A Cox Thus 1 4 A ID T 0 I WL EB D A Often only A β is available
5 eview from previous lecture: Statistical Modeling of Current Sources 1 4 A ID T 0 I WL EB D A Standard Deviation Decreases with Sqrt of A Large EB reduces standard deviation Operating near cutoff results in large mismatch Often threshold voltage variations dominate mismatch ID T 0 I EB WL D A
6 eview from previous lecture: Statistical Modeling of Circuits The previous statistical analysis was somewhat tedious Will try to formalize the process Assume Y is a function of n random variables x 1, x n where the mean and variance of x i are small Y = f x, x,... x 1 n n f Y = f X + x + x x x X 0 x,,... j1 j X 0 x x X =... x 1 n j 1 n where x, x,... x 1 n small
7 eview from previous lecture: Statistical Modeling of Circuits Alternatively, if we define S f xj = x Y i f x j X 0 we thus obtain n = f S Y xj x Y j1 x j i
8 eview from previous lecture:
9 eview from previous lecture:
10 eview from previous lecture: CDF showing random variable mapping of x 1 from U(0,1) 1 F x 1 x F -1 (x 1 )
11 Example: Determine the area required for the resistors for an n-bit -string DAC to achieve a yield of P if the device is marketable provided 1 IL kmax LSB Assume the area of each resistor is WL A A OM A WL
12 Since P is fixed, can solve for X
13 P F X 1 where F (X ) is the CDF on (0,1) 1 P 1 X F X 1 x 1 A WL X 1 X A WL WL A X 1 P 1 WL A F
14 1 P 1 WL A F WL A X Total area n n n n 3n TOT A WL A X A X A X A 3 n TOT A X or equivalently 3n 1 P 1 ATOT A F
15 Offset oltages All ADCs have comparators and many ADCs and DACs have operational amplifiers The offset voltages of both amplifiers and comparators are random variables and invariably are key factors affecting the performance of a data converter Operational Amplifiers: Generally differential amplifiers whose offset is dominantly determined by randomness in the first stage Comparators: High Gain Operational Amplifiers Latching Structures (often clocked) Combination of High Gain Amplifiers and Latching Structures Offset voltages of high-gain amplifiers well understood Offset voltage of Latching Structures often difficult to determine and can be very large
16 Consider First Offset in Operational Amplifiers Input-referred Offset oltage: Differential oltage that must be applied to the input to make the output assume its desired value ote: With a good design, a designer will have OUT at the desired value if the components assume the values used in the design Any difference in the output from what is desired when components assume the nominal values used in a design is attributable to a systematic offset voltage
17 O XX
18 Analysis of Offset oltage Since I I D1 D3 L C W 1 p3 OX S T1 X DD T 3 L3n 1C OX1W 1 Since I I D D4 L C W p4 OX 4 4 S Tn X DD Tp4 L4n COX W
19 Analysis of Offset oltage Define: L1 p3cox 3W3 a L C W 3 n1 OX1 1 b L C W p4 OX 4 4 L C W 4 n OX Substituting for a and b, it follows that b a a b OS 1 Tn Tn1 X DD Tp3 Tp4 Assume X X X a a a b b b Tni Tn Tni i 1, i 3,4 Tpi Tp Tpi Observe a =b and X - DD - Tp = EB3 It follows that b a a OS Tn Tn EB3 Tp3 Tp 4 a EB3 OS Tn Tp 3 a b Will now obtain a and b
20 Analysis of Offset oltage b a a OS Tn Tn EB3 Tp3 Tp 4 a L 1 L1 p3 3 COX 3 COX 3 W 3 W3 L L C C W W 3 3 n1 1 OX1 OX1 1 1 x ecall for x small, 1 x 1 Likewise b x x L W 1 L L C C W W a 1 L W L L C C W W Thus L 1 3W 3 p 1 L1 L C C W W a OX OX L n W L 1 L COX 3 COX 1 W 3 W 3 a 1 p OX 3 OX n p3 n1 OX 3 OX1 3 3 L L 1 p3 3 W W 3 n1 1 L W 1 L L C C W W L W L L C C W W 1 p OX 4 OX 4 3 n1 1 4 p4 n OX 4 OX 4
21 Analysis of Offset oltage a b L1 L L 4 L L 1p3W 3 1 L 1 L L 4 L 3 p3 p4 n n1 L W C C C C W W W W C C C C W W W W 3 n1 1 OX3 OX 4 OX OX OX 3 OX 4 OX OX L W 1 1 p3 3 a b L L C C W W 3 n1 1 L L C C W W L W OX OX 1 3 p3 n OX 3 OX Thus L W 1 p3 3 L 3n1W 1 OS Tn Tp 3 L W 1 1 p3 3 EB3 L L C C W W L 3n1W 1 L L C C W W OX 3 OX p3 n OX 3 OX1 3 1
22 Analysis of Offset oltage but A AT 0 ACox AL AW T C OX L W WL WL WL WL W L C L W OX So the offset variance can be expressed as L A ATn0 p 1 Tp0 OS W1L 1 nw1 L3 plw A A 1 1 n p EB 3 ACox AW AL nl3w 1 W3L3 W1L 1 W3L3 W1L 1 W3 L3 W1 L1 W1L 1 W3L3 Often this can be approximated by A 0 pl1 ATp 0 plw A Tn 1 1 n p OS EB3 ACox W1L 1 nw1 L3 nl3w 1 W3L3 W1L 1 W3L3 W1L 1 Or even approximated by L A ATn0 p 1 Tp0 OS W1L 1 nw1 L3 A
23 End of Lecture 11
24 Statistical Characterization of esistors some additional issue From previous model: OM A WL B W L B ote: Have neglected edge roughness, contact resistance interconnect resistance
EE 505 Lecture 10. Statistical Circuit Modeling
EE 505 Lecture 10 Statistical Circuit Modeling Amplifier Gain Accuracy eview from previous lecture: - + String DAC Statistical Performance eview from previous lecture: esistors are uncorrelated but identically
EE 505 Lecture 10. Statistical Circuit Modeling
EE 505 Lecture 10 Statistical Circuit Modeling mplifier Gain ccuracy eview from previous lecture: - + eview from previous lecture: String DC Statistical Performance 1 1 k k k ILk j 1 j 1 k 1 OM j1 1 1
EE 505. Lecture 11. Offset Voltages DAC Design
EE 505 Lecture 11 Offset Voltages DC Design Offset Voltages ll DCs have comparators and many DCs and DCs have operational amplifiers The offset voltages of both amplifiers and comparators are random variables
EE 505 Lecture 8. Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 8 Clock Jitter Statistical Circuit Modeling Spectral Characterization of Data Converters Distortion Analysis Time Quantization Effects of DACs of ADCs Amplitude Quantization Effects of DACs
EE 435. Lecture 22. Offset Voltages
EE 435 Lecture Offset Voltages . Review from last lecture. Offset Voltage Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output
EE 435. Lecture 38. DAC Design Current Steering DACs Charge Redistribution DACs ADC Design
EE 435 Lecture 38 DAC Design Current Steering DACs Charge edistribution DACs ADC Design eview from last lecture Current Steering DACs X N Binary to Thermometer ndecoder (all ON) S S N- S N V EF F nherently
EE 435. Lecture 22. Offset Voltages Common Mode Feedback
EE 435 Lecture Offset Voltages Common Mode Feedback Review from last lecture Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage V ICQ Definition: The output offset
ECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
EE 434 Lecture 33. Logic Design
EE 434 Lecture 33 Logic Design Review from last time: Ask the inverter how it will interpret logic levels V IN V OUT V H =? V L =? V LARGE V H V L V H Review from last time: The two-inverter loop X Y X
EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
Lecture 10, ATIK. Data converters 3
Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering
EE 435. Lecture 36. Quantization Noise ENOB Absolute and Relative Accuracy DAC Design. The String DAC
EE 435 Lecture 36 Quantization Noise ENOB Absolute and elative Accuracy DAC Design The String DAC . eview from last lecture. Quantization Noise in ADC ecall: If the random variable f is uniformly distributed
EE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
EE 508 Lecture 13. Statistical Characterization of Filter Characteristics
EE 508 Lecture 3 Statistical Characterization of Filter Characteristics Comonents used to build filters are not recisely redictable L C Temerature Variations Manufacturing Variations Aging Model variations
EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model
EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
EE 505 Lecture 7. Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 7 Spectral Performance of Data Converters - Time Quantization - Amplitude Quantization Clock Jitter Statistical Circuit Modeling . Review from last lecture. MatLab comparison: 512 Samples
EE 330 Lecture 36. Digital Circuits. Transfer Characteristics of the Inverter Pair One device sizing strategy Multiple-input gates
EE 330 Lecture 36 Digital Circuits Transfer Characteristics of the Inverter Pair One device sizing strategy Multiple-input gates Review from Last Time The basic logic gates It suffices to characterize
EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law
CMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices
EECS240 Spring 2008 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS echnology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 oday s Lecture
Lecture 400 Discrete-Time Comparators (4/8/02) Page 400-1
Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators
ELEN 610 Data Converters
Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power
ECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues
EE105 - Fall 006 Microelectronic evices and Circuits Prof. Jan M. Rabaey (jan@eecs Lecture 8: MOS Small Signal Model Some Administrative Issues REIEW Session Next Week Tu Sept 6 6:00-7:30pm; 060 alley
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
Biasing the CE Amplifier
Biasing the CE Amplifier Graphical approach: plot I C as a function of the DC base-emitter voltage (note: normally plot vs. base current, so we must return to Ebers-Moll): I C I S e V BE V th I S e V th
EE 435. Lecture 16. Compensation Systematic Two-Stage Op Amp Design
EE 435 Lecture 6 Compensation Systematic Two-Stage Op Amp Design Review from last lecture Review of Basic Concepts Pole Locations and Stability Theorem: A system is stable iff all closed-loop poles lie
EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
Practice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
D/A Converters. D/A Examples
D/A architecture examples Unit element Binary weighted Static performance Component matching Architectures Unit element Binary weighted Segmented Dynamic element matching Dynamic performance Glitches Reconstruction
PARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.2-1 10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS CLASSIFICATION OF DIGITAL-ANALOG CONVERTERS CMOS Analog IC Design Page 10.2-2 CURRENT SCALING DIGITAL-ANALOG CONVERTERS GENERAL
EE 330 Lecture 31. Current Source Biasing Current Sources and Mirrors
EE 330 Lecture 31 urrent Source Biasing urrent Sources and Mirrors eview from Last Lecture Basic mplifier Gain Table DD DD DD DD in B E out in B E out E B BB in E out in B E E out in 2 D Q EE SS E/S /D
In this lecture, we will consider how to analyse an electrical circuit by applying KVL and KCL. As a result, we can predict the voltages and currents
In this lecture, we will consider how to analyse an electrical circuit by applying KVL and KCL. As a result, we can predict the voltages and currents around an electrical circuit. This is a short lecture,
Random Offset in CMOS IC Design
Random Offset in CMOS C esign ECEN487/587 Analog C esign October 19, 007 Art Zirger, National Semiconductor art.zirger@nsc.com 303-845-404 Where to start? How do we choose what transistor sizes to use
The Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
Lecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1
Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog
ECE 342 Electronic Circuits. Lecture 35 CMOS Delay Model
ECE 34 Electronic Circuits Lecture 35 CMOS Delay Model Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances
EE 435 Lecture 37 Parasitic Capacitances in MOS Devices String DAC Parasitic Capacitances Parasitic Capacitors in MOSFET (will initially consider two) Parasitic Capacitors in MOSFET C GCH Parasitic Capacitors
EE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods
EE 230 Lecture 20 Nonlinear Op Amp Applications The Comparator Nonlinear Analysis Methods Quiz 14 What is the major purpose of compensation when designing an operatinal amplifier? And the number is? 1
Digital to Analog Converters I
Advanced Analog Building Blocks 2 Digital to Analog Converters I Albert Comerma (PI) (comerma@physi.uni-heidelberg.de) Course web WiSe 2017 DAC parameters DACs parameters DACs non ideal effects DACs performance
A novel Capacitor Array based Digital to Analog Converter
Chapter 4 A novel Capacitor Array based Digital to Analog Converter We present a novel capacitor array digital to analog converter(dac architecture. This DAC architecture replaces the large MSB (Most Significant
Chapter 2 MOS Transistor theory
Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the
EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOFET Modeling CMO Process Flow Review from Last Lecture Limitations of Existing Models V V OUT V OUT V?? V IN V OUT V IN V IN V witch-level Models V imple square-law Model Logic ate
Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION
ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
ECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
Frequency Detection of CDRs (1)
Frequency Detection of CDs (1) ecall that faster PLL locking can be accomplished by use of a phase-frequency detector (PFD): V in V up V up V dn -4 π -2 π +2 π +4 π φ in φ out 2V swing V f V dn K pd =
Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
VLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter First-Order DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
EE 330 Lecture 25. Small Signal Modeling
EE 330 Lecture 25 Small Signal Modeling Review from Last Lecture Amplification with Transistors From Wikipedia: Generall, an amplifier or simpl amp, is an device that changes, usuall increases, the amplitude
MOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
CMOS Digital Integrated Circuits Lec 13 Semiconductor Memories
Lec 13 Semiconductor Memories 1 Semiconductor Memory Types Semiconductor Memories Read/Write (R/W) Memory or Random Access Memory (RAM) Read-Only Memory (ROM) Dynamic RAM (DRAM) Static RAM (SRAM) 1. Mask
Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.
Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to
Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
EE 330 Lecture 37. Digital Circuits. Other Logic Families. Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates)
EE 330 Lecture 37 Digital Circuits Other Logic Families Static Power Dissipation Propagation Delay basic characterization Device Sizing (Inverter and multiple-input gates) Review from Last Time Inverter
EE 505 Lecture 9. Statistical Circuit Modeling
EE 505 Lecture 9 Statistical Circuit Modelig eview from previous lecture: Statistical Aalysis Strategy Will first focus o statistical characterizatio of resistors, the exted to capacitors ad trasistors
CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process
EECS240 Spring 202 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS Technology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 Today s Lecture
High-to-Low Propagation Delay t PHL
High-to-Low Propagation Delay t PHL V IN switches instantly from low to high. Driver transistor (n-channel) immediately switches from cutoff to saturation; the p-channel pull-up switches from triode to
EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically
ECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
ESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 017 Final Wednesday, May 3 4 Problems with point weightings shown.
ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION
ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may
P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions
P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the
At point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
EE 330 Lecture 18. Small-signal Model (very preliminary) Bulk CMOS Process Flow
EE 330 Lecture 18 Small-signal Model (very preliminary) Bulk CMOS Process Flow Review from Last Lecture How many models of the MOSFET do we have? Switch-level model (2) Square-law model Square-law model
Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata nd Ed. (0/9/07) Page Errata of CMOS Analog Circuit Design nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 8 Line 4 after figure 3.3, CISW CJSW 0 Line from bottom: F F 5 Replace
and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
ECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology
EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor
Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1
Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits
EE 435. Lecture 44. References
EE 5 Lecture eferences . eview from last lecture. Consider oltage eferences DD M BIAS oltage eference Circuit EF EF M DD, T reference EF DD T 0 WL WL W L W L Observation ariables with units olts needed
Lecture 12 Circuits numériques (II)
Lecture 12 Circuits numériques (II) Circuits inverseurs MOS Outline NMOS inverter with resistor pull-up The inverter NMOS inverter with current-source pull-up Complementary MOS (CMOS) inverter Static analysis
Lecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
CMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators
IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater
EE 434 Lecture 34. Logic Design
EE 434 ecture 34 ogic Design Review from last time: Transfer characteristics of the static CMOS inverter (Neglect λ effects) Case 5 M cutoff, M triode V -V > V -V -V Tp V < V Tn V V V Tp Transfer characteristics
Electronics II. Midterm #2
The University of Toledo EECS:3400 Electronics I Section sums_elct7.fm - StudentName Electronics II Midterm # Problems Points. 8. 3. 7 Total 0 Was the exam fair? yes no The University of Toledo sums_elct7.fm
Edited By : Engr. Muhammad Muizz bin Mohd Nawawi
Edited By : Engr. Muhammad Muizz bin Mohd Nawawi In an electronic circuit, a combination of high voltage (+5V) and low voltage (0V) is usually used to represent a binary number. For example, a binary number
Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1
Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop
EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
EE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
Lecture 28 Field-Effect Transistors
Lecture 8 Field-Effect Transistors Field-Effect Transistors 1. Understand MOSFET operation.. Analyze basic FET amplifiers using the loadline technique. 3. Analyze bias circuits. 4. Use small-signal equialent
Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg
Errata 2 nd Ed. (5/22/2) Page Errata of CMOS Analog Circuit Design 2 nd Edition By Phillip E. Allen and Douglas R. Holberg Page Errata 82 Line 4 after figure 3.2-3, CISW CJSW 88 Line between Eqs. (3.3-2)
P-MOS Device and CMOS Inverters
Lecture 23 P-MOS Device and CMOS Inverters A) P-MOS Device Structure and Oeration B) Relation of Current to t OX, µ V LIMIT C) CMOS Device Equations and Use D) CMOS Inverter V OUT vs. V IN E) CMOS Short
ECE 342 Solid State Devices & Circuits 4. CMOS
ECE 34 Solid State Devices & Circuits 4. CMOS Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu ECE 34 Jose Schutt Aine 1 Digital Circuits V IH : Input
2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
University of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
Lecture Notes 7 Fixed Pattern Noise. Sources of FPN. Analysis of FPN in PPS and APS. Total Noise Model. Correlated Double Sampling
Lecture Notes 7 Fixed Pattern Noise Definition Sources of FPN Analysis of FPN in PPS and APS Total Noise Model Correlated Double Sampling EE 392B: Fixed Pattern Noise 7-1 Fixed Pattern Noise (FPN) FPN
Chapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
EE 435. Lecture 26. Data Converters. Data Converter Characterization
EE 435 Lecture 26 Data Converters Data Converter Characterization . Review from last lecture. Data Converter Architectures Large number of different circuits have been proposed for building data converters
Chapter 6: Field-Effect Transistors
Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled
Analog and Telecommunication Electronics
Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D2 - DAC taxonomy and errors» Static and dynamic parameters» DAC taxonomy» DAC circuits» Error sources AY 2015-16
Kirchhoff's Laws and Circuit Analysis (EC 2)
Kirchhoff's Laws and Circuit Analysis (EC ) Circuit analysis: solving for I and V at each element Linear circuits: involve resistors, capacitors, inductors Initial analysis uses only resistors Power sources,
Lecture 14 - Digital Circuits (III) CMOS. April 1, 2003
6.12 - Microelectronic Devices and Circuits - Spring 23 Lecture 14-1 Lecture 14 - Digital Circuits (III) CMOS April 1, 23 Contents: 1. Complementary MOS (CMOS) inverter: introduction 2. CMOS inverter:
Integrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
Power Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
Nyquist-Rate D/A Converters. D/A Converter Basics.
Nyquist-Rate D/A Converters David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 20 D/A Converter Basics. B in D/A is a digital signal (or word), B in b i B in = 2 1