Lecture Notes 7 Fixed Pattern Noise. Sources of FPN. Analysis of FPN in PPS and APS. Total Noise Model. Correlated Double Sampling
|
|
- Charles Davidson
- 6 years ago
- Views:
Transcription
1 Lecture Notes 7 Fixed Pattern Noise Definition Sources of FPN Analysis of FPN in PPS and APS Total Noise Model Correlated Double Sampling EE 392B: Fixed Pattern Noise 7-1
2 Fixed Pattern Noise (FPN) FPN (also called nonuniformity) isthespatialvariationinpixeloutput values under uniform illumination due to device and interconnect parameter variations (mismatches) across the sensor It is fixed for a given sensor, but varies from sensor to sensor, so if v o is the nominal pixel output value (at unifrom illumination), and the output pixel values (excluding temporal noise) from the sensor are v ij for 1 i n and 1 j m, thenthefixedpatternnoiseisthesetofvalues v oij = v oij v o FPN consists of offset and gain components increases with illumination, but causes more degradation in image quality at low illumination FPN for CCD image sensors appears random CMOS (PPS and APS) sensors have higher FPN than CCDs and suffer from column FPN, which appears as stripes in the image and can result in significant image quality degradation EE 392B: Fixed Pattern Noise 7-2
3 FPN Images For CCD sensor For CMOS sensor EE 392B: Fixed Pattern Noise 7-3
4 Sources of FPN CCD image sensors only suffer from pixel FPN due to spatial variation in photodetector device parameters and dark current neither the CCDs nor the output amplifier (which is shared by all pixels) cause FPN (additional nonuniformity can result if more than one output amplifier is used, however) In CMOS image sensors pixel transistors cause additional pixel FPN and column amplifiers cause column FPN. As a result FPN is in general higher than in CCDs EE 392B: Fixed Pattern Noise 7-4
5 Main sources of FPN in PPS: i dc A D v T,C ol C f v o v REF + v op os Pixel FPN is mainly due to the variation in the photodetector parameters (e.g., area A D )anddarkcurrent Column FPN is due to the variation in the column amplifier parameters, e.g., offset voltage vos, op feedbackcapacitorvalue,reset transistor threshold voltage and overlap capacitance value C ol EE 392B: Fixed Pattern Noise 7-5
6 In APS v DD v DD v TR, C olr i dc v TF, W F L F A D C D v o i bias In addition to variation in the photodetector parameters and dark current, pixel FPN is caused also by variations in transistor parameters Column FPN is mainly due to variation i bias EE 392B: Fixed Pattern Noise 7-6
7 PPS and APS FPN APS suffers from higher pixel FPN than PPS but PPS generally suffers from higher column FPN PPS APS EE 392B: Fixed Pattern Noise 7-7
8 Quantifying FPN FPN is quantified by the standard deviation of the spatial variation in pixel outputs under uniform illumination (not including temporal noise). It is typically reported as a % of voltage swing (or well capacity) FPN standard deviation values of < 0.1% to > 4% of well capacity have been reported Experimentally, FPN is measured as follows: Set a constant uniform illumination level (including no illumination) Take many images For each pixel compute the average output value (to average out temporal noise) Estimate the standard deviation of the average pixel values Repeat the procedure for several uniform illumination levels EE 392B: Fixed Pattern Noise 7-8
9 Analysis of FPN Suppose we are given the standard deviation of each parameter that casues FPN, we now show how to compute its contribution to the total FPN Assume the parameter values to be random variables Z 1,Z 2,..., Z k expressed as Z i = z i + Z i, where z i is the mean of Z i (i.e., nominal value of the device parameter) and Z i is the variation of Z i from its mean, and has zero mean and standard deviation σ Zi Assuming sufficiently small device parameter variations, we can approximate the pixel output voltage (for a given illumination) as a function of the device parameters using the Taylor series expansion, as V o (Z 1,Z 2,...,Z k ) v o (z 1,z 2,...z k )+ k i=1 v o z i z1,z 2,...z k Z i EE 392B: Fixed Pattern Noise 7-9
10 where v o (z 1,z 2,...z k ) is the nominal output voltage and v o / z i is the sensitivity of v o w.r.t. the ith parameter (evaluated at the nominal parameter values) So the variation in V o can be represented by the random variable k v o z1 V o = Z i z i,z 2,...z k i=1 To quantify FPN, we find the standard deviation of the output voltage, σ Vo, i.e., the standard deviation of the r.v. V o Assuming that the Z i sareuncorrelated(maynotbeagoodassumption in general), we can write σ Vo = k ( vo ) 2 z1 σz 2 z i,z 2,...z i k i=1 EE 392B: Fixed Pattern Noise 7-10
11 Column and Pixel FPN For a CMOS (PPS or APS) image sensor, let the column device parameters be Z 1, Z 2,..., Z l and the rest be the pixel device parameters, we can define the column variation as and the pixel variation as Y = X = l i=1 k i=l+1 v o z i z1,z 2,...z k Z i v o z i z1,z 2,...z k Z i We quantify column FPN by σ Y and pixel FPN by σ X (vary with illumination) Since (by assumption) X and Y are uncorrelated σ 2 V o = σ 2 Y + σ 2 X EE 392B: Fixed Pattern Noise 7-11
12 Offset and Gain FPN The pixel output voltage v o and FPN σ Vo vary with illumination The nominal output voltage from a pixel can be expressed in terms of the photocurrent density as v o = hj ph + v os where h is the pixel gain in V cm 2 /A (not to be confused with sensor conversion gain g) andv os is the pixel offset (which includes the dark signal as well as the offset voltages due to the amplifiers used, e.g., v op os for PPS) Assuming all photodetectors have the same QE, and thus under uniform illumination, they have the same photocurrent density, we can now write the pixel output voltage variation as V o = ( k i=1 h z i z1,z 2,...z k Z i = Hj ph + V os ) j ph + ( k i=1 v os z i z1,z 2,...z k Z i ) EE 392B: Fixed Pattern Noise 7-12
13 We quantify offset FPN by σ Vos and gain FPN by σ H j ph Offest FPN is reported as % of well capacity Gain FPN is referred to as Pixel Response Nonuniformity (PRNU) and is reported as % of gain factor variation, i.e., 100σ H /h Note that H and V os are not necessarily uncorrelated, since some device parameters can affect both offset and gain EE 392B: Fixed Pattern Noise 7-13
14 Analysis of FPN in PPS The figure shows the device parameters considered i dc A D vt,c ol C f v o v REF + v op os A D is the photodiode area, i dc is its dark current, v op os is the opamp offset voltage, C ol is the overlap capacitance, and v T is the threshold voltage EE 392B: Fixed Pattern Noise 7-14
15 The output voltage in steady state is given by 1 v o =(Q + C ol v T ) + v REF + v C os, op f where C ol v T is the feedthrough charge (when the reset transistor is turned off), and the charge Q accumulated on the photodiode capacitance Q =(j ph A D + i dc )t int The following table lists the absolute values of the parameter senitivities and effect on FPN v o z i Parameter Sensitivity Effect on FPN A D t int C j ph f pixel/gain pixel/offset i dc v op C f t int C f os 1 column/offset column/offset v T C ol i dc t int +C ol v T Cf 2 + A Dt int Cf 2 C ol C f v T C f j ph column/gain column/offset column/offset EE 392B: Fixed Pattern Noise 7-15
16 Offset FPN σ Vos = ( t int σ idc C f ) 2 + σ 2 v op os + (( ) ) 2 ( ) 2 ( ) 2 i dc t int + C ol v T vt Col Cf 2 σ Cf + σ Col + σ vt C f C f Gain FPN σ H j ph = j ( ) ( ) 2 2 t int A D t int ph σ AD + C f Cf 2 σ Cf Pixel FPN Column FPN σ X = (jph t int C f σ AD ) 2 + ( ) 2 tint σ idc C f (( ) ) 2 σ Y = σ 2 vos op + i dc t int + C ol v T + A D j ph t int Cf 2 σ Cf + ( ) 2 ( ) 2 vt Col σ Col + σ vt C f C f Note that the FPN variance σv 2 o = σx 2 + σ2 Y can be written as the sum of three terms, a term that is independent of the signal, a term that increases linearly with the signal, and a term that increases quadratically with the signal EE 392B: Fixed Pattern Noise 7-16
17 Example Assume the following device parameter means, standard deviations, and that t int =30ms Parameter Mean σ Sensitivity A D 50µm 2 0.4%A D j ph V/µm 2 i dc 5fA 2%i dc 1.5mV/fA vos op 0V 2mV 1 C f 20fF 0.2%C f V/F 37500j ph V/fF v TR 0.8V 0.2%v TR 0.02 C ol 0.4fF 0.4%C ol 0.04V/fF EE 392B: Fixed Pattern Noise 7-17
18 Offset FPN and Parameter Contribution to σ Vos i dc 0.15 mv vos op 2 mv C f mv v TR mv mv C ol σ Vos 2mV, which is basically equal to the opamp offset σ v op os value Gain FPN at j ph = A/cm 2 (high illumination) Parameter Contribution to σ H j ph A D 7.92 mv 3.96 mv C f and σ H j ph =8.85mV EE 392B: Fixed Pattern Noise 7-18
19 The following figure plots total FPN σ Vo, pixel FPN σ X, and column FPN σ Y,assumingmonochromaticilluminationF 0 photons/cm 2.s at quantum efficiency QE = Pixel FPN Column FPN Total FPN FPN (mv) illumination F o (photon/cm 2 s) EE 392B: Fixed Pattern Noise 7-19
20 Analysis of FPN in APS v DD v DD v TR, C olr i dc v TF, W F L F A D C D v o i bias In steady state and assuming soft reset, the output voltage is given by ( v o = v DD v TR Q ) 2LF v TF + i bias, C D k n W F where the charge accumulted on the photodiode is given by Q =(A D j ph + i dc )t int + C olr v DD The C olr v DD term is the feedthrough charge (when the reset transistor is turned off) EE 392B: Fixed Pattern Noise 7-20
21 Example Consider the following parameter means and standard deviations parameter mean σ effect on FPN i dc 5fA 2%i dc pixel/offset A D 50µm 2 0.4%A D pixel/gain C D 20fF 0.4%C D pixel/offset,gain v TR 1.1V 0.2%v TR pixel/offset C olr 0.4fF 0.4%C olr pixel/pffset v TF 0.9V 0.2%v TF pixel/offset W F L F % W F L F pixel/offset i bias 1.88µA 1%i bias column/offset You will compute the FPN component values in the homework EE 392B: Fixed Pattern Noise 7-21
22 Image Sensor Total Noise Model Combining temporal noise and FPN, we can express the total input referred noise charge as where Q n = Q shot + Q reset + Q readout + Q fpn, Q shot is the r.v. representing the noise charge due to photodetector photo and dark current shot noise and is Gaussian with zero mean and variance 1 q (i ph + i dc )t int electrons 2 Q reset is the r.v. representing the reset noise and is basically independent of the signal Q readout is the r.v. representing the readout circuit noise (possibly including quantization) and is basically independent of the signal EE 392B: Fixed Pattern Noise 7-22
23 Q fpn is the r.v. representing FPN (in electrons), and can be represented either as a sum of pixel and column components Q fpn = 1 g (X + Y ) where g is the sensor conversion gain in V/electron, or offset and gain components Q fpn = 1 g ( Hj ph + V os ) Thus it has one component that is independent of signal and one that grows with the signal The noise components are assumed independent Thus the total average noise power is the sum of three components: One that does not depend on the signal (due to reset and readout noise and offset FPN) One that increases linearly with the signal (i ph or j ph )(duetoshot noise and gain FPN) One that increases quadratically with the signal (due to gain FPN) EE 392B: Fixed Pattern Noise 7-23
24 Noise as Function of Photocurrent 10 3 Average Noise power (V 2 ) i ph (A) EE 392B: Fixed Pattern Noise 7-24
25 Correlated Double Sampling (CDS) CDS is a multiple sampling technique commonly used in image sensors to reduce FPN, and reset and 1/f noise You sample the output twice; once right after reset and a second time with the signal present. The output signal is the difference between the two samples CDS only reduces offset FPN (does not reduce gain FPN) CDS does not cancel offset FPN due to dark current variation In CCDs, PPS, photogate and pinned diode APS, CDS cancels reset noise. In photodiode APS it increases it EE 392B: Fixed Pattern Noise 7-25
26 CDS in PPS Word Reset SS SR C os C or Reset SR Word, SS EE 392B: Fixed Pattern Noise 7-26
27 Cancells FPN due to vos, op v T,andC ol Temporal noise due to reset (terms Vo2 2 and V o3 2 Readout noise due to op-amp 1/f noise Does not cancel Adds in our analysis) Offset FPN due to i dc variation. This is called Dark Signal Non-uniformity (DSNU) Gain FPN (or PRNU) Other temporal noise components Opamp noise due to reset read (Vo4 2 term) noise due to SS and SR transistors KT C EE 392B: Fixed Pattern Noise 7-27
28 To summarize, the total noise charge for the two samples are given by: Q n1 = Q reset + Q read1 + Q fpn1 Q n2 = Q shot + Q reset + Q readout2 + Q fpn2 Note that Q fpn1 is simply an offset FPN whereas Q fpn2 is the sum of offset and gain FPN (PRNU). However, Q fpn1 does not include the offset FPN due to dark current variation (DSNU), whereas the offset part of Q fpn1 includes it The difference between the two samples is thus: Q n2 Q n1 = Q shot +(Q readout2 Q readout1 )+Q prnu + Q dsnu EE 392B: Fixed Pattern Noise 7-28
29 PPS FPN With and Without CDS The following figure plots PPS FPN with and without CDS (assuming that v op os, v T,andC ol are eliminated) 10 9 CDS w/o CDS FPN (mv) illumination F o (photon/cm 2 s) EE 392B: Fixed Pattern Noise 7-29
30 PPS Offset FPN With and Without CDS without CDS with CDS EE 392B: Fixed Pattern Noise 7-30
31 CDS in 3T APS Reset SS Word SR C os C or Word SS Reset SR EE 392B: Fixed Pattern Noise 7-31
32 Cancells All offset FPN terms involving v TR, v TF, C olr, W F L F,andi bias Does not cancel Adds DSNU Reset noise PRNU Readout noise Reset noise kt 2C D (reset noise component during reset readout independent of that during signal readout) Readout noise during reset readout kt C due to SS and SR transistors EE 392B: Fixed Pattern Noise 7-32
33 To summarize, the total noise charge for the two samples are given by: The difference is: Q n1 = Q shot + Q reset1 + Q readout1 + Q fpn1 Q n2 = Q reset2 + Q readout2 + Q fpn2 Q n1 Q n2 = Q shot +(Q reset1 Q reset2 )+(Q read1 Q read2 )+Q prnu + Q dsnu An important advantage of photogate and pinned diode APS is that reset noise is eliminated using CDS instead of doubled EE 392B: Fixed Pattern Noise 7-33
E18 DR. Giorgio Mussi 14/12/2018
POLITECNICO DI MILANO MSC COURSE - MEMS AND MICROSENSORS - 2018/2019 E18 DR Giorgio Mussi 14/12/2018 In this class we will define and discuss an important parameter to characterize the performance of an
More informationLast Name Minotti Given Name Paolo ID Number
Last Name Minotti Given Name Paolo ID Number 20180131 Question n. 1 Draw and describe the simplest electrical equivalent model of a 3-port MEMS resonator, and its frequency behavior. Introduce possible
More informationLecture Notes 2 Charge-Coupled Devices (CCDs) Part I. Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis
Lecture Notes 2 Charge-Coupled Devices (CCDs) Part I Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis Charge Well Capacity Buried channel CCD Transfer Efficiency Readout Speed
More informationLecture 320 Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1
Lecture 32 Improved OpenLoop Comparators and es (3/28/1) Page 321 LECTURE 32 IMPROVED OPENLOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline Autozeroing Hysteresis Simple es Summary CMOS Analog
More informationEstimation and Modeling of the Full Well Capacity in Pinned Photodiode CMOS Image Sensors
Estimation and Modeling of the Full Well Capacity in Pinned Photodiode CMOS Image Sensors Alice Pelamatti, Vincent Goiffon, Magali Estribeau, Paola Cervantes, Pierre Magnan To cite this version: Alice
More informationEE 435. Lecture 22. Offset Voltages
EE 435 Lecture Offset Voltages . Review from last lecture. Offset Voltage Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output
More informationLecture 400 Discrete-Time Comparators (4/8/02) Page 400-1
Lecture 400 DiscreteTime omparators (4/8/02) Page 4001 LETURE 400 DISRETETIME OMPARATORS (LATHES) (READING: AH 475483) Objective The objective of this presentation is: 1.) Illustrate discretetime comparators
More informationEE 435. Lecture 22. Offset Voltages Common Mode Feedback
EE 435 Lecture Offset Voltages Common Mode Feedback Review from last lecture Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage V ICQ Definition: The output offset
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationLecture 310 Open-Loop Comparators (3/28/10) Page 310-1
Lecture 310 Open-Loop Comparators (3/28/10) Page 310-1 LECTURE 310 OPEN-LOOP COMPARATORS LECTURE ORGANIZATION Outline Characterization of comparators Dominant pole, open-loop comparators Two-pole, open-loop
More information5.0 CMOS Inverter. W.Kucewicz VLSICirciuit Design 1
5.0 CMOS Inverter W.Kucewicz VLSICirciuit Design 1 Properties Switching Threshold Dynamic Behaviour Capacitance Propagation Delay nmos/pmos Ratio Power Consumption Contents W.Kucewicz VLSICirciuit Design
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More informationLecture 7 MOS Capacitor
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 7 MOS Capacitor Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030
More informationSample-and-Holds David Johns and Ken Martin University of Toronto
Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters
More informationResearch Article Evaluation of the Degradation on a COTS Linear CCD Induced by Total Ionizing Dose Radiation Damage
Sensors Volume 216, Article ID 96442, 6 pages http://dx.doi.org/1.1155/216/96442 Research Article Evaluation of the Degradation on a COTS Linear CCD Induced by Total Ionizing Dose Radiation Damage Zujun
More informationAdvances in Radio Science
Advances in Radio Science, 3, 331 336, 2005 SRef-ID: 1684-9973/ars/2005-3-331 Copernicus GmbH 2005 Advances in Radio Science Noise Considerations of Integrators for Current Readout Circuits B. Bechen,
More informationHow we wanted to revolutionize X-ray radiography, and how we then "accidentally" discovered single-photon CMOS imaging
How we wanted to revolutionize X-ray radiography, and how we then "accidentally" discovered single-photon CMOS imaging Stanford University EE Computer Systems Colloquium February 23 rd, 2011 EE380 Peter
More informationEE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods
EE 230 Lecture 20 Nonlinear Op Amp Applications The Comparator Nonlinear Analysis Methods Quiz 14 What is the major purpose of compensation when designing an operatinal amplifier? And the number is? 1
More informationOPAMPs I: The Ideal Case
I: The Ideal Case The basic composition of an operational amplifier (OPAMP) includes a high gain differential amplifier, followed by a second high gain amplifier, followed by a unity gain, low impedance,
More informationLast Name _Piatoles_ Given Name Americo ID Number
Last Name _Piatoles_ Given Name Americo ID Number 20170908 Question n. 1 The "C-V curve" method can be used to test a MEMS in the electromechanical characterization phase. Describe how this procedure is
More informationCMOS Comparators. Kyungpook National University. Integrated Systems Lab, Kyungpook National University. Comparators
IsLab Analog Integrated ircuit Design OMP-21 MOS omparators כ Kyungpook National University IsLab Analog Integrated ircuit Design OMP-1 omparators A comparator is used to detect whether a signal is greater
More informationSWITCHED CAPACITOR AMPLIFIERS
SWITCHED CAPACITOR AMPLIFIERS AO 0V 4. AO 0V 4.2 i Q AO 0V 4.3 Q AO 0V 4.4 Q i AO 0V 4.5 AO 0V 4.6 i Q AO 0V 4.7 Q AO 0V 4.8 i Q AO 0V 4.9 Simple amplifier First approach: A 0 = infinite. C : V C = V s
More informationDesign of Analog Integrated Circuits
Design of Analog Integrated Circuits Chapter 11: Introduction to Switched- Capacitor Circuits Textbook Chapter 13 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4
More information2007 Fall: Electronic Circuits 2 CHAPTER 10. Deog-Kyoon Jeong School of Electrical Engineering
007 Fall: Electronic Circuits CHAPTER 10 Digital CMOS Logic Circuits Deog-Kyoon Jeong dkjeong@snu.ac.kr k School of Electrical Engineering Seoul lnational luniversity it Introduction In this chapter, we
More informationEffects of Transfer Gate Spill Back in Low Light High Performances CMOS Image Sensors
Effects of Transfer Gate Spill Back in Low Light High Performances CMOS Image Sensors Photon Counting, Low Flux and High Dynamic Range Optoelectronic Detectors Workshop Toulouse 17th November 2016 Julien
More informationCARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130
ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED
More informationECE 6412, Spring Final Exam Page 1
ECE 64, Spring 005 Final Exam Page FINAL EXAMINATION SOLUTIONS (Average score = 89/00) Problem (0 points This problem is required) A comparator consists of an amplifier cascaded with a latch as shown below.
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationFinal Exam. 55:041 Electronic Circuits. The University of Iowa. Fall 2013.
Final Exam Name: Max: 130 Points Question 1 In the circuit shown, the op-amp is ideal, except for an input bias current I b = 1 na. Further, R F = 10K, R 1 = 100 Ω and C = 1 μf. The switch is opened at
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD S D V in V out C L D S CMOS Inverter N Well V DD V DD PMOS 2λ PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND CMOS Inverter: Steady State Response V
More informationEEE 421 VLSI Circuits
EEE 421 CMOS Properties Full rail-to-rail swing high noise margins» Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless Always a path to V dd or GND in steady
More informationEE 321 Analog Electronics, Fall 2013 Homework #3 solution
EE 32 Analog Electronics, Fall 203 Homework #3 solution 2.47. (a) Use superposition to show that the output of the circuit in Fig. P2.47 is given by + [ Rf v N + R f v N2 +... + R ] f v Nn R N R N2 R [
More informationChoice of V t and Gate Doping Type
Choice of V t and Gate Doping Type To make circuit design easier, it is routine to set V t at a small positive value, e.g., 0.4 V, so that, at V g = 0, the transistor does not have an inversion layer and
More informationEE C245 ME C218 Introduction to MEMS Design
EE C45 ME C18 Introduction to MEMS Design Fall 008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 6: Output
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationECEN 326 Electronic Circuits
ECEN 326 Electronic Circuits Stability Dr. Aydın İlker Karşılayan Texas A&M University Department of Electrical and Computer Engineering Ideal Configuration V i Σ V ε a(s) V o V fb f a(s) = V o V ε (s)
More informationECE 6412, Spring Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120
ECE 6412, Spring 2002 Final Exam Page 1 FINAL EXAMINATION NAME SCORE /120 Problem 1O 2O 3 4 5 6 7 8 Score INSTRUCTIONS: This exam is closed book with four sheets of notes permitted. The exam consists of
More informationClassification of Solids
Classification of Solids Classification by conductivity, which is related to the band structure: (Filled bands are shown dark; D(E) = Density of states) Class Electron Density Density of States D(E) Examples
More informationAuxiliaire d enseignement Nicolas Ayotte
2012-02-15 GEL 4203 / GEL 7041 OPTOÉLECTRONIQUE Auxiliaire d enseignement Nicolas Ayotte GEL 4203 / GEL 7041 Optoélectronique VI PN JUNCTION The density of charge sign Fixed charge density remaining 2
More informationDark Current Limiting Mechanisms in CMOS Image Sensors
Dark Current Limiting Mechanisms in CMOS Image Sensors Dan McGrath BAE Systems Information and Electronic Systems Integration Inc., Lexington, MA 02421, USA,
More informationENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)
ENGR89 Digital VLSI Design Fall 5 Lecture 4: CMOS Inverter (static view) [Adapted from Chapter 5 of Digital Integrated Circuits, 3, J. Rabaey et al.] [Also borrowed from Vijay Narayanan and Mary Jane Irwin]
More informationDESIGN MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT. Dr. Eman Azab Assistant Professor Office: C
MICROELECTRONICS ELCT 703 (W17) LECTURE 3: OP-AMP CMOS CIRCUIT DESIGN Dr. Eman Azab Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 TWO STAGE CMOS OP-AMP It consists of two stages: First
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter III CMOS Device, Inverter, Combinational circuit Logic and Layout Part 3 Combinational Logic Gates (textbook chapter 6) 9/18/2008 GMU, ECE 680 Physical VLSI Design
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationEE 505 Lecture 8. Clock Jitter Statistical Circuit Modeling
EE 505 Lecture 8 Clock Jitter Statistical Circuit Modeling Spectral Characterization of Data Converters Distortion Analysis Time Quantization Effects of DACs of ADCs Amplitude Quantization Effects of DACs
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationMOSFET and CMOS Gate. Copy Right by Wentai Liu
MOSFET and CMOS Gate CMOS Inverter DC Analysis - Voltage Transfer Curve (VTC) Find (1) (2) (3) (4) (5) (6) V OH min, V V OL min, V V IH min, V V IL min, V OHmax OLmax IHmax ILmax NM L = V ILmax V OL max
More informationSection 4. Nonlinear Circuits
Section 4 Nonlinear Circuits 1 ) Voltage Comparators V P < V N : V o = V ol V P > V N : V o = V oh One bit A/D converter, Practical gain : 10 3 10 6 V OH and V OL should be far apart enough Response Time:
More informationThe distribution of electron energy is given by the Fermi-Dirac distribution.
Notes: Semiconductors are materials with electrical resistivities that are in between conductors and insulators. Type Resistivity, Ohm m Resistance, Ohm (1mm length) Conductor 10-8 10-5 Semiconductor 10-2
More informationNTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate
NTE4501 Integrated Circuit CMOS, Dual 4 Input NAND Gate, 2 Input NOR/OR Gate, 8 Input AND/NAND Gate Description: The NTE4501 is a triple gate device in a 16 Lead DIP type package constructed with MOS P
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationEE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design
EE 435 Lecture 3 Spring 2016 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationLast Name _Di Tredici_ Given Name _Venere_ ID Number
Last Name _Di Tredici_ Given Name _Venere_ ID Number 0180713 Question n. 1 Discuss noise in MEMS accelerometers, indicating the different physical sources and which design parameters you can act on (with
More informationEE C245 ME C218 Introduction to MEMS Design Fall 2011
EE C245 ME C218 Introduction to MEMS Design Fall 2011 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture EE C245:
More informationIntegrated Circuit Design ELCT 701 (Winter 2017) Lecture 2: Resistive Load Inverter
1 Integrated Circuit Design ELCT 701 (Winter 017) Lecture : Resistive Load Inverter Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg Digital Inverters Introduction 3 Digital Inverter: Introduction
More informationVTS Process Photodiodes
VTS PROCESS LOW CAPACITANCE, LARGE AREA PHOTODIODE FEATURES Visible to IR spectral range Excellent QE - 400 to 1100 nm Guaranteed 400 nm response Response @ 940 nm, 0.60 A/W, typical Useable with visible
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN
ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN CMOS PROCESS CHARACTERIZATION VISHAL SAXENA VSAXENA@UIDAHO.EDU Vishal Saxena DESIGN PARAMETERS Analog circuit designers care about: Open-loop Gain: g m r o
More informationEE 505 Lecture 11. Statistical Circuit Modeling. R-string Example Offset Voltages
EE 505 Lecture 11 Statistical Circuit Modeling -string Example Offset oltages eview from previous lecture: Current Steering DAC Statistical Characterization Binary Weighted IL b= 1 1 IGk 1 1 I
More informationSystematic Design of Operational Amplifiers
Systematic Design of Operational Amplifiers Willy Sansen KULeuven, ESAT-MICAS Leuven, Belgium willy.sansen@esat.kuleuven.be Willy Sansen 10-05 061 Table of contents Design of Single-stage OTA Design of
More informationCONVERSION GAIN AND INTERPIXEL CAPACITANCE OF CMOS HYBRID FOCAL PLANE ARRAYS Nodal capacitance measurement by a capacitance comparison technique
CONVERSION GAIN AND INTERPIXEL CAPACITANCE OF CMOS HYBRID FOCAL PLANE ARRAYS Nodal capacitance measurement by a capacitance comparison technique G. Finger 1, J. Beletic 2, R. Dorn 1, M. Meyer 1, L. Mehrgan
More informationCOMBINATIONAL LOGIC. Combinational Logic
COMINTIONL LOGIC Overview Static CMOS Conventional Static CMOS Logic Ratioed Logic Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic Domino np-cmos Combinational vs. Sequential Logic In Logic
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically
More informationDevelopment of a Silicon PIN Diode X-Ray Detector
1 E-mail: jkabramov@gmail.com \ Chonghan Liu E-mail: kent@smu.edu Tiankuan Liu E-mail: liu@smu.edu Jingbo Ye E-mail: yejb@smu.edu Xiandong Zhao E-mail: xiandongz@smu.edu X-ray detectors currently on the
More informationLecture 4, Noise. Noise and distortion
Lecture 4, Noise Noise and distortion What did we do last time? Operational amplifiers Circuit-level aspects Simulation aspects Some terminology Some practical concerns Limited current Limited bandwidth
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More informationCMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)
CMPEN 411 VLSI Digital Circuits Lecture 04: CMOS Inverter (static view) Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 9 Propagation delay Power and delay Tradeoffs Follow board notes Propagation Delay Switching Time
More information3. Basic building blocks. Analog Design for CMOS VLSI Systems Franco Maloberti
Inverter with active load It is the simplest gain stage. The dc gain is given by the slope of the transfer characteristics. Small signal analysis C = C gs + C gs,ov C 2 = C gd + C gd,ov + C 3 = C db +
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Final EECS 240 Monday, May 19, 2008 SPRING 2008 You should write your results on the exam
More informationSystem on a Chip. Prof. Dr. Michael Kraft
System on a Chip Prof. Dr. Michael Kraft Lecture 3: Sample and Hold Circuits Switched Capacitor Circuits Circuits and Systems Sampling Signal Processing Sample and Hold Analogue Circuits Switched Capacitor
More informationNyquist-Rate A/D Converters
IsLab Analog Integrated ircuit Design AD-51 Nyquist-ate A/D onverters כ Kyungpook National University IsLab Analog Integrated ircuit Design AD-1 Nyquist-ate MOS A/D onverters Nyquist-rate : oversampling
More informationVLSI Design and Simulation
VLSI Design and Simulation CMOS Inverters Topics Inverter VTC Noise Margin Static Load Inverters CMOS Inverter First-Order DC Analysis R p V OL = 0 V OH = R n =0 = CMOS Inverter: Transient Response R p
More informationHIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
DESCRIPTION The / optocouplers consist of an AlGaAS LED, optically coupled to a very high speed integrated photo-detector logic gate with a strobable output. The devices are housed in a compact small-outline
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 12 The CMOS Inverter: static behavior guntzel@inf.ufsc.br
More informationIntegrated Circuit Operational Amplifiers
Analog Integrated Circuit Design A video course under the NPTEL Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India National Programme on Technology Enhanced
More information9/18/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI esign Chapter IV esigning Sequential Logic Circuits (Chapter 7) 1 Sequential Logic Inputs Current State COMBINATIONAL LOGIC Registers Outputs Next state 2 storage mechanisms positive
More informationEE 435. Lecture 23. Common Mode Feedback Data Converters
EE 435 Lecture 3 Common Mode Feedback Data Converters Review from last lecture Offset Voltage Distribution Pdf of zero-mean Gaussian distribution f(x) -kσ kσ x Percent between: ±σ 68.3% ±σ 95.5% ±3σ 99.73%
More informationEE 505. Lecture 11. Offset Voltages DAC Design
EE 505 Lecture 11 Offset Voltages DC Design Offset Voltages ll DCs have comparators and many DCs and DCs have operational amplifiers The offset voltages of both amplifiers and comparators are random variables
More informationEE 435. Lecture 3 Spring Design Space Exploration --with applications to single-stage amplifier design
EE 435 ecture 3 Spring 2019 Design Space Exploration --with applications to single-stage amplifier design 1 Review from last lecture: Single-ended Op Amp Inverting Amplifier V IN R 1 V 1 R 2 A V V OUT
More informationECE2262 Electric Circuits. Chapter 4: Operational Amplifier (OP-AMP) Circuits
ECE2262 Electric Circuits Chapter 4: Operational Amplifier (OP-AMP) Circuits 1 4.1 Operational Amplifiers 2 4. Voltages and currents in electrical circuits may represent signals and circuits can perform
More informationOPTI510R: Photonics. Khanh Kieu College of Optical Sciences, University of Arizona Meinel building R.626
OPTI510R: Photonics Khanh Kieu College of Optical Sciences, University of Arizona kkieu@optics.arizona.edu Meinel building R.626 Announcements Homework #6 is assigned, due May 1 st Final exam May 8, 10:30-12:30pm
More informationLecture 10, ATIK. Data converters 3
Lecture, ATIK Data converters 3 What did we do last time? A quick glance at sigma-delta modulators Understanding how the noise is shaped to higher frequencies DACs A case study of the current-steering
More informationMicroelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
More informationBlock Diagram. φclp 20
ILX3B -pixel CCD Linear Seor (B/W) Description The ILX3B is a reduction type CCD linear seor developped for DPPC, multifunction printers. This seor reads A4-size documents at a deity of 6 DPI at high speed
More informationSC70, 1.6V, Nanopower, Beyond-the-Rails Comparators With/Without Reference
19-1862; Rev 4; 1/7 SC7, 1.6V, Nanopower, Beyond-the-Rails General Description The nanopower comparators in space-saving SC7 packages feature Beyond-the- Rails inputs and are guaranteed to operate down
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationEECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-
EECS40 Spring 010 Lecture 1: Matching Elad Alon Dept. of EECS Offset V i+ V i- To achieve zero offset, comparator devices must be perfectly matched to each other How well-matched can the devices be made?
More informationNTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register
NTE4194B Integrated Circuit CMOS, 4Bit Bidirectional Universal Shift Register Description: The NTE4194B is a universal shift register in a 16Lead DIP type package featuring parallel inputs, parallel outputs
More informationV in (min) and V in (min) = (V OH -V OL ) dv out (0) dt = A p 1 V in = = 10 6 = 1V/µs
ECE 642, Spring 2003 - Final Exam Page FINAL EXAMINATION (ALLEN) - SOLUTION (Average Score = 9/20) Problem - (20 points - This problem is required) An open-loop comparator has a gain of 0 4, a dominant
More informationJan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. November Digital Integrated Circuits 2nd Sequential Circuits
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic esigning i Sequential Logic Circuits November 2002 Sequential Logic Inputs Current State COMBINATIONAL
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationBlock Diagram. Blue 3648 G R B 1
368 R 368 G 368 B 368 3pixel CCD Linear Seor (Color) ILX76K Description The ILX76K is a reduction type CCD linear seor developed for color image scanner, and has shutter function per each color. This seor
More informationSummary Last Lecture
EE247 Lecture 19 ADC Converters Sampling (continued) Sampling switch charge injection & clock feedthrough Complementary switch Use of dummy device Bottom-plate switching Track & hold T/H circuits T/H combined
More informationThe CMOS Inverter: A First Glance
The CMOS Inverter: A First Glance V DD V in V out C L CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power
More information