Block Diagram. φclp 20

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1 ILX3B -pixel CCD Linear Seor (B/W) Description The ILX3B is a reduction type CCD linear seor developped for DPPC, multifunction printers. This seor reads A4-size documents at a deity of 6 DPI at high speed of 6MHZ. 22 pin DIP (Plastic) Features Number of effective pixels: pixels Pixel size: 7µm 7µm (7µm pitch) Clamp circuit is on-chip Ultra high seitivity/ultra low lag Maximum data rate: 6MHz Single 2V power supply Input clock pulse: CMOS V drive Block Diagram 6 Package: 22 pin Plastic DIP (4mil) Absolute Maximum Ratings Supply voltage VDD V Operating temperature to +6 C Storage temperature 3 to +8 C Pin Configuration (Top View) D D64 S D63 S Read out gate Driver CCD register D4 D 8 VDD VDD Sony reserves the right to change products and specificatio without prior notice. This information does not convey any licee by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits. EY36

2 ILX3B Pin Description Pin No. Symbol Description VDD Signal out 2V power supply Clock pulse input Pin No. Symbol Description Clock pulse input Clock pulse input Clock pulse input Clock pulse input Clock pulse input Recommended Supply Voltage Item Min. VDD.4 Typ. 2. Max. 2.6 Unit V Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of, C, C 4 pf Input capacity of C pf Input capacity of C pf Input capacity of C pf Input capacity of C pf Clock Frequency Item Symbol Min. Typ. Max. Unit,,,, f, f, f, f, f 6 MHz Input Clock Pulse Voltage Condition Item Min. Typ. Max. Unit,,,,, pulse voltage High level Low level V V 2

3 ILX3B Electrooptical Characteristics (Note ) Item Symbol Seitivity R Seitivity nonuniformity PRNU Saturation output voltage VSAT Saturation exposure SER Dark voltage average VDRK Dark signal nonuniformity DSNU Image lag IL Supply current IVDD Total trafer efficiency TTE Output impedance ZO Offset level VOS Ta = 2 C, VDD = 2V, fφr = 2MHz, Input clock = Vp-p, Light source = 32K, IR cut filter CM-S (t =.mm) Min. Typ. Max. Unit Remarks V/(lx s) Note 2 4 % Note 3 2 V Note 4.4 lx s Note.3 2 mv.6 3 mv Note 6.2 % Note 7 3 ma % 23 Ω 6.2 V Note 8 Notes ) In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D4, D, to D62. 2) For the seitivity test light is applied with a uniform inteity of illumination. 3) PRNU is defined as indicated below. Ray incidence conditio are the same as for Note 2. = mv (Typ.) (VMAX VMIN)/2 PRNU = [%] The maximum output of pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. VAVE 4) Use below the minimum value of the saturation output voltage. ) Saturation exposure is defined as follows. SE = VSAT R 6) Optical signal accumulated time τ int stands at ms. 7) = mv (Typ.) 8) VOS is defined as indicated bellow. VOS 3

4 D D2 D3 D3 D4 D D6 D62 D63 S S2 S48 S49 S D64 D Clock Timing Chart 4 Optical black (49 pixles) Dummy signal (63 pixles) -line output period (22 pixles) Note) The trafer pulses (,, ) must have more than 22 cycles. ILX3B

5 ILX3B Clock Timing Chart 2 t4 t t2 t6 t7 t t3 Clock Timing Chart 3 t7 t6 t9 t t t8 t3 t4 t2 t t6 t7

6 ILX3B Clock Timing Chart 4 Cross point and V.V (Min.).V (Min.) V Cross point and V 2.V (Min.).V (Min.) V 6

7 ILX3B Clock Pulse Recommended Timing Item Symbol Min. Typ. Max. Unit, pulse timing t pulse high level period t2 3 µs, pulse timing t3 2 µs pulse rise time t4 pulse fall time t pulse rise time/ pulse fall time t6 2 6 pulse fall time/ pulse rise time t7 2 6 pulse high level period t8 () 2, pulse timing t9 () 2 pulse rise time t (3) pulse fall time t (3) pulse high level period t2 (2) 2, pulse timing t3 () pulse rise time t4 (3) pulse fall time t (3) Signal output delay time t6 t7 8 These timing is the recommended condition under f = MHz. 7

8 Application Circuit IC2 IC2 IC Ω Ω Ω Ω 2Ω VDD V Ω 2Ω 47µF/6V.µF Tr IC Data rate f = MHz.kΩ IC: 74AC4 IC2: 74HC4 Tr: 2SC278 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume respoibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ILX3B

9 ILX3B Example of Representative Characteristics (VDD = 2V, Ta = 2 C) Spectral seitivity characteristics (Standard characteristics) Relative seitivity Dark signal output temperature characteristics (Standard characteristics) Wavelength [nm] Integration time output voltage characteristics (Standard characteristics) Output voltage rate. Output voltage rate Ta Ambient temperature [ C] τ int integration time [ms] Offset level vs. VDD characteristics (Standard characteristics) Offset level vs. Temperature characteristics (Standard characteristics) VOS Offset level [V] Ta = 2 C VOS.6 VDD VOS Offset level [V] VOS Ta 2mV/ C VDD [V] Ta Ambient temperature [ C] 9

10 ILX3B Notes of Handling ) Static charge prevention CCD image seors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Itall a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image seor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Packages The following points should be observed when handling and italling packages. a) Remain within the following limits when applying static load to the package: () Compressive strength: 39N/surface (Do not apply load more than.7mm iide the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Teile strength: 29N/surface (4) Torsional strength:.9nm Cover glass Plastic portion 39N 29N 29N.9Nm Ceramic portion Adhesive () (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for itallation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the package to crack or dust to be generated. () Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer. () Applying the metal a crash or a rub agait the plastic portion. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. d) The notch of the plastic portion is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch or ceramic may overlap with the notch of the plastic portion.

11 ILX3B 3) Soldering a) Make sure the package temperature does not exceed 8 C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 3W soldering iron with a ground wire and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condeation, preheat or precool when moving to a room with great temperature differences. ) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditio. 6) CCD image seors are precise optical equipment that should not be subject to mechanical shocks.

12 ±. 4. ± ±.3.6. ±.3 to 9 Package Outline Unit: mm 22 pin DIP (4mil).7 ±.3.6 ± (7µm X pixels) 22 2 V H No. Pixel.2 3. ( 4. ) M. The height from the bottom to the seor surface is 2.38 ±.3mm. 2. The thickness of the cover glass is.7mm, and the refractive index is.. PACKAGE STRUCTURE PACKAGE MATERIAL Plastic, Ceramic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY Sony Corporation PACKAGE MASS DRAWING NUMBER.43g LS-B23-2(E) ILX3B