SN54F175, SN74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
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1 Contain Four Flip-Flops With Double-ail Outputs Buffered Clock and Direct Clear Inputs Applicatio Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Optio Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs description These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear () input. Information at the data (D) inputs meeting setup time requirements is traferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the traition time of the positive-going pulse. When the clock () input is at either the high or low level, the D-input signal has no effect at the output. The SNF is characterized for operation over the full military temperature range of C to C. The SNF is characterized for operation from 0 C to 0 C. SNF...J PACKAGE SNF...D O N PACKAGE (TOP VIEW) GND 8 SNF... FK PACKAGE (TOP VIEW) V CC Q GND 0 Q V CC Q Q D D Q Q No internal connection Q D D Q FUTION TABLE INPUTS OUTPUTS D Q Q L X X L H H H H L H L L H H L X Q0 Q0 PODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Itruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS
2 logic symbol C 0 D D Q Q Q Q This symbol is in accordance with ANSI/IEEE Std -8 and IEC Publication -. logic diagram (positive logic) C Two Identical Channels Not Shown D Q C Q Pin numbers shown are for the D, J, and N packages. POST OFFICE BOX 0 DALLAS, TEXAS
3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to V Input voltage range, V I (see Note ) V to V Input current range ma to ma Voltage range applied to any output in the high state V to V CC Current into any output in the low state ma Operating free-air temperature range: SNF C to C SNF C to 0 C Storage temperature range C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTE : The input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditio SNF SNF MIN NOM MAX MIN NOM MAX VCC Supply voltage.... V VIH High-level input voltage V VIL Low-level input voltage V IIK Input clamp current 8 8 ma IOH High-level output current ma IOL Low-level output current 0 0 ma TA Operating free-air temperature 0 0 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST CONDITIONS SNF SNF MIN TYP MAX MIN TYP MAX VIK VCC =. V, II = 8 ma.. V VOH VCC =. V, IOH = ma.... VCC =. V, IOH = ma. VOL VCC =. V, IOL = 0 ma V II VCC =. V, VI = V ma IIH VCC =. V, VI =. V 0 0 µa IIL VCC =. V, VI = 0. V ma IOS VCC =. V, VO = ma ICC VCC =. V, See Note.. ma All typical values are at VCC = V, TA = C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE : ICC is measured with outputs open with. V applied to all data inputs after a momentary ground followed by. V applied to. V POST OFFICE BOX 0 DALLAS, TEXAS
4 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = V, TA = C SNF SNF F MIN MAX MIN MAX MIN MAX fclock Clock frequency MHz high tw Pulse duration low tsu low Setup time, data before High or low Setup time, inactive state, data before high th Hold time, data after High or low Inactive-state setup time is also referred to as recovery time. switching characteristics (see Note ) PAAMETE FOM (INPUT) TO (OUTPUT) VCC = V, CL = 0 pf, L = 00 Ω, TA = C VCC =. V to. V, CL = 0 pf, L = 00 Ω, TA = MIN to MAX F SNF SNF MIN TYP MAX MIN MAX MIN MAX fmax MHz tplh tphl QorQ Q tplh Q tphl Q For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. NOTE : Load circuits and waveforms are shown in Section. POST OFFICE BOX 0 DALLAS, TEXAS
5 IMPOTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CETAIN APPLICATIONS USING SEMICONDUCTO PODUCTS MAY INVOLVE POTENTIAL ISKS OF DEATH, PESONAL INJUY, O SEVEE POPETY O ENVIONMENTAL DAMAGE ( CITICAL APPLICATIONS ). TI SEMICONDUCTO PODUCTS AE NOT DESIGNED, AUTHOIZED, O WAANTED TO BE SUITABLE FO USE IN LIFE-SUPPOT DEVICES O SYSTEMS O OTHE CITICAL APPLICATIONS. ILUSION OF TI PODUCTS IN SUCH APPLICATIONS IS UNDESTOOD TO BE FULLY AT THE CUSTOME S ISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 8, Texas Itruments Incorporated
SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs description These devices contain two independent J-K positive-edge-triggered flip-flops.
SN54HCT273, SN74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
Inputs Are TTL-Voltage ompatible ontain Eight D-Type Flip-Flops Direct lear Input Applicatio Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Optio Include Plastic Small-Outline
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ontain Eight Flip-Flops With Single-ail Outputs Direct lear Input Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Options
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Package Optio Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and eramic Flat (W) Packages, eramic hip arriers (FK), and Standard Plastic (N) and eramic (J)
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SNH, SNH 8-Line to -Line Multiplexers an Perform as: oolean Function enerators Parallel-to-Serial onverters Data Source Selectors Package Options Include Plastic Small-Outline (D) and eramic Flat () Packages,
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INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels
SN54/74LS147 SN54/74LS148 SN54/74LS LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54/ 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to eure that only the highest order
Time Constant. φ φ0.2 Bare copper wire
Figure 1.1. The physical photo of high temperature plastic tubing and sealed by epoxy, while the T70 is the non-sealed version. Comparing with conventional assemblies containing epoxy encapsulated thermistors,
INTEGRATED CIRCUITS. 74F521 8-bit identity comparator. Product specification May 15. IC15 Data Handbook
INTEGRATED CIRCUITS 1990 May IC Data Handbook FEATURES Compares two 8-bit words in 6.5ns typical Expandable to any word length DESCRIPTION The is an expandable 8-bit comparator. It compares two words of
INTEGRATED CIRCUITS. 74ALS138 1-of-8 decoder/demultiplexer. Product specification 1996 Jul 03 IC05 Data Handbook
INTEGRATED CIRCUITS 1996 Jul 03 IC05 Data Handbook FEATURES Demultiplexing capability Multiple input enable for easy expansion Ideal for memory chip select decoding DESCRIPTION The decoder accepts three
3.3 V 256 K 16 CMOS SRAM
August 2004 AS7C34098A 3.3 V 256 K 16 CMOS SRAM Features Pin compatible with AS7C34098 Industrial and commercial temperature Organization: 262,144 words 16 bits Center power and ground pins High speed
. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING) tpd = 11 ns (TYP.
M54HC137 M74HC137 3 TO 8 LINE DECODER/LATCH (INVERTING). HIGH SPEED tpd = 11 (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT DRIVE
Standard Products UT54ACS109/UT54ACTS109 Dual J-K Flip-Flops. Datasheet November 2010
Standard Products UT54ACS109/UT54ACTS109 Dual J-K Flip-Flops Datasheet November 2010 www.aeroflex.com/logic FEATURES 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available
74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:
Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM MAY 1999 FEATURES High-speed access time: 10, 12, 15, 20, 25 ns Low active power: 400 mw (typical) Low standby power 250 µw (typical) CMOS standby 55 mw (typical) TTL
54LS160A DM74LS160A 54LS162A DM74LS162A Synchronous Presettable BCD Decade Counters
54LS160A DM74LS160A 54LS162A DM74LS162A Synchronous Presettable BCD Decade Counters General Description The LS160 and LS162 are high speed synchronous decade counters operating in the BCD (8421) sequence
74LVC374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS
INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of February 1996 IC24 ata Handbook 1997 Mar 12 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance
74LV393 Dual 4-bit binary ripple counter
INTEGRATED CIRCUITS Supersedes data of 1997 Mar 04 IC24 Data Handbook 1997 Jun 10 FEATURES Optimized for Low Voltage applications: 1.0 to.6v Accepts TTL input levels between V CC = 2.7V and V CC =.6V Typical
INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels
F3 F F1 GND
4-BIT ARITHMETIC LOGIC UNIT The MC54/74F82 performs three arithmetic and three logic operatio on two 4-bit words, A and B. Two additional elect input codes force the Function outputs LOW or HIGH. An Overflow
DM74LS174/DM74LS175 Hex/Quad D Flip-Flops with Clear
DM74LS174/DM74LS175 Hex/Quad D Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input,
Standard Products UT54ACS74/UT54ACTS74 Dual D Flip-Flops with Clear & Preset. Datasheet November 2010
Standard Products UT54ACS74/UT54ACTS74 Dual D Flip-Flops with Clear & Preset Datasheet November 2010 www.aeroflex.com/logic FEATURES 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5
LOW POWER SCHOTTKY. GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648
The SN74LS247 is a BCD-to-Seven-Segment Decoder/Drivers. The LS247 composes the and with the tails. The LS247 has active-low outputs for direct drive of indicators. The LS247 features a lamp test input
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
with 30 Ω termination resistors; 3-state Rev. 03 17 January 2005 Product data sheet 1. General description 2. Features The is a high performance BiCMOS product designed for V CC operation at 3.3 V. The
74HC109-Q100; 74HCT109-Q100
Rev. 1 28 September 2016 Product data sheet 1. General description The is a dual positive edge triggered JK flip-flop featuring individual nj and nk inputs. It has clock (ncp) inputs, set (nsd) and reset
TC4511BP,TC4511BF TC4511BP/BF. TC4511B BCD-to-Seven Segment Latch/Decoder/Driver. Pin Assignment. Display
TC411BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC411BP,TC411BF TC411B BCD-to-Seven Segment Latch/Decoder/Driver TC411B is decoder which converts the input of BCD code into the 7
INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28
INTEGRATED CIRCUITS -to-8 line decoder/demultiplexer; inverting 998 Apr 8 FEATURES Wide supply voltage range of. to. V In accordance with JEDEC standard no. 8-A Inputs accept voltages up to. V CMOS lower
The 74HC21 provide the 4-input AND function.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
Analog Technologies. High Stability Miniature Thermistor ATH10K0.1%1R25
Figure 1.1. Physical Photo of the DESCRIPTIONS The series thermistor is consisted of three versions, as shown in Figure 1.1, T70 shown in Figure 1.2 and T70S. The has bear leads coated with copper, the