SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
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1 SNH, SN7H -IT PLLEL-OUT SEIL SHIFT EGISTES SCLS DECEME 92 EVISED MY 997 ND-Gated (Enable/ Disable) Serial Inputs Fully uffered Clock and Serial Inputs Direct Clear Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These -bit shift registers feature ND-gated serial inputs and an asynchronous clear (CL) input. The gated serial ( and ) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock () pulse. high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level transition of. The SNH is characterized for operation over the full military temperature range of C to 2 C. The SN7H is characterized for operation from 0 C to C. SNH...J O W PCKGE SN7H...D O N PCKGE (TOP VIEW) Q Q Q C Q D GND V CC Q H Q G Q F Q E CL SNH... FK PCKGE (TOP VIEW) Q Q Q C Q D GND CC H V Q CL No internal connection Q G Q F Q E FUTION TLE INPUTS OUTPUTS CL Q Q...QH L X X X L L L H L X X Q0 Q0 QH0 H H H H Qn QGn H L X L Qn QGn H X L L Qn QGn Q0, Q0, QH0 = the level of Q, Q, or QH, respectively, before the indicated steady-state input conditions were established Qn, QGn = the level of Q or QG before the most recent transition of : indicates a -bit shift Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PODUCTION DT information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 997, Texas Instruments Incorporated POST OFFICE OX 0 DLLS, TEXS 72
2 SNH, SN7H -IT PLLEL-OUT SEIL SHIFT EGISTES SCLS DECEME 92 EVISED MY 997 logic symbol SG 9 CL / & Q Q QC QD QE QF QG QH This symbol is in accordance with NSI/IEEE Std 9-9 and IEC Publication 7-2. Pin numbers shown are for the D, J, N, and W packages. logic diagram (positive logic) 2 CL Q Q QC QD QE QF QG QH Pin numbers shown are for the D, J, N, and W packages. 2 POST OFFICE OX 0 DLLS, TEXS 72
3 SNH, SN7H -IT PLLEL-OUT SEIL SHIFT EGISTES SCLS DECEME 92 EVISED MY 997 typical clear, shift, and clear sequence CL Serial Inputs Q Q QC Outputs QD QE QF QG QH Clear Clear absolute maximum ratings over operating free-air temperature range Supply voltage range, V CC V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note ) ±20 m Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note ) ±20 m Continuous output current, I O (V O = 0 to V CC ) ±2 m Continuous current through V CC or GND ±0 m Package thermal impedance, θ J (see Note 2): D package C/W N package C/W Storage temperature range, T stg C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a trace length of zero. POST OFFICE OX 0 DLLS, TEXS 72
4 SNH, SN7H -IT PLLEL-OUT SEIL SHIFT EGISTES SCLS DECEME 92 EVISED MY 997 recommended operating conditions SNH SN7H MIN NOM MX MIN NOM MX Supply voltage 2 2 V = 2 V.. VIH High-level input voltage =. V.. V = V.2.2 = 2 V VIL Low-level input voltage =. V V = V VI Input voltage 0 0 V VO Output voltage 0 0 V = 2 V tt Input transition (rise and fall) time =. V ns = V T Operating free-air temperature 2 0 C If this device is used in the threshold region (from VILmax = 0. V to VIHmin =. V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 000 ns and = 2 V does not damage the device; however, functionally, the inputs are not ensured while in the shift, count, or toggle operating modes. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PMETE TEST CONDITIONS T = 2 C SNH SN7H MIN TYP MX MIN MX MIN MX 2 V IOH = 20 µ. V VOH VI = VIH or VIL V V IOH = m. V IOH =.2 m V V IOL = 20 µ. V VOL VI = VIH or VIL V V IOL = m. V IOL =.2 m V II VI = or 0 V ±0. ±00 ±000 ±000 n ICC VI = or 0, IO = 0 V 0 0 µ Ci 2 V to V pf POST OFFICE OX 0 DLLS, TEXS 72
5 SNH, SN7H -IT PLLEL-OUT SEIL SHIFT EGISTES SCLS DECEME 92 EVISED MY 997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) T = 2 C SNH SN7H MIN MX MIN MX MIN MX 2 V fclock Clock frequency. V MHz tw tsu Pulse duration Setup time before V V CL low. V V V high or low. V 2 20 V 20 2 V Data. V V V CL inactive. V V V th Hold time, data after. V ns V ns ns switching characteristics over recommended operating free-air temperature range, C L = 0 pf (unless otherwise noted) (see Figure ) PMETE FOM (INPUT) TO (OUTPUT) T = 2 C SNH SN7H MIN TYP MX MIN MX MIN MX 2 V 0.2 fmax. V 2 2 MHz V V tphl CL ny Q. V 2 9 V 2 2 V tpd ny Q. V 2 V V tt. V 22 9 ns V 9 ns operating characteristics, T = 2 C PMETE TEST CONDITIONS TYP Cpd Power dissipation capacitance No load pf POST OFFICE OX 0 DLLS, TEXS 72
6 SNH, SN7H -IT PLLEL-OUT SEIL SHIFT EGISTES SCLS DECEME 92 EVISED MY 997 PMETE MESUEMENT INFOMTION From Output Under Test Test Point CL = 0 pf (see Note ) High-Level Pulse Low-Level Pulse tw LOD CICUIT VOLTGE WVEFOMS PULSE DUTIONS Input tplh tphl eference Input Data Input tsu th 90% 90% tr tf In-Phase Output Out-of-Phase Output tphl 90% 90% 90% tr tf tplh VOH VOL tf VOH 90% VOL tr VOLTGE WVEFOMS SETUP ND HOLD ND INPUT ISE ND FLL TIMES VOLTGE WVEFOMS POPGTION DELY ND OUTPUT TNSITION TIMES NOTES:. CL includes probe and test-fixture capacitance.. Phase relationships between waveforms were chosen arbitrarily. ll input pulses are supplied by generators having the following characteristics: P MHz, ZO = 0 Ω, tr = ns, tf = ns. C. For clock inputs, fmax is measured when the input duty cycle is. D. The outputs are measured one at a time with one input transition per measurement. E. tplh and tphl are the same as tpd. Figure. Load Circuit and Voltage Waveforms POST OFFICE OX 0 DLLS, TEXS 72
7 IMPOTNT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. ll products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CETIN PPLICTIONS USING SEMICONDUCTO PODUCTS MY INVOLVE POTENTIL ISKS OF DETH, PESONL INJUY, O SEVEE POPETY O ENVIONMENTL DMGE ( CITICL PPLICTIONS ). TI SEMICONDUCTO PODUCTS E NOT DESIGNED, UTHOIZED, O WNTED TO E SUITLE FO USE IN LIFE-SUPPOT DEVICES O SYSTEMS O OTHE CITICL PPLICTIONS. ILUSION OF TI PODUCTS IN SUCH PPLICTIONS IS UNDESTOOD TO E FULLY T THE CUSTOME S ISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 99, Texas Instruments Incorporated
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