TL7702B, TL7702BY, TL7705B, TL7705BY SUPPLY VOLTAGE SUPERVISORS

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1 Power-On Reset Generator Automatic Reset Generation After Voltage Drop Output Defined From V CC 1 V Precision Voltage Seor Temperature-Compeated Voltage Reference True and Complement Reset Outputs Externally Adjustable Pulse Duration description The TL02B and TL0B are monolithic integrated-circuit supply-voltage supervisors designed for use as reset conollers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for undervoltage conditio at the input. During power up, the output becomes active (low) when V CC attai a value approaching 1 V. As V CC approaches 3 V (assuming that is above V T+ ), the delay timer function activates a time delay, after which outputs and go inactive (high and low, respectively). When an undervoltage condition occurs during normal operation, outputs and go active. To eure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the input exceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor C T : t d C T, where C T is in farads (F) and t d is in seconds (s). TLxxBC...D OR P PACKAGE TLxxBM... JG PACKAGE (TOP VIEW) TLxxBM...FK PACKAGE (TOP VIEW) V CC An external capacitor (typically 0.1 µf) must be connected to to reduce the influence of fast aients in the supply voltage. The TL02BC and TL0BC are characterized for operation from 0 C to 0 C. The TL02BI and TL0BI are characterized for operation from 40 C to C. The TL02BQ and TL0BQ are characterized for operation from 40 C to 12 C. The TL02BM and TL0BM are characterized for operation from C to 12 C V CC TLxxBM...U PACKAGE (TOP VIEW) V CC No internal connection No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Iuments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Iuments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 199, Texas Iuments Incorporated On products compliant to MIL-PRF-33, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 303 DALLAS, TEXAS 2 1

2 TA 0 C to0 C 40 C to C 40 C to12 C C to12 C SMALL OUTLINE (D) CHIP CARRIER (FK) AVAILABLE OPTIONS PACKAGED DEVICES CERAMIC DIP (JG) PLASTIC DIP (P) CERAMIC FLATPACK (U) CHIP FORM (Y) TL02BCD TL02BCP TL0BCD TL0BCP TL02BID TL02BIP TL0BID TL0BIP TL02BY TL02BQD TL02BQP TL0BY TL0BQD TL0BQP TL02BMFK TL02BMJG TL02BMU TL0BMFK TL0BMJG TL0BMU TL02BY and TL0BY chip information These chips, when properly assembled, have characteristics similar to the TL02BC and the TL0BC. Thermal compression or ulasonic bonding can be used on the doped-aluminum bonding pads. The chips can be mounted with conductive epoxy or a gold-silicon preform. Bonding-Pad Assignments (1) () () 1 (2) (1) (2) (3) (4) TLxxBY () () () () VCC (3) (4) () () Chip Thickness: 1 Mils Typical Bonding Pads: 4 4 Mils Minimum TJ(max) = 10 C Tolerances Are ±10%. All Dimeio Are in Mils. 2 POST OFFICE BOX 303 DALLAS, TEXAS 2

3 functional block diagram The functional block diagram is shown for illusative purposes only; the actual circuit includes a imming network to adjust the reference voltage and see-comparator ip point. VCC 3 Reference Voltage 0 µa R1 (see Note A) R2 (see Note A) Pin numbers shown are for the D, JG, and P packages. NOTE A: TL02B: R1 = 0 Ω, R2 = open TL0B: R1 = 23 kω, R2 = 10 kω, nominal typical timing diagram VCC and VIT+ VIT VIT+ VIT Vres Vres 0 td td ÎÎÎÎ Output Undefined 0 Output ÎÎÎÎÎ Undefined POST OFFICE BOX 303 DALLAS, TEXAS 2 3

4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note 1) V Input voltage range, V I : V to 20 V V to 20 V High-level output current, I OH () ma Low-level output current, I OL () ma Continuous total power dissipation See Dissipation Rating Table Storage temperature range, T stg C to 10 C Case temperature for 0 seconds, T C : FK package C Lead temperature 1, mm (1/1 inch) from case for 0 seconds: JG or U packages C Lead temperature 1, mm (1/1 inch) from case for 10 seconds: D or P packages C Sesses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are sess ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the network ground terminal. PACKAGE TA 2 C POWER RATING DISSIPATION RATING TABLE DERATING FAOR ABOVE TA = 2 C TA = 0 C POWER RATING TA = C POWER RATING TA = 12 C POWER RATING D 2 mw. mw/ C 44 mw 3 mw 14 mw FK 13 mw 11.0 mw/ C 0 mw 1 mw 2 mw JG 100 mw.4 mw/ C 2 mw 4 mw 210 mw P 1000 mw.0 mw/ C 40 mw 20 mw 200 mw U 00 mw. mw/ C 43 mw 30 mw 10 mw recommended operating conditio MIN MAX UNIT Supply voltage, VCC 3. 1 V High-level input voltage, VIH 2 1 V Low-level input voltage, VIL 0 0. V Input voltage, VI 0 1 V High-level output current, IOH 1 ma Low-level output current, IOL 1 ma TL0xBC 0 0 Operating free-air temperature range, TA TL0xBI 40 TL0xBQ C TL0xBM 12 4 POST OFFICE BOX 303 DALLAS, TEXAS 2

5 elecical characteristics over recommended operating conditio (unless otherwise noted) TEST CONDITIONS TLxxBC TLxxBI TLxxBQ UNIT VOH High-level output voltage, IOH = 1 ma VCC 1. V VOL Low-level output voltage, IOL = 1 ma 0.4 V Vref Reference voltage Iref = 00 µa, TA = 2 C V VIT Vhys Negative-going input threshold voltage at input Hysteresis, (VIT+ VIT ) TL02B TL0B TL02B TL0B TL02B TL0B TA =2 C TA = full range VCC =3Vto1V 3. V, TA =2 C Vres Power-up reset voltage IOL at = 2 ma, TA = 2 C 1 V II Input current VI = 0.4 V to VCC 10 TL02B VI = Vref to 1 V IOH High-level output current, VO = 1 V, See Figure 1 0 µa IOL Low-level output current, VO = 0 V, See Figure 1 0 µa ICC Supply current V = 1 V, 2 V 1. 3 ma VCC = 1 V, TA = full range 3. ma All elecical characteristics are measured with 0.1-µF capacitors connected at,, and VCC to. Full range for the C-suffix device is 0 C to 0 C, full range for the I-suffix device is 40 C to C, and full range for the Q-suffix device is 40 C to 12 C. This is the lowest voltage at which becomes active. switching characteristics, V CC = V, open, T A = 2 C V mv µa FROM TO (INPUT) (OUTPUT) TEST CONDITIONS TLxxBC TLxxBI TLxxBQ UNIT tplh tphl low- to high-level output high- to low-level output See Figures 1, 2, and tw Effective pulse duration See Figure Rise time Fall time Rise time Fall time See Figures 1 and POST OFFICE BOX 303 DALLAS, TEXAS 2

6 elecical characteristics over recommended operating conditio (unless otherwise noted) TEST CONDITIONS TL02BM TL0BM UNIT VOH High-level output voltage, IOH = 1 ma VCC 1. V VOL Low-level output voltage, IOL = 1 ma 0.4 V Vref Reference voltage Iref = 00 µa, TA = 2 C V VIT Vhys Negative-going input threshold voltage at input Hysteresis, (VIT+ VIT ) TL02B TL0B TL02B TL0B TL02B TL0B TA =2 C TA = full range VCC =3Vto1V 3. V, TA =2 C Vres Power-up reset voltage IOL at = 2 ma, TA = 2 C 1 V II Input current VI = 0.4 V to VCC 10 TL02B VI = Vref to VCC 1. V IOH High-level output current, VO = 1 V 0 µa IOL Low-level output current, VO = 0 0 µa ICC Supply current V = 1 V, 2 V 1. 3 VCC = 1 V, TA = full range 4 All elecical characteristics are measured with 0.1-µF capacitors connected at,, and VCC to. Full range for the M-suffix device is C to 12 C. This is the lowest value at which becomes active. switching characteristics, V CC = V, open, T A = 2 C V mv µa ma tplh tphl tw low- to high-level output high- to low-level output Effective pulse duration FROM (INPUT) TO (OUTPUT) TEST CONDITIONS See Figures 1, 2, and 3 See Figure 2 Rise time Fall time See Figures 1 and 3 Rise time Fall time * On products compliant to MIL-PRF-33, these parameters are not production tested. TL02BM TL0BM UNIT 20 00* 20 00* * * 10* 0* POST OFFICE BOX 303 DALLAS, TEXAS 2

7 elecical characteristics over recommended operating conditio, T A = 2 C (unless otherwise noted) TEST CONDITIONS TL02BY TL0BY UNIT VOH High-level output voltage, IOH = 1 ma VCC 1. V VOL Low-level output voltage, IOL = 1 ma 0.4 V Vref Reference voltage Iref = 00 µa V VIT Negative-going g g input threshold voltage TL02BY at input TL0BY Vhys Hysteresis, (VIT+ VIT ) TL02BY TL0BY V CC =3Vto1V 3. V Vres Power-up reset voltage IOL at = 2 ma 1 V II Input current VI = 0.4 V to VCC 10 TL02BY VI = Vref to 1 V IOH High-level output current, VO = 1 V, See Figure 1 0 µa IOL Low-level output current, VO = 0 V, See Figure 1 0 µa ICC Supply current V = 1 V, 2 V 1. 3 ma All elecical characteristics are measured with 0.1-µF capacitors connected at,, and VCC to. This is the lowest voltage at which becomes active. switching characteristics, V CC = V, open, T A = 2 C V mv µa FROM (INPUT) TO (OUTPUT) TEST CONDITIONS TL02BY TL0BY UNIT tplh tphl low- to high-level output high- to low-level output See Figures 1, 2, and tw Effective pulse duration See Figure Rise time Fall time Rise time Fall time See Figures 1 and POST OFFICE BOX 303 DALLAS, TEXAS 2

8 MEASUREMENT INFORMATION V RL (see Note A) DUT V VCC DUT 1 pf (see Note B) RL (see Note A) 1 pf (see Note B) OUTPUT CONFIGURATION OUTPUT CONFIGURATION NOTES: A. For IOL and IOH, RL = 10 kω. For all switching characteristics, RL = 11 Ω. B. This figure includes jig and probe capacitance. Figure 1. and Output Configuratio tw V 2. V 0 V WAVEFORMS tw VT + 2 V VT VT 2 V Figure 2. Input Pulse Definition Voltage Fault VIT+ VIT VIT+ 0 V VIH Undefined 0. V 2 V VIL 90% 10% tplh 90% 90% V OH 0% td td Î t d 90% 0% 10% 10% 10% 10% VOL tphl Figure 3. Voltage Waveforms POST OFFICE BOX 303 DALLAS, TEXAS 2

9 TYPICAL CHARAERISTICS 20 1 VCC = V = 0.1 µf CL = 10 pf TA = 2 C ASSERTION TIME vs LOAD RESISTAE VCC = V = 0.1 µf CL = 10 pf TA = 2 C DEASSERTION TIME vs LOAD RESISTAE t Assertion Time t Deassertion Time RL Load Resistance kω Figure RL Load Resistance kω Figure 3 30 VCC = V = 0.1 µf RL = 4. kω TA = 2 C ASSERTION TIME vs LOAD CAPACITAE µ s VCC = V = 0.1 µf RL = 4. kω TA = 2 C DEASSERTION TIME vs LOAD CAPACITAE t Assertion Time t Deassertion Time and CL Load Capacitance pf Figure CL Load Capacitance pf Figure For proper operation, both and should be terminated with resistors of similar value. Failure to do so may cause unwanted plateauing in either output waveform during switching. POST OFFICE BOX 303 DALLAS, TEXAS 2 9

10 APPLICATION INFORMATION VS System Supply Reset Input (from system) 0.1 µf 2 1 RT 3 (see text) VCC 4 10 kω 10 kω To System To System Figure. System Reset Conoller With Undervoltage Seing When the TL0xB terminal is used to monitor V CC, a current-limiting resistor in series with C T is recommended. During normal operation, the timing capacitor is charged by the on-board current source to approximately V CC or an internal voltage clamp (.1-V zener), whichever is less. When the circuit is then subjected to an undervoltage condition during which V CC is rapidly slewed down, the voltage on exceeds that on V CC. This forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when V CC drops below V (), not when V falls below V T. Texas Iuments performs a 100% elecical screen to verify that the outputs do not switch with 1 ma forced into the terminal. Adding the external resistor, R T, prevents false iggering. Its value is calculated as follows: V () V T R T Where: V () = V CC or.1 V, whichever is less V T = 4. V (nom) R T = value of series resistor required For V CC = V: 4. 1mA R T Therefore, R T 40 Using a 20% tolerance resistor, R T should be greater than 0 Ω. Adding this series resistor changes the duration of the reset pulse by no more than 10%. R T extends the discharge of C T, but also skews the V () threshold. These effects tend to cancel one another. The precise percentage change can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration of the supply-voltage fault condition. Both outputs of the TL0xB should be terminated with similar value resistors, even when only one is being used. This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an undefined state or delay system reset. 10 POST OFFICE BOX 303 DALLAS, TEXAS 2

11 IMPORTANT NOTICE Texas Iuments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality conol techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUOR PRODUS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUOR PRODUS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. ILUSION OF TI PRODUS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 199, Texas Iuments Incorporated