TL601, TL604, TL607, TL610 P-MOS ANALOG SWITCHES

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1 TL0, TL0, TL0, TL0 P-MO NLOG WITCHE L0 D, JUNE 9 REVIED OCTOBER 9 witch ± 0-V nalog ignals TTL Logic Capability -to 0-V upply Ranges Low (00 Ω) On-tate Resistance High (0 Ω) Off-tate Resistance -Pin Functions description The TL0, TL0, TL0, and TL0 are a family of monolithic P-MO analog switches that provide fast switching speeds with high r off /r on ratio and no offset voltage. The p-channel enhancement-type MO switches accept analog signals up to ±0 V and are controlled by TTL-compatible logic inputs. The monolithic structure is made possible by BI-MO technology, which combines p-channel MO with standard bipolar transistors. These switches are particularly useful in military, industrial, and commercial applications such as data acquisition, multiplexers, /D and D/ converters, MODEM, sample-and-hold systems, signal multiplexing, integrators, programmable operational amplifiers, programmable voltage regulators, crosspoint switching networks, logic interface, and many other analog systems. The TL0 is an PDT switch with two logic control inputs. The TL0 is a dual complementary PT switch with a single control input. The TL0 is an PDT switch with one logic control input and one enable input. The TL0 is an PT switch with three logic control inputs. The TL0 features a higher r off /r on ratio than the other members of the family. The TL0C, TL0C, TL0C, and TL0C are characterized for operation from 0 C to 0 C, the TL0I, TL0I, TL0I, and TL0I are characterized for operation from C to C, and thetl0m, TL0M, TL0M, and TL0M are characterized for operation over the full military temperature range of C to C. B ENBLE B TYPICL OF LL INPUT JG OR P PCKGE (TOP VIEW) TL0 TL0 TL0 TL0 C schematics of inputs and outputs TYPICL OF LL WITCHE VCC VCC+ VCC PRODUCTION DT information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 9, Texas Instruments Incorporated POT OFFICE BOX 0 DLL, TEX

2 TL0, TL0, TL0, TL0 P-MO NLOG WITCHE D, JUNE 9 REVIED OCTOBER 9 logic symbols and switch diagrams B / & TL0 X X TL0 FUNCTION TBLE FUNCTION TBLE INPUT NLOG WITCHE INPUT NLOG WITCHE B L X Off (open) On (closed) H On (closed) Off (open) X L Off (open) On (closed) L Off (open) On (closed) H H On (closed) Off (open) ENBLE G X / TL0 B C & TL0 X FUNCTION TBLE FUNCTION TBLE INPUT NLOG WITCHE INPUT NLOG WITCHE ENBLE B C X L Off (open) Off (open) L X X Off (open) L H Off (open) On (closed) X L X Off (open) H H On (closed) Off (open) X X L Off (open) X H H On (closed) These symbols are in accordance with NI/IEEE td 9-9. TL0 logic diagram (positive logic) ENBLE POT OFFICE BOX 0 DLL, TEX

3 TL0, TL0, TL0, TL0 P-MO NLOG WITCHE D, JUNE 9 REVIED OCTOBER 9 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) upply voltage, V CC+ (see Note ) V upply voltage, V CC V V CC+ to V CC supply voltage differential V Control input voltage V CC+ witch off-state voltage V witch on-state current m Operating free-air temperature range: TL0C, TL0C, TL0C, TL0C C to 0 C TL0I, TL0I, TL0I, TL0I C to C TL0M, TL0M, TL0M, TL0M C to C torage temperature range C to 0 C Lead temperature (, mm) / inch from case for 0 seconds: JG package C Lead temperature (, mm) / inch from case for 0 seconds: P package C NOTE : ll voltage values are with respect to network ground terminal. recommended operating conditions TL0C, TL0C TL0C, TL0C TL0I, TL0I TL0I, TL0I TL0M, TL0M TL0M, TL0M UNIT MIN TYP MX MIN TYP MX MIN TYP MX upply voltage, VCC+ (see Figure ) V upply voltage, VCC (see Figure ) V VCC+ to VCC supply voltage differential (see Figure ) V High-level control input voltage, VIH... V Low-level control input voltage, VIL ll inputs Voltage at any analog switch () terminal VCC + VCC+ VCC + VCC+ VCC + VCC+ V witch on-state current m Operating free-air temperature, T 0 0 C POT OFFICE BOX 0 DLL, TEX

4 TL0, TL0, TL0, TL0 P-MO NLOG WITCHE D, JUNE 9 REVIED OCTOBER 9 electrical characteristics over recommended operating free-air temperature range, V CC+ = 0 V, V CC = 0 V, analog switch test current = m (unless otherwise noted) Ioff TL M TL C PRMETER TET CONDITION TL I MIN TYP MX MIN TYP MX IIH High-level input current VI =. V µ IIL Low-level input current VI = 0. V µ witch off-state current ICC upply current from VCC VI(sw) = 0 V, T = C p ee Note T = MX n VI(sw) = 0 V, IO(sw) = m Logic input(s) at. V, ll switch terminals open TL0 TL0 TL0 toff witch turn-off time RL = kω, CL = pf, ee Figure ns ton witch turn-on time 00 0 TL ron witch on-state resistance TL TL0 Ω VI(sw) = 0 V, TL IO(sw) = m TL0 TL roff witch off-state resistance 0 0 GΩ Con witch on-state input capacitance VI(sw) = 0 V, f = MHz pf Coff witch off-state input capacitance VI(sw) = 0 V, f = MHz pf Logic TL0 TL0 0 0 input(s) at ENBLE. V, 0 0 ICC+ upply current from VCC+ high ll switch TL0 ENBLE terminals low open m TL0 0 0 TL0 TL0.... ENBLE high ENBLE low MX is 0 C for C-suffix types, C for I-suffix types, and C for M-suffix types. ll typical values are at T= C except for loff at T= MX. NOTE : The other terminal of the switch under test is at VCC+ = 0 V. switching characteristics, V CC+ = 0 V, V CC = 0 V, T = C TL0.... PRMETER TET CONDITION MIN TYP MX UNIT UNIT m POT OFFICE BOX 0 DLL, TEX

5 TL0, TL0, TL0, TL0 P-MO NLOG WITCHE PRMETER MEUREMENT INFORMTION D, JUNE 9 REVIED OCTOBER 9 Figure shows power supply boundary conditions for proper operation of the TL0 eries. The range of operation for supply V CC+ from V to V is shown on the vertical axis. The range of V CC from V to V is shown on the horizontal axis. recommended 0-V maximum voltage differential from V CC+ to V CC governs the maximum V CC+ for a chosen V CC (or vice versa). minimum recommended difference of V from V CC+ to V CC and the boundaries shown in Figure allow the designer to select the proper combinations of the two supplies. The designer-selected V CC+ supply value for a chosen V CC supply value limits the maximum input voltage that can be applied to either switch terminal; that is, the input voltage should be between V CC + V and V CC+ to keep the on-state resistance within specified limits. 0 RECOMMENDED COMBINTION OF UPPLY VOLTGE upply Voltage V V CC+ 0 0 FE RE VCC upply Voltage V 0 Figure POT OFFICE BOX 0 DLL, TEX

6 TL0, TL0, TL0, TL0 P-MO NLOG WITCHE D, JUNE 9 REVIED OCTOBER 9 PRMETER MEUREMENT INFORMTION Pulse Generator (see Note ). V +0 V or 0 V TET CIRCUIT RL = kω Output CL = pf (see Note B) Input 0% Output NOTE:. The pulse generator has the following characteristics: Zo = 0 Ω, tr ns, tf ns, tw = 00 ns. B. CL includes probe and jig capacitance. Figure ton 90% toff 0% V O (0 V) k kr on VOLTGE WVEFORM V 0 V VO 0% TYPICL CHRCTERITIC 000 M-UFFIX DEVICE I-UFFIX DEVICE WITCH ON-TTE REITNCE vs WITCH NLOG VOLTGE 000 M-UFFIX DEVICE I-UFFIX DEVICE WITCH ON-TTE REITNCE vs FREE-IR TEMPERTURE r on witch On-tate Resistance Ω VCC+ = 0 V VCC = 0 V T = C IO(sw) = 0 m IO(sw) = m IO(sw) = 00 µ r on witch On-tate Resistance Ω VI(sw) = V VI(sw) = V VI(sw) = 0 V ÎÎÎÎÎ VI(sw) = V VI(sw) = 0 V VI(sw) = 0 V VCC+ = 0 V VCC = 0 V IO(sw) = m 0 0 VI(sw) witch nalog Voltage V T Free-ir Temperature C 00 Figure Figure POT OFFICE BOX 0 DLL, TEX

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