SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B DECEMBER 1982 REVISED MAY 1997

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1 ontain Eight Flip-Flops With Single-ail Outputs Direct lear Input Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Options Include Plastic Small-Outline (DW), Thin Shrink Small-Outline (PW), and eramic Flat (W) Packages, eramic hip arriers (FK), and Standard Plastic (N) and eramic (J) 00-mil DIPs SNH2, SNH2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLSB DEEMBE 92 EVISED MAY 99 SNH2...J O W PAKAGE SNH2...DW, N, O PW PAKAGE (TOP VIEW) L Q Q D GND V Q D D Q LK description These circuits are positive-edge-triggered D-type flip-flops with a direct clear (L) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (LK) pulse. lock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When LK is at either the high or low level, the D input has no effect at the output. The SNH2 is characterized for operation over the full military temperature range of to 2. The SNH2 is characterized for operation from 0 to. SNH2... FK PAKAGE (TOP VIEW) Q D Q L GND LK V Q D Q D FUNTION TABLE (each flip-flop) INPUTS OUTPUT L LK D Q L X X L H H H H L L H L X Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PODUTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 99, Texas Instruments Incorporated POST OFFIE BOX 0 DALLAS, TEXAS 2

2 SNH2, SNH2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLSB DEEMBE 92 EVISED MAY 99 logic symbol L LK D D D Q Q Q Q This symbol is in accordance with ANSI/IEEE Std 9-9 and IE Publication -2. logic diagram (positive logic) D D D LK L Q Q Q Q logic diagram, each flip-flop (positive logic) D Q LK(I) 2 POST OFFIE BOX 0 DALLAS, TEXAS 2

3 absolute maximum ratings over operating free-air temperature range SNH2, SNH2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLSB DEEMBE 92 EVISED MAY 99 Supply voltage range, V V to V Input clamp current, I IK (V I < 0 or V I > V ) (see Note ) ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note ) ±20 ma ontinuous output current, I O (V O = 0 to V ) ±2 ma ontinuous current through V or GND ±0 ma Package thermal impedance, θ JA (see Note 2): DW package /W N package /W PW package /W Storage temperature range, T stg to 0 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a trace length of zero. recommended operating conditions SNH2 SNH2 MIN NOM MAX MIN NOM MAX V Supply voltage 2 2 V V = 2 V.. VIH High-level input voltage V =. V.. V V = V.2.2 V = 2 V VIL Low-level input voltage V =. V V V = V VI Input voltage V VO Output voltage V V = 2 V ttt Input transition (rise and fall) time V =. V ns V = V TA Operating free-air temperature 2 0 POST OFFIE BOX 0 DALLAS, TEXAS 2

4 SNH2, SNH2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLSB DEEMBE 92 EVISED MAY 99 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST ONDITIONS V VOH VI I = VIH or VIL VOL VI I = VIH or VIL TA = 2 SNH2 SNH2 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 20 µa. V V V IOH = ma. V.9... IOH =.2 ma V V IOL = 20 µa. V V V IOL = ma. V IOL =.2 ma V II VI = V or 0 V ±0. ±00 ±000 ±000 na I VI = V or 0, IO = 0 V 0 0 µa i 2 V to V pf timing requirements over recommended operating free-air temperature range (unless otherwise noted) V TA = 2 SNH2 SNH2 MIN MAX MIN MAX MIN MAX 2 V fclock lock frequency. V MHz V tw tsu Pulse duration Setup time before LK 2 V L low. V 2 20 V 20 2 V LK high or low. V 2 20 V 20 2 V Data. V V V L inactive. V V V thh Hold time, data after LK. V ns V ns ns POST OFFIE BOX 0 DALLAS, TEXAS 2

5 SNH2, SNH2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLSB DEEMBE 92 EVISED MAY 99 switching characteristics over recommended operating free-air temperature range, L = 0 pf (unless otherwise noted) (see Figure ) PAAMETE FOM (INPUT) TO (OUTPUT) V TA = 2 SNH2 SNH2 MIN TYP MAX MIN MAX MIN MAX 2 V fmax. V MHz V V tphl L Any. V 2 0 ns V V tpd LK Any. V 2 0 ns V 2 2 V 0 9 ttt Any. V 22 9 ns V 9 operating characteristics, T A = 2 PAAMETE TEST ONDITIONS TYP pd Power dissipation capacitance per flip-flop No load pf POST OFFIE BOX 0 DALLAS, TEXAS 2

6 SNH2, SNH2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLSB DEEMBE 92 EVISED MAY 99 PAAMETE MEASUEMENT INFOMATION From Output Under Test Test Point L = 0 pf (see Note A) High-Level Pulse Low-Level Pulse tw V V LOAD IUIT VOLTAGE WAVEFOMS PULSE DUATIONS Input V tplh tphl eference Input Data Input 0% tsu th 90% 90% tr V V 0% tf In-Phase Output Out-of-Phase Output 0% tphl 90% 90% 90% tr 0% 0% tf tplh VOH 0% VOL tf VOH 90% VOL tr VOLTAGE WAVEFOMS SETUP AND HOLD AND INPUT ISE AND FALL TIMES VOLTAGE WAVEFOMS POPAGATION DELAY AND OUTPUT TANSITION TIMES NOTES: A. L includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: P MHz, ZO = 0 Ω, tr = ns, tf = ns.. For clock inputs, fmax is measured when the input duty cycle is. D. The outputs are measured one at a time with one input transition per measurement. E. tplh and tphl are the same as tpd. Figure. Load ircuit and Voltage Waveforms POST OFFIE BOX 0 DALLAS, TEXAS 2

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