SN54HCT273, SN74HCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
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1 Inputs Are TTL-Voltage ompatible ontain Eight D-Type Flip-Flops Direct lear Input Applicatio Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Optio Include Plastic Small-Outline (DW) and eramic Flat (W) Packages, eramic hip arriers (FK), and Standard Plastic (N) and eramic (J) 00-mil DIPs description SNHT2, SNHT2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLS0 NOVEMBE 9 EVISED MAY 99 SNHT2...J O W PAKAGE SNHT2...DW, N, O PW PAKAGE (TOP VIEW) L Q Q D D Q GND V Q D D Q Q D D Q LK These devices are positive-edge-triggered D-type flip-flops with a common enable input. The HT2 are similar to the HT, but feature a common clear enable (L) input itead of a latched clock. Information at the data (D) inputs meeting the setup time requirements is traferred to the Q outputs on the positive-going edge of the clock (LK) pulse. lock triggering occurs at a particular voltage level and is not directly related to the positive-going pulse. When LK is at either the high or low level, the D input has no effect at the output. The circuits are designed to prevent false clocking by traitio at L. The SNHT2 is characterized for operation over the full military temperature range of to 2. The SNHT2 is characterized for operation from 0 to. FUNTION TABLE (each flip-flop) INPUTS OUTPUT L LK D Q L X X L H H H H L L H L X Q0 SNHT2... FK PAKAGE (TOP VIEW) Q D D Q L Q GND LK V Q D Q D D Q Q D Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHEWISE NOTED this document contai PODUTION DATA information current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 99, Texas Itruments Incorporated POST OFFIE BOX 0 DALLAS, TEXAS 2
2 SNHT2, SNHT2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLS0 NOVEMBE 9 EVISED MAY 99 logic symbol L LK D D D D D D Q Q Q Q Q Q Q This symbol is in accordance with ANSI/IEEE Std 9-9 and IE Publication -2. logic diagram (positive logic) D D D D D D LK L Q Q Q Q Q Q Q logic diagram, each flip-flop (positive logic) D Q LK(I) 2 POST OFFIE BOX 0 DALLAS, TEXAS 2
3 absolute maximum ratings over operating free-air temperature range SNHT2, SNHT2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLS0 NOVEMBE 9 EVISED MAY 99 Supply voltage range, V V to V Input clamp current, I IK (V I < 0 or V I > V ) (see Note ) ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note ) ±20 ma ontinuous output current, I O (V O = 0 to V ) ±2 ma ontinuous current through V or GND ±0 ma Package thermal impedance, θ JA (see Note 2): DW package /W N package /W PW package /W Storage temperature range, T stg to 0 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a trace length of zero. recommended operating conditio SNHT2 SNHT2 MIN NOM MAX MIN NOM MAX V Supply voltage.... V VIH High-level input voltage V =. V to. V 2 2 V VIL Low-level input voltage V =. V to. V V VI Input voltage V VO Output voltage V tt Input traition (rise and fall) times TA Operating free-air temperature 2 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST ONDITIONS V VOH VOL VI =VIH or VIL VI =VIH or VIL TA = 2 SNHT2 SNHT2 MIN TYP MAX MIN MAX MIN MAX IOH = 20 µa. V IOH = ma. V IOL = 20 µa. V IOL = ma. V II VI = V or 0. V ±0. ±00 ±000 ±000 na I VI = V or 0, IO = 0. V 0 0 µa I One input at 0. V or 2. V, Other inputs at 0 or V. V ma. V i pf to. V This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than or V. V V PODUT PEVIEW information concer products in the formative or design phase of development. haracteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. POST OFFIE BOX 0 DALLAS, TEXAS 2
4 SNHT2, SNHT2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLS0 NOVEMBE 9 EVISED MAY 99 timing requirements over recommended operating free-air temperature range (unless otherwise noted) V TA = 2 SNHT2 SNHT2 MIN MAX MIN MAX MIN MAX fclock lock frequency. V V MHz tw Pulse duration LK high or low L low. V V V V 20 tsu Setup time before LK Data L inactive. V V 2 2. V V 2 2 th Hold time data after LK. V V switching characteristics over recommended operating free-air temperature range, V = V ± 0. V, L = 0 pf (unless otherwise noted) (see Figure ) PAAMETE FOM TO (INPUT) (OUTPUT) fmax tpd L Any tphl L Any tt Any SNHT2 V TA = 2 MIN TYP MAX MIN MAX. V 2. V 2 9. V 0. V V 0. V 2. V 22. V 9 2 MHz switching characteristics over recommended operating free-air temperature range, V = V ± 0. V, L = 0 pf (unless otherwise noted) (see Figure ) PAAMETE FOM TO (INPUT) (OUTPUT) fmax tpd L Any tphl L Any tt Any SNHT2 V TA = 2 MIN TYP MAX MIN MAX. V V 2 2. V 2. V V 2. V 29. V 9. V MHz PODUT PEVIEW information concer products in the formative or design phase of development. haracteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. POST OFFIE BOX 0 DALLAS, TEXAS 2
5 SNHT2, SNHT2 OTAL D-TYPE FLIP-FLOPS WITH LEA SLS0 NOVEMBE 9 EVISED MAY 99 operating characteristics, V = V, T A = 2 PAAMETE TEST ONDITIONS TYP pd Power dissipation capacitance No load 0 pf PAAMETE MEASUEMENT INFOMATION From Output Under Test LOAD IUIT Test Point L = 0 pf (see Note A) High-Level Pulse Low-Level Pulse tw Input VOLTAGE WAVEFOMS PULSE DUATIONS In-Phase Output Out-of- Phase Output tplh 0% tphl 90% 90% 90% tr tphl 0% 0% tf tplh VOH 0% VOL tf VOH 90% VOL tr eference Input Data Input 0. tsu th 2. V 2. V tr 0. tf VOLTAGE WAVEFOMS SETUP AND HOLD AND INPUT ISE AND FALL TIMES VOLTAGE WAVEFOMS POPAGATION DELAY AND OUTPUT ISE AND FALL TIMES NOTES: A. L includes probe and test-fixture capacitance. B. Phase relatiohips between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: P MHz, ZO = 0 Ω, tr =, tf =.. The outputs are measured one at a time with one input traition per measurement. D. E. For clock inputs, fmax is measured when the input duty cycle is 0%. tplh and tphl are the same as tpd. Figure. Load ircuit and Voltage Waveforms POST OFFIE BOX 0 DALLAS, TEXAS 2
6 IMPOTANT NOTIE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. ETAIN APPLIATIONS USING SEMIONDUTO PODUTS MAY INVOLVE POTENTIAL ISKS OF DEATH, PESONAL INJUY, O SEVEE POPETY O ENVIONMENTAL DAMAGE ( ITIAL APPLIATIONS ). TI SEMIONDUTO PODUTS AE NOT DESIGNED, AUTHOIZED, O WAANTED TO BE SUITABLE FO USE IN LIFE-SUPPOT DEVIES O SYSTEMS O OTHE ITIAL APPLIATIONS. INLUSION OF TI PODUTS IN SUH APPLIATIONS IS UNDESTOOD TO BE FULLY AT THE USTOME S ISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. opyright 99, Texas Itruments Incorporated
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