SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS094B DECEMBER 1982 REVISED MAY 1997

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1 Package Optio Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and eramic Flat (W) Packages, eramic hip arriers (FK), and Standard Plastic (N) and eramic (J) 00-mil DIPs description The H7 contain two independent D-type positive-edge-iggered flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements are aferred to the outputs on the positive-going edge of the clock (LK) pulse. lock iggering occurs at a voltage level and is not directly related to the rise time of LK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SNH7 is characterized for operation over the full military temperature range to 2. The SN7H7 is characterized for operation from 0 to. FUTION TABLE INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is utable; that is, it does not persist when PRE or LR retur to its inactive (high) level. SNH7...J OR W PAKAGE SN7H7... D, DB, N, OR PW PAKAGE (TOP VIEW) GND V SNH7... FK PAKAGE (TOP VIEW) GND V No internal connection 7 Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Iuments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Iuments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 997, Texas Iuments Incorporated POST OFFIE BOX 0 DALLAS, TEXAS 72

2 logic symbol S R 9 This symbol is in accordance with ANSI/IEEE Std 9-9 and IE Publication 7-2. Pin numbers shown are for the D, DB, J, N, PW, and W packages. logic diagram (positive logic) PRE LK Q D LR Q absolute maximum ratings over operating free-air temperature range Supply voltage range, V V to 7 V clamp current, I IK (V I < 0 or V I > V ) (see Note ) ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note ) ±20 ma ontinuous output current, I O (V O = 0 to V ) ±2 ma ontinuous current through V or GND ±0 ma Package thermal impedance, θ JA (see Note 2): D package /W DB package /W N package /W PW package /W Storage temperature range, T stg to 0 Sesses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are sess ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD, except for through-hole packages, which use a ace length of zero. 2 POST OFFIE BOX 0 DALLAS, TEXAS 72

3 recommended operating conditio SNH7 SN7H7 MIN NOM MAX MIN NOM MAX V Supply voltage 2 2 V V = 2 V.. VIH High-level input voltage V =. V.. V V = V.2.2 V = 2 V VIL Low-level input voltage V =. V V V = V VI voltage V VO Output voltage V V = 2 V ttt aition (rise and fall) time V =. V V = V TA Operating free-air temperature 2 0 elecical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V VI I = VIH or VIL VI I = VIH or VIL TA = 2 SNH7 SN7H7 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 20 µa. V V V IOH = ma. V IOH =.2 ma V V IOL = 20 µa. V V V IOL = ma. V IOL =.2 ma V II VI = V or 0 V ±0. ±00 ±000 ±000 na I VI = V or 0, IO = 0 V 0 0 µa i 2 V to V pf POST OFFIE BOX 0 DALLAS, TEXAS 72

4 timing requirements over recommended operating free-air temperature range (unless otherwise noted) V TA = 2 SNH7 SN7H7 MIN MAX MIN MAX MIN MAX 2 V fclock lock frequency. V MHz V tw tsu Pulse duration Setup time before LK 2 V PRE or LR low. V V V LK high or low. V 2 20 V V Data. V V V PRE or LR inactive. V V 7 2 V thh Hold time, data after LK. V V switching characteristics over recommended operating free-air temperature range, L = 0 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) V TA = 2 SNH7 SN7H7 MIN TYP MAX MIN MAX MIN MAX 2 V 0.2 fmax. V MHz V tpd 2 V PRE or LR Q or Q. V 20 9 V V LK Q or Q. V 20 0 V V ttt Q or Q. V 22 9 V 9 operating characteristics, T A = 2 PARAMETER TEST ONDITIONS TYP pd Power dissipation capacitance per flip-flop No load pf POST OFFIE BOX 0 DALLAS, TEXAS 72

5 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point LOAD IRUIT L = 0 pf (see Note A) High-Level Pulse Low-Level Pulse 0% tw 0% 0% 0% V V TAGE WAVEFORMS PULSE DURATIONS Reference tsu 0% th V 0% tplh 0% tphl V Data 0% 0% 90% 90% V 0% 0% TAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES In-Phase Output Out-of-Phase Output 0% 0% tphl 90% 90% 90% 0% 0% 0% 0% tplh 0% 0% 90% TAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. L includes probe and test-fixture capacitance. B. Phase relatiohips between waveforms were chosen arbiarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 0 Ω, =, =.. For clock inputs, fmax is measured when the input duty cycle is 0%. D. The outputs are measured one at a time with one input aition per measurement. E. tplh and tphl are the same as tpd. Figure. Load ircuit and Voltage Waveforms POST OFFIE BOX 0 DALLAS, TEXAS 72

SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B DECEMBER 1982 REVISED MAY 1997

SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B DECEMBER 1982 REVISED MAY 1997 ontain Eight Flip-Flops With Single-ail Outputs Direct lear Input Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage egisters Shift egisters Pattern Generators Package Options