AVAILABLE OPTIONS PACKAGED DEVICES CHIP CARRIER (FK) CERAMIC DIP (JG) TL7702ACD TL7715ACD TL7702ACP TL7715ACP TL7702ACY TL7715ACY

Transcription

1 Power-On Reset Generator Automatic Reset Generation After Voltage Drop Wide Supply Voltage Range Precision Voltage Sensor Temperature-Compensated Voltage Reference True and Complement Reset Outputs Externally Adjustable Pulse Duration description The TLxxA family of monolithic integrated circuit supply voltage supervisors are specifically designed for use as reset controllers in microcomputer and microprocessor systems. The supply voltage supervisor monitors the supply for undervoltage conditions at the input. During power up, the output becomes active (low) when V CC attains a value approaching. V. At this point (assuming that is above V IT+ ), the delay timer function activates a time delay after which outputs and TL0A, TL0A, TL09A, TLA, TLA RESIN D, JG, OR P PACKAGE (TOP VIEW) REF RESIN go inactive (high and low respectively). When an undervoltage condition occurs during normal operation, outputs and go active. To ensure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the input exceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor C T : t d =. x 0 x C T, where C T is in farads (F) and t d is in seconds (s). During power down (assuming that is below V IT ), the outputs remain active until the V CC falls below a maximum of V. After this, the outputs are undefined. An external capacitor (typically 0.µF for the TLxxAC and TLxxAI and typically 0.0 µf for the TLxxAM) must be connected to REF to reduce the influence of fast transients in the supply voltage. The TLxxAC series are characterized for operation from 0 C to 0 C. The TLxxAI series are characterized for operation from 0 C to C. The TL0AM and TL0AM are characterized for operation over the full military range of C to C. FK PACKAGE (TOP VIEW) REF V CC No internal connection V CC TA 0 C to 0 C 0 C to C C to C SMALL OUTLINE (D) AVAILABLE OPTIONS PACKAGED DEVICES CHIP CARRIER (FK) CERAMIC DIP (JG) PLASTIC DIP (P) CHIP FORM (Y) TL0ACD TLACD TL0ACP TLACP TL0ACY TLACY TL0AID TLAID TL0AMFK TL0AMFK TL0AMJG TL0AMJG TL0AIP TLAIP PRODUION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Instruments Incorporated On products compliant to MIL-STD-, Class B, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 0 DALLAS, TEXAS

2 TLxxAY chip information This chip, when properly assembled, displays characteristics similar to the TLxxAC. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS () () () () REF RESIN () () () () TLxxAY () () () () () () () () CHIP THICKNESS: MILS TYPICAL BONDING PADS: MILS MINIMUM TJmax = 0 C TOLERAES ARE ±0% ALL DIMENSIONS ARE IN MILS POST OFFICE BOX 0 DALLAS, TEXAS

3 functional block diagram The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming network to adjust the reference voltage and sense comparator trip point. Reference Voltage 00 µa R (see Note A) R (see Note A) RESIN NOTES: A. TL0A: R = 0 Ω, R = open TL0A: R =. kω, R = 0 kω TL09A: R = 9. kω, R = 0 kω TLA: R =. kω, R = 0 kω TLA: R =. kω, R = 0 kω B. Terminal numbers shown are for the D, JG, or P package. C. Resistor values shown are nominal. timing diagram and REF Threshold Voltage. V V ÎÎ t d td Output Undefined Output Undefined POST OFFICE BOX 0 DALLAS, TEXAS

4 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, V CC (see Note ) V Input voltage range, V I, RESIN V to 0 V Input voltage range, V I, : TL0A (see Note ) V to V TL0A V to 0 V TL09A V to 0 V TLA, TLA V to 0 V High-level output current, I OH, ma Low-level output current, I OL, ma Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, T A : TLxxAC C to 0 C TLxxAl C to C TL0AM, TL0AM C to C Storage temperature range, T stg C to 0 C Case temperature for 0 seconds, T C : FK package C Lead temperature, mm (/ inch) from case for 0 seconds: D or P package C Lead temperature, mm (/ inch) from case for 0 seconds: JG package C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltage values are with respect to the network ground terminal. PACKAGE TA C POWER RATING DISSIPATION RATING TABLE DERATING FAOR ABOVE TA = C TA = 0 C POWER RATING TA = C POWER RATING TA = C POWER RATING D mw. mw/ C mw mw mw FK mw.0 mw/ C 0 mw mw mw JG 00 mw. mw/ C mw mw 0 mw P 000 mw.0 mw/ C 0 mw 0 mw 00 mw recommended operating conditions TLxxAC, TLxxAI TLxxAM MIN MAX MIN MAX Supply voltage,.. 0 V High-level input voltage at RESIN, VIH V Low-level input voltage at RESIN, VIL V TL0A 0 See Note 0 See Note TL0A Input voltage,, VI TL09A 0 V TLA 0 0 TLA 0 0 High-level output current,, IOH ma Low-level output current,, IOL ma Timing capacitor, 0 0 µf TLxxAC 0 0 Operating free-air temperature range, TA TLxxAI 0 C TL0AM, TL0AM NOTE : For proper operation of the TL0A, the voltage applied to the terminal should not exceed V or V, whichever is less. POST OFFICE BOX 0 DALLAS, TEXAS

5 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TLxxAC, TLxxAI MIN TYP MAX VOH High-level output voltage, IOH = ma. V VOL Low-level output voltage, IOL = ma 0. V Vref Reference voltage TA = C... V VIT Negative-going i input threshold h voltage, TL0A... TL0A... TL09A TA = C... V TLA TLA... TL0A 0 TL0A Vhysy Hysteresis, (VIT + VIT ) TL09A TA = C 0 mv TLA II Input current, RESIN TLA VI =. V to 0 VI = 0. V 00 II Input current, TL0A Vref < VI <. V 0. µa IOH High-level output current, VO = V 0 µa IOL Low-level output current, VO = 0 0 µa ICC Supply current All inputs and outputs open. ma All electrical characteristics are measured with 0.-µF capacitors connected at REF,, and to. switching characteristics over recommended operating conditions (unless otherwise noted) tw(s) PARAMETER TEST CONDITIONS TLxxAC, TLxxAI MIN TYP MAX Output pulse duration = 0. µf 0... µs Input pulse duration at RESIN 0. µs Pulse duration at input to switch outputs VIH = VIT + 00 mv, VIL = VIT 00 mv µa µs tpd Propagation delay time from RESIN to = V µs 0. tr. = V, See Note. tf 0. All switching characteristics are measured with 0.-µF capacitors connected at REF and to. NOTE : The rise and fall times are measured with a.-kω load resistor at and. µs µs POST OFFICE BOX 0 DALLAS, TEXAS

6 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TL0AM, TL0AM MIN TYP MAX VOH High-level output voltage, IOH = ma. V VOL Low-level output voltage, IOL = ma 0. V Vref Reference voltage... V VIT Negative-going g g input threshold voltage, TL0AM =Vto0V TL0AM V CC. V Vhys Hysteresis (VIT + VIT ) II Input current, RESIN TL0AM TL0AM V CC =Vto0V. V VI =. V to 0 VI = 0. V 00 II Input current, TL0AM Vref < VI <. V 0. µa IOH High-level output current, VO = 0 V 0 µa IOL Low-level output current, VO = 0 0 µa ICC Supply current All inputs and outputs open. ma All electrical characteristics are measured with 0.0-µF capacitors connected at REF,, and to. switching characteristics over recommended operating conditions (unless otherwise noted) tw(s) PARAMETER TEST CONDITIONS Pulse duration at input to switch outputs VIH = VIT + 00 mv, VIL = VIT 00 mv 0 TL0AM, TL0AM MIN TYP MAX V mv µa * µs tpd Propagation delay time, RESIN to = V. µs tr tf 0.* = V, See Note 0.* * On products compliant to MIL-STD-, Class B, this parameter is not production tested. All switching characteristics are measured with 0.0-µF capacitors connected at REF and to. NOTE : The rise and fall times are measured with a.-kω load resistor at and..*.* µs µs POST OFFICE BOX 0 DALLAS, TEXAS

7 electrical characteristics over recommended operating conditions, T A = C (unless otherwise noted) PARAMETER TEST CONDITIONS TLxxAY MIN TYP MAX Vref Reference voltage. V VIT Negative-going i input threshold h voltage, TL0A. TL0A. TL09A. V TLA 0. TLA. TL0A 0 TL0A Vhys Hysteresis, (VIT + VIT ) TL09A 0 mv TLA TLA II Input current, TL0A Vref < VI <. V 0. µa ICC Supply current All inputs and outputs open. ma All electrical characteristics are measured with 0.-µF capacitors connected at REF,, and to. switching characteristics over recommended operating conditions, T A = C (unless otherwise noted) PARAMETER TEST CONDITIONS TLxxAY MIN TYP MAX Output pulse duration = 0. µf. µs All switching characteristics are measured with 0.-µF capacitors connected at REF and to. POST OFFICE BOX 0 DALLAS, TEXAS 9

8 PARAMETER MEASUREMENT INFORMATION Voltage Drop tw(s) VIT+ VIT VIT+ 0 V VIH RESIN Undefined tf 90% 0% tr 90% 0. V tpd 0% V 90% ÎÎ t d VIL VOH () td tf td 90% 0% 0% 0% 0% 0% VOL() tr Figure. Voltage Waveforms 0 POST OFFICE BOX 0 DALLAS, TEXAS

9 TYPICAL CHARAERISTICS ASSERTION TIME vs LOAD RESISTAE DEASSERTION TIME vs LOAD RESISTAE t Assertion Time ns 0 tr = V = 0. µf CL = 0 pf TA = C µ s t Deassertion Time tf = V = 0. µf CL = 0 pf TA = C tf tr 0 0 RL Load Resistance kω RL Load Resistance kω Figure Figure ASSERTION TIME vs LOAD CAPACITAE DEASSERTION TIME vs LOAD CAPACITAE. t Assertion Time ns 0 = V = 0. µf RL =. kω TA = C tr t Deassertion Time µ s.... = V = 0. µf RL =. kω TA = C tf tr tf CL Load Capacitance pf CL Load Capacitance pf Figure Figure For proper operation both and should be terminated with resistors of similar value. Failure to do so may cause unwanted plateauing in either output waveform during switching. POST OFFICE BOX 0 DALLAS, TEXAS

10 APPLICATION INFORMATION V V RESIN TLA REF 0. µf 0 kω 0 kω kω RESIN TL0A REF 0. µf 0 kω System Reset 0 kω RESIN TLA REF 0 kω (F) = td(s). x 0 0. µf V Figure. Multiple Power Supply System Reset Generation V RESIN TL0A REF 0 kω 0 kω 0. µf TMS000 VSS (F) = td(s). x 0 Figure. Reset Controller for TMS000 System Terminal numbers shown are for the D, JG, and P packages. POST OFFICE BOX 0 DALLAS, TEXAS

11 APPLICATION INFORMATION V Input µa0 INPUT OUTPUT COMMON CI CO TL0A REF 0. µf. kω G. kω S D kω Q N99 System Figure. Eliminating Undefined States Using a P-Channel JFET 0 kω 0 Ω Input TLxxA RESIN. kω Q N0 System REF 0 kω kω 0. µf Figure 9. Eliminating Undefined States Using a pnp Transistor Terminal numbers shown are for the D, JG, and P packages. POST OFFICE BOX 0 DALLAS, TEXAS

12 POST OFFICE BOX 0 DALLAS, TEXAS

13 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical Applications ). TI SEMICONDUOR PRODUS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 99, Texas Instruments Incorporated