# Integrated Circuit Design ELCT 701 (Winter 2017) Lecture 2: Resistive Load Inverter

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1 1 Integrated Circuit Design ELCT 701 (Winter 017) Lecture : Resistive Load Inverter Assistant Professor Office: C

2 Digital Inverters Introduction

3 3 Digital Inverter: Introduction A Fundamental logic gate that performs invert Boolean operation Single input logic gate Logic 1 and 0 are represented by node voltages referring to ground potential According to Positive logic convention : Logic 1 is V DD (Highest Supply Voltage) and logic 0 is gnd (0V)

4 4 Digital Inverter: Introduction The relation between the output and input voltages of the inverter is given by: DC Voltage Transfer Characteristics VTC Ideal Inverter VTC Input Voltage [V] Input Logic Output Logic Output Voltage [V] 0 V in < V th 0 1 V DD V th <V in V DD V th = V DD Note: V th is the inverter threshold Voltage

5 5 Digital Inverter: Introduction Actual inverter VTC deviates from the Ideal characteristics No abrupt change between logic 1 and 0 How can we evaluate the performance of the inverter? There are five parameters that defines the inverter s VTC Parameter V OH V OL V IL V IH V th Definition Maximum output Voltage when the output level is logic 1 Maximum output Voltage when the output level is logic 0 Maximum input Voltage that can be considered as logic 0 Minimum input Voltage that can be considered as logic 1 The inverter threshold voltage

6 6 Digital Inverter: Introduction How to calculate the VTC parameters: V OH : by putting the minimum allowed voltage in the circuit as the input voltage to the inverter and calculating the output voltage V OL : by putting the input voltage of the inverter as V OH and calculating the output voltage V IL & V IH is the smallest and largest Input voltages that satisfies respectively the following equation: dv out dv in = 1 V th : is the intersection between VTC & the equation: V out =V in

7 7 Digital Inverter: Introduction Notes: Any input voltage between lowest Supply and V IL is considered logic input 0 Any input voltage between V IH and highest supply is considered logic input 1 Any output voltage between the lowest supply in the circuit and V OL is considered logic output 0 Any output voltage between V OH and the highest supply in the circuit is considered logic output 1 The logic levels aren t represented by a quantized voltage values but rather by a range

8 8 Digital Inverter: Introduction Notes (Cont.): The ability of the inverter to interpret logic 0 and 1 over a wide range is a plus (Close to ideal inverter VTC) The circuit functionality is not affected significantly by noise signals (high robustness) A transition region is defined between V IL and V IH, the input signal logic is undefined (V IL <V in <V IH ) Noise Margin defines the tolerance of the circuit How much the circuit is immune to noise signals? NM H = V OH V IH NM L = V IL V OL

9 9 Digital Inverter: Introduction Notes (Cont.): The shaded area indicates the valid voltage levels of the input and output voltages that won t affect the circuit functionality V IL and V IH is at the points where the slope is -1, why?? V out = f(v in ) In case of noise added to the input: Applying Taylor Series: If the derivative term is more than -1 the output due to the noise will be more than the original signal! V out = f(v in + V noise ) V out = f V in + dv out dv in V noise + higher order negligible terms

10 10 Resistive Load Inverter Circuit Structure and DC Analysis

11 11 Resistive Load Inverter: introduction Generalized Circuit Structure: Enhancement NMOS transistor is the inverter driver Transistor A two-terminal load is used to connect the driver transistor to the voltage supply C out represents the loading effect of the next gates connected at the output node (neglected in Static VTC analysis) Driver NMOS Bulk (Substrate) is connected to its Source (V SB =0,Constant V T ) V in = V GS I L = I D V out = V DS

12 1 Linear Resistance-Load Inverter Enhancement NMOS transistor is the inverter driver Transistor A Resistive load is used to connect the driver transistor to the voltage supply Note: the driver transistor s threshold voltage is given by: V T = V To + γ F + V SB F At Zero substrate bias, the transistor s threshold voltage is constant V SB = 0 V T = V To Where: V To is the Zero substrate bias threshold voltage, ᵞ is the substrate-bias coefficient and ᶲ F is the substrate Fermi Potential V in = V GS I R = I D V out = V DS

13 13 Linear Resistance-Load Inverter Driver Enhancement NMOS transistor modes of operation Input Voltage Range NMOS mode Drain Current V Cut-OFF in < V To I D = 0 V To V in V out + V To V in V out + V To Saturation Linear I D = K n V GS V To I D = K n V GS V To V DS V DS V in = V GS V out = V DS I R = I D

14 14 Linear Resistance-Load Inverter 1. Calculation of V OH : Assuming that V in Cutoff is low, M is in V in = V GS < V To I D = I R = 0 V out = V DD I R R L = V OH V OH = V DD

15 15 Linear Resistance-Load Inverter. Calculation of V OL : Assuming that V in =V OH, M is in Linear mode and V out is low V in = V OH = V DD V out = V OL V in = V DD > V To V in > V out + V To I D = K n V DD V To V OL V OL = I R = V DD V OL R L V OL V DD V To + 1 V K n R OL + = 0 L K n R L A quadratic equation with two solutions, However 0 < V OL < V DD V OL = V DD V To + 1 V K n R DD V To + 1 L K n R L V DD K n R L

16 16 Linear Resistance-Load Inverter 3. Calculation of V IL : Assuming that V in >V OL, M is in Saturation mode and V out is high V in > V To V in < V out + V To I D = I R = K n V in V To = V DD V out R L Calculate the derivative of the current w.r.t. V in K n V in V To = 1 dv out R L dv in To get V IL we will Substitute with: V in = V IL dv out dv in = 1 V IL = V To + 1 K n R L

17 17 Linear Resistance-Load Inverter 4. Calculation of V IH : Assuming that V in <V OH, M is in Linear mode and V out is low ( < V OL ) V in > V To V in > V out + V To I D = I R = K n V in V To V out V out = V DD V out R L Calculate the derivative of the current w.r.t. V in K n V in V To dv out dv in + V out V out dv out dv in To get V IH we will Substitute with: V in = V IH dv out dv in = 1 = 1 R L dv out dv in V IH = V To 1 K n R L + V out

18 18 Linear Resistance-Load Inverter 4. Calculation of V IH : (Cont.) To get V IH we have to find V out at V IH using the drain current equation K n V IH V To V out V out = V DD V out R L K n 1 K n R L + V out V out V out = V DD V out R L V DD V out = 3 K n R L Then V IH is given by: V IH = V To 1 K n R L + V out V IH = V To 1 K n R L V DD K n R L

19 19 Linear Resistance-Load Inverter 5. Calculation of V th : Assume that V in =V out V GS = V DS Thus M is in Saturation I D = I R = K n V in V To = V DD V out R L K n V th V To = V DD V th R L Derive V th Assignment

20 0 Linear Resistance-Load Inverter Summary: V OH = V DD V OL = V DD V To + 1 V K n R DD V To + 1 L K n R L V DD K n R L V IH = V To 1 K n R L + 8 V DD 3 K n R L V IL = V To + 1 K n R L Note that the term K n R L affects the VTC of the inverter significantly The designer use the aspect ratio W/L and the load value to determine the VTC

21 1 Linear Resistance-Load Inverter Power Dissipation: Static power dissipation is given by the current drawn from the supply during steady state P DC = V DD I DC Assuming that the output voltage level is 50% of the time logic 0 and the other 50% logic 1 P DC,avg. = V DD I = 0 + I = 1 For the resistive load inverter I in = 0 is 0A, thus the avg. power is given by: P DC,avg. = V DD V DD V OL R L

22 Linear Resistance-Load Inverter Notes on Power Dissipation: Increasing R L improves the VTC and the power consumption (lower power) However increasing R L means larger area which is a major drawback for IC design We can maintain the same K n R L product by increasing W/L, however still a few kω load will consume large area.

23 3 NMOS-Load Inverters Circuit Structure and Static Characteristics

24 4 Enhancement NMOS Load Type 1: Inverter Enhancement NMOS transistor is the inverter driver Transistor Enhancement NMOS transistor is the inverter load Driver Bulk (Substrate) is connected to its Source (V SB =0,Constant V T ) For Self-biased load V GD,load =0, the load is always in saturation It suffers from low V OH V OH = V DD V T,load

25 5 Enhancement NMOS Load Type : Inverter Enhancement NMOS transistor is the inverter driver Transistor Enhancement NMOS transistor is the inverter load Driver Bulk (Substrate) is connected to its Source (V SB =0,Constant V T ) The gate of the load is connected to another supply V G,load =V GG, the load is always in linear We have two supply lines V OH = V DD

26 6 Depletion NMOS Load Inverter General Circuit Structure: Enhancement NMOS transistor is the inverter driver Transistor depletion NMOS transistor is the inverter load Driver NMOS Bulk (Substrate) is connected to its Source (V SB,driver =0,Constant V To,driver ) Depl. NMOS Bulk (Substrate) is not connected to its Source (V T,load is not constant) The load V GS,load =0, the load is always ON (negative V T )

27 7 Depletion NMOS Load Inverter NMOS transistors modes of operation for Depl. Load inverter Input Voltage Range Driver NMOS mode Depletion NMOS mode V in = V OL V in = V IL Cut-OFF Saturation Linear Linear V in = V IH V in = V OH Linear Linear Saturation Saturation V in = V th Saturation Saturation V in = V GS,driver V out = V DS,driver I D,load = I D,driver

28 8 Depletion NMOS Load Inverter 1. Calculation of V OH : Assuming that V in is low, driver is in Cutoff and load is in linear mode V in = V GS,driver < V To,driver I D,driver = I D,load = 0 V GS,load = 0 V DS,load = V DD V OH I D,load = K n,load V T,load V DD V OH V DD V OH ) = 0 V DD V OH = 0 V OH = V DD

30 30 Depletion NMOS Load Inverter. Calculation of V OL : (Cont.) Note: V T,load is not constant, it is a function in V SB,load =V OL V OL = V DD V To,driver K n,load V DD V To,driver V K T,load n,driver V T,load V OL = V To,load + γ F + V OL F Thus to get V OL, we must solve the two equations together

31 31 Depletion NMOS Load Inverter 3. Calculation of V IL : Assuming that V in >V OL, driver is in Saturation mode and load is in linear V out is high V in = V GS,driver > V To,driver V in < V out + V To,driver V GS,load = 0 > V DD V out + V T,load K n,driver V in V To,driver = K n,load V T,load V DD V out V DD V out Calculate the derivative of the current w.r.t. V in K n,driver V in V To,driver = K n,load V T,load dv out dv in + V DD V out dv T,load dv in V DD V out dv out dv in To get V IL we will Substitute with: V in = V IL dv out dv in = 1 Negligible term

32 3 Depletion NMOS Load Inverter 3. Calculation of V IL : (Cont.) To get V IL we will Substitute with: K n,driver V in V To,driver = K n,load V T,load dv out dv in + V DD V out dv T,load dv in V DD V out dv out dv in K n,driver V IL V To,driver = K n,load V T,load V DD V out Negligible term V IL = V To,driver + K n,load K n,driver V T,load + V out V DD We have to get V V in =V IL to solve the equation The threshold voltage of the load is also variable

33 33 Depletion NMOS Load Inverter 4. Calculation of V IH : Assuming that V in <V OH, driver is in Linear mode and load is in sat. (V out is low ( < V OL )) K n,driver V in V To,driver V out V out = K n,load V T,load Calculate the derivative of the current w.r.t. V in K n,driver V in V To,driver dv out dv in + V out V out dv out dv in = K n,load V T,load dv T,load dv out dv out dv in To get V IH we will Substitute with: V in = V IH dv out dv in = 1 V IH = V To,driver + K n,load dv T,load V K T,load + V n,driver dv out out

34 34 Depletion NMOS Load Inverter 4. Calculation of V IH : (Cont.) We have to calculate V V IH to get the exact expression of V IH V IH = V To,driver + K n,load dv T,load V K T,load + V n,driver dv out out K n,driver V IH V To,driver V out V out = K n,load V T,load

35 35 Depletion NMOS Load Inverter 5. Calculation of V th : Assume that V in =V out V GS,driver = V DS,driver = V th Thus driver and load are in Saturation K n,driver V in V To = K n,load V T,load Derive V th (Homework)

36 36 Depletion NMOS Load Inverter Note that: K R the ratio between the load to the driver aspect ration affects the VTC of the inverter significantly K R = K n,load K n,driver

37 37 Depletion NMOS Load Inverter Power Dissipation: Assuming that the output voltage level is 50% of the time logic 0 and the other 50% logic 1 P DC,avg. = V DD I = 0 + I = 1 For the depl. load inverter I in = 1 is calculated while the load is in saturation P DC,avg. = V DD K n,load V T,load

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