Analog and Telecommunication Electronics

Transcription

1 Politecnico di Torino Electronic Eng. Master Degree Analog and Telecommunication Electronics D2 - DAC taxonomy and errors» Static and dynamic parameters» DAC taxonomy» DAC circuits» Error sources AY /04/ ATLCE - D DDC 2016 DDC 1

2 Lesson D2: D/A converters Parameters of D/A converters Linear: gain and offset error Integral and differential nonlinearity Dynamic parameters DAC structures Uniform and weighted architectures Circuit examples, V/I reciprocity Bipolar and multiplying circuits Error sources References: Elettronica per Telecom.: 4.2 Convertitori digitale/analogico Design with Op Amp : 12.2,.3 D/A Conv Tech., Multip. DAC 16/04/ ATLCE - D DDC 2016 DDC 2

3 DAC transfer function Input variable (D) is discrete The A(D) plot is a sequence of dots With constant Ad the dots are aligned S A Ad 0 D LSB M 16/04/ ATLCE - D DDC 2016 DDC 3

4 Conversion characteristic M = 2 N if high N many dots: the dot sequence becomes a continuous line steps have constant x and x straigth line A S 0 D 0 M 16/04/ ATLCE - D DDC 2016 DDC 4

5 Errors in D/A converters Two types of errors in a real system: Static errors Constant input Steady state behavior Appear in the A(D) diagram Dynamic errors Variable input signal Transient behavior Appear in A(t) 16/04/ ATLCE - D DDC 2016 DDC 5

6 Static errors: two step analysis The actual transfer function is not a straight line Which parameters define how good is a DAC? Two-step analysis: Plot the best approximating straight line Compare actual ideal transfer functions in two steps 1: Linear approximation ideal transfer function Linear errors: offset and gain 2: Actual transfer function linear approximation Nonlinearity errors 16/04/ ATLCE - D DDC 2016 DDC 6

7 Ideal and actual D/A characteristic S A ideal 0 0 actual M D 16/04/ ATLCE - D DDC 2016 DDC 7

8 Approximation with straight line S A Best approximating straight line 0 0 actual M D 16/04/ ATLCE - D DDC 2016 DDC 8

9 Ideal vs best linear approximation S A ideal Best approximating straight line 0 0 M D 16/04/ ATLCE - D DDC 2016 DDC 9

10 Linear errors: offset and gain The approximation straight line does go across (0,0) and (M,S). The difference is described by: Offset o : Intercept of approximating line with A axis Can be compensated adding a constant Gain error g : Difference among real and actual slope Can be compensated by gain correction This analysis methodology applies for any (nominally) linear transfer function 16/04/ ATLCE - D DDC 2016 DDC 10

11 Offset error Ideal transfer function D = 0 A = 0 Actual transfer function Not through 0,0 A On the approximating straight line D = 0 A = Voff Offset error: o = Voff Voff D 16/04/ ATLCE - D DDC 2016 DDC 11

12 Gain error Ideal transfer function A = K D Actual transfer function Different slope For the approximating straight line A = K D K = K + K Gain error: g = K/K A g D 16/04/ ATLCE - D DDC 2016 DDC 12

13 Integral nonlinearity S A maximum deviation of actual fdt from best straight line: integral nonlinearity error Nonlinearity band inl Best approximating straight line 0 Actual transfer function D 0 M 16/04/ ATLCE - D DDC 2016 DDC 13

14 Differential nonlinearity A Actual transfer function A D A D 0 D 0 Best linear approximation 1 LSB 16/04/ ATLCE - D DDC 2016 DDC 14

15 Differential nonlinearity error Ideal transfer function: dots spaced A D (A axis) 1 LSB (D axis) Actual transfer function: dots spaced A D A D The difference A D -A D = dnl is the differential nonlinearity If dnl > 1 LSB, (slope inversion) Non-monotonicity error 16/04/ ATLCE - D DDC 2016 DDC 15

16 Non-monotonicity error A S A D A D 0 0 slope inversion M D 16/04/ ATLCE - D DDC 2016 DDC 16

17 Test D2-1: Diff. vs. integral nonlin. Draw the conversion characteristic for a 3-bit DAC with: ε dnl = + 1/4 LSB from 000 to 011 (MSB = 0) ε dnl = - 1/4 LSB from 100 to 111 (MSB = 1) Draw the conversion characteristic for a 3-bit DAC with: ε dnl = + 1/4 LSB when LSB = 0 ε dnl = - 1/4 LSB when LSB = 1 Compare the two cases evaluate integral nonlinearity error ε inl evaluate differential nonlinearity error ε dnl evaluate offset and gain errors 16/04/ ATLCE - D DDC 2016 DDC 17

18 Integral and differential nonlinearity Integral nonlinearity INL Unique figure: deviation of transfer function from a straight line Differential nonlinearity DNL Difference A D -A D between ideal (A D ) and actual (A D ) amplitude of each stair step Specific to each step (but has a max!) ε INL = ( DNL ) = ( DNL ) ε DNL = δ( INL )/δd Fixed polarity ε DNL high ε INL Alternate polarity ε DNL low ε INL 16/04/ ATLCE - D DDC 2016 DDC 18

19 Overall view S A ideal non-linearity band Best approximating straigth line 0 0 actual M D 16/04/ ATLCE - D DDC 2016 DDC 19

20 Settling time The D/A output takes a settling time Ts to reach the new value (within a ± ½ LSB error) Limited by slew rate II order response 16/04/ ATLCE - D DDC 2016 DDC 20

21 Glitch In a transient the output can go to a widely wrong value (typically 0V or full-scale S). The spike is called GLITCH 16/04/ ATLCE - D DDC 2016 DDC 21

22 Where do glitches come from? Glitches are caused by differences in switching delays of various bits. These delays cause faulty transient states (e.g and 0000 when moving from 0111 to 1000). These states drive the output - for a very short time towards 0V or full scale S. Glitches occur in transitions like x0111 x1000 change is 1 LSB, temporary state during the transient can be x0000 or x /04/ ATLCE - D DDC 2016 DDC 22

23 DAC error summary Static error parameters Linear errors: gain: G offset: O Nonlinearity errors: Integral NL: inl differential NL: dnl Dynamic parameters Settling time: t S Glitches Measured as % of full scale S Absolute value (mv, µv) Fraction of LSB (1/2 LSB, ¼ LSB, ) 16/04/ ATLCE - D DDC 2016 DDC 23

24 Lesson D2: D/A converters Parameters of D/A converters Classification of errors in D/A converters linear: gain and offset Integral and differential nonlinearity Dynamic parameters DAC structures Uniform and weighted architectures Circuit examples Bipolar and multiplying circuits 16/04/ ATLCE - D DDC 2016 DDC 24

25 D/A conversion basic circuits Sum of elementary quantities (V or I) controlled by D REFERENCE ELEMENTARY QUANTITIES DIGITAL INPUT (D) ANALOG OUTPUT (A) Uniform elementary quantities (1, 1, 1, ) Weighted elementary quantities (1, 2, 4, ) 16/04/ ATLCE - D DDC 2016 DDC 25

26 Uniform quantities Sum of elementary units with the same weight (1) The number of units is controlled by the digital value. Output = D * LSB Example: 13 D = This is called uniform elements conversion 16/04/ ATLCE - D DDC 2016 DDC 26

27 Weighted quantities Sum of elementary units with the weights corresponding to power of 2 (1, 2, 4, 8, ) Each unit is controlled by the corresponding bit value (1/0 ) Output = 2 i * Di Example: 13 D = 1101 B Weight Value D = 8*1 + 4*1 + 2*0 + 1*1 This is called weighted elements conversion 16/04/ ATLCE - D DDC 2016 DDC 27

28 Uniform currents D/A converter Ie Io The output current Io is the sum of a variable number of identical elementary currents controlled by D: N bits M = 2N identical branches V R R(D) I O 16/04/ ATLCE - D DDC 2016 DDC 28

29 Uniform voltages D/A converters The output is a voltage Vo obtained summing elementary voltage drops on the resistor chain. Since all resistors have the same value, all voltage drops are the same. V O The tap is selected by the digital value D. This structure is a potentiometric DAC V R V O 16/04/ ATLCE - D DDC 2016 DDC 29

30 Weighted elements converters Weighted elements (usually currents) Obtained from a reference (usually a voltage Vr) through a weight network, Added or blocked towards the adder by a bank of switches controlled by bits Ci of the digital input data D Vr DIGITAL INPUT (D) WEIGHT NETWORK N-1 1 C 0 2 C 1 4 C 2 2 N-1 C N-1 ANALOG OUTPUT (A) 16/04/ ATLCE - D DDC 2016 DDC 30

31 Weighted currents D/A converters R 2R 4R 2 N-1 R Io Ii The output current Io is the sum of a variable number of weighted elementary currents Ii (weight ratio 2), directly controlled by D N bits N = weighted branches V R R(D) I O 16/04/ ATLCE - D DDC 2016 DDC 31

32 Weighted resistor D/A converter Same circuit, with switches steering currents towards nodes at the same potential (GND/Io) Current switches High dynamic range for resistors (2 N-1 ) Constant load on Vr 16/04/ ATLCE - D DDC 2016 DDC 32

33 Voltage and current switches Linear passive networks: reciprocity If input and output are exchanged, same I(V) relation I 1 = D(V 1 ) I 2 = D(V 2 ) 16/04/ ATLCE - D DDC 2016 DDC 33

34 Weighted elements - voltage switches Same network, exchange of Vr and Iu Switches operate between nodes at different potential (Vr, GND) Voltage switches again, high dynamic range for resistors (2 N-1 ) 16/04/ ATLCE - D DDC 2016 DDC 34

35 Voltage/current switch comparison Current switches (both nodes 0 V) Voltage switches (nodes at Vr / 0V) 16/04/ ATLCE - D DDC 2016 DDC 35

36 Ladder network - 1 Splitting a current in two equal parts V R 2I 2R I I R R I I = V R /2R 16/04/ ATLCE - D DDC 2016 DDC 36

37 Ladder network - 2 Repeat the splitting 2I I R I/2 R V R 2R 2R R I I/2 I/2 I = V R /2R 16/04/ ATLCE - D DDC 2016 DDC 37

38 Ladder network - 3 Continue splitting (4 currents) 2I I R I/2 R I/4 R I/8 R V R 2R 2R 2R 2R I I/2 I/4 I/8 R I 0 I 1 I 2 I 3 I = V R /2R I i = I/2 i 16/04/ ATLCE - D DDC 2016 DDC 38

39 Benefits of ladder networks The ladder network is fully modular Any number of bits Uses only R and 2R resistors Same technology, same behavior (temp, aging, ) Precise current ratio D/A converter with ladder network: branch currents can be sent to ground/output summing node with current switches V-output with Norton/Thevenin conversion Reciprocal network with V-switches feasible 16/04/ ATLCE - D DDC 2016 DDC 39

40 Ladder network with I-out and I-SW 2I I R R R R V R 2R 2R 2R 2R I I/2 I/4 I/8 R MSB 0 1 I O I-Switches steer the current between equipotential nodes 16/04/ ATLCE - D DDC 2016 DDC 40

41 Ladder network with I-out and V-SW I R R R R I OUT 2R 2R 2R 2R I I/2 I/4 I/8 R MSB 0 1 V R V-Switch connect a node to V R /0 Voltage output 16/04/ ATLCE - D DDC 2016 DDC 41

42 Ladder network - conversion example 2I I R R R R V R 2R 2R 2R 2R I I/2 I/4 I/8 R MSB I TOT = I/2 + I/8 I TOT 16/04/ ATLCE - D DDC 2016 DDC 42

43 Current and voltage outputs Constant equivalent output resistance The Thevenin and Norton equivalent generators have the same relation with digital input D Io = K D Vo = K R D A circuit with current output (Icc) and constant Ru can be turned into a voltage-output circuit. 16/04/ ATLCE - D DDC 2016 DDC 43

44 Ladder network with voltage output I R R R R V OUT 2R 2R 2R 2R I I/2 I/4 I/8 R MSB Switches operate between GND and V R V R 16/04/ ATLCE - D DDC 2016 DDC 44

45 Capacitive weight networks Use as weighted element charge instead of current The weight network uses capacitors instead of resistors Precision depends on capacitance ratio Better suited for MOS technology Reduced power consumption 16/04/ ATLCE - D DDC 2016 DDC 45

46 Error sources Linear errors gain, offset Gainerror» Changes in Vr» Systematic error in the weight network Offset error» Leakage current of switches» Offset of Op Amp These errors do not depend on the value D A unique correction value works for all dynamic range Can be corrected in the digital domain 16/04/ ATLCE - D DDC 2016 DDC 46

47 Branch errors Equivalent resistance of switches (Ron) Modifies the total branch resistance Same effects as weight resistor error (tolerance) Modifies the branch current If R/R constant gain error Leakage current of switches (Ioff) Some output current even for D = 0 If constant: offset error Depends on temperature 16/04/ ATLCE - D DDC 2016 DDC 47

48 Errors in weighted D/A networks Each branch contributes to output when corresponding bit is 1 MSB contributes over S/2, MSB-1 over S k/4,... Branches have different weight MSB weight is 1/2, MSB-1 weight is 1/4,. Out_error = branch_error x branch_weight the same % error in different branches causes different errors at the output higher effects on MSBs MSBs branches must be more precise Critical parameter differential nonlinearity. 16/04/ ATLCE - D DDC 2016 DDC 48

49 Errors in weighted D/A - example Error on MSB branch actual contribution higher than ideal raised upper half of characteristic branch error 10%: output error 5% Error on MSB - 1 branch actual contribution lower than ideal lowered odd quarters (1, 3) of characteristic branch error 10%: output error 2.5% Error on MSB - 2 branch branch error 10%: output error 1.25%... 16/04/ ATLCE - D DDC 2016 DDC 49

50 Errors in weight network: MSB, MSB-1 S A S A S/2 nla S/2 nla 0 D 0 D nla nla Slope inversion error on MSB (+) error on MSB 1 (-) 16/04/ ATLCE - D DDC 2016 DDC 50

51 Errors in uniform D/A networks Out_error = branch_error x branch_weight each branch has the same weight (1 LSB) the same % error in any branch causes the same output error intrinsically monotonic output» sum of elements with the same sign All branches can have the same precision Errors of all branches sum at the output Critical parameter: integral nonlinearity 16/04/ ATLCE - D DDC 2016 DDC 51

52 Uniform elements D/A: example Potentiometric converter with systematic error in the resistor chain + R in the upper half, - R in the lower half high integral nonlinearity S S/2 0 A D The voltage divider is unbalanced; the mid node is at a voltage lower than S/2. Intermediate nodes have proportional errors /04/ ATLCE - D DDC 2016 DDC 52

53 Problem D2-a: DAC errors Weighted R Error R +/-10% (alternated) in all branches Error R +10% in all branches Plot Vo(D) 16/04/ ATLCE - D DDC 2016 DDC 53

54 Error summary Gain error Changes of reference voltage Vr Systematic errors in the weight network Offset error Op Amp offsets Leakage current of switches Nonlinear errors Random errors in the weight network (N LD ) Systematic error in the uniform network (N LI ) 16/04/ ATLCE - D DDC 2016 DDC 54

55 Mixed D/A converters Weighted networks simple (Order N) need high precision on MSBs branches Uniform networks complex (Order 2 N ) intrinsically monotone Mixed structures: use uniform branches for MSBs use weighted branches for LSBs benefits of both structures: simple, no need for high precision Split weighted uniform decoding Keep benefits of uniform networks, with reduced complexity 16/04/ ATLCE - D DDC 2016 DDC 55

56 Example of mixed D/A converter 2 MSBs: linear DAC 3 resistors + 3 SW 4 LSBs: weighted DAC Weighted R or ladder network 16R Uniform elements (2 MSBs) Weighted elements (4 LSBs) 16/04/ ATLCE - D DDC 2016 DDC 56

57 Example: mixed DAC 5linear + 5coded 16/04/ ATLCE - D DDC 2016 DDC 57

58 Example of split DAC 20 μa x 2 4 = 320 μa 16R 10 μa 10 μa x 2 1 = 20 μa 16/04/ ATLCE - D DDC 2016 DDC 58

59 Indirect D/A converters Use an intermediate quantity (e.g. time) From numeric value D to a time T 1 (pulse width) Signal average (after LPF) is proportional to D Direct conversion of digital signals 16/04/ ATLCE - D DDC 2016 DDC 59

60 Bipolar D/A converters - 1 Sign inversion of output voltage V O Unipolar DAC sign A -1 Possible jump in (0,0) caused by offset 16/04/ ATLCE - D DDC 2016 DDC 60

61 Bipolar D/A converters 2 Translation of a unipolar characteristic Unipolar DAC No jump in (0,0) offset 16/04/ ATLCE - D DDC 2016 DDC 61

62 Bipolar D/A converters - 3 Sign inversion of reference voltage V R Requires 2-quadrant multiplying DAC 16/04/ ATLCE - D DDC 2016 DDC 62

63 Multiplying D/A converters Multiplying DAC allow for V R variations: I O = K D V R 1/2/4 quadrant capability Applications: Variable gain amplifiers (VGA) Bipolar DAC (with V R inversion) Ratiometric ADC (next lesson) 16/04/ ATLCE - D DDC 2016 DDC 63

64 Gain control with a DAC The DAC id used as feedback (or input) transconductance. The D/A must allow V R sign inversion: I O = K D V R 16/04/ ATLCE - D DDC 2016 DDC 64

65 Lesson D2 final test How can we correct offset and gain errors of a DAC? Can we correct nonlinearity errors? Define non-monotonicity error. Which circuits can be used to reduce glitches? Which is the main problem of weighted resistors DAC circuits? Which are the benefits of ladder networks? Explain the difference between voltage and current switches. Can we build a voltage-output DAC using a ladder network with current switches? Draw the block diagram of a 4+4 mixed DAC. 16/04/ ATLCE - D DDC 2016 DDC 65