Analog Integrated Circuit Design (Analog CMOS Circuit Design)

Size: px
Start display at page:

Download "Analog Integrated Circuit Design (Analog CMOS Circuit Design)"

Transcription

1 Aalog tegrate ircuit Desig (Aalog MOS ircuit Desig) Ali Heiary, Electrical Egieerig, g, Guila Uiversity Table of tets - MOs techology - troucti to MOS trasistor 3- urret mirror 4- Amplifier, active loa 5- Frequecy respse, stability a compesati 6- Noise i electric circuit 7- Offset 8- Example 9-Excersise

2 Refereces i. Aalog tegrate ircuit Desig, Davi Johs a Ke Marti, Joh iley & Ss, c., 997. ii. Desig of Aalog MOS tegrate ircuits, Behza Razavi, McGraw-Hill,. iii. Aalysis a Desig of Aalog tegrate ircuits, P.R.Gray, P.J.Hurst, S.H.ewis, a R.G.Meyer, Joh iley & Ss, c.,. iv. Aalog Desig Essetials, illy M.. Sase., 8. 3 MOS Basic Operati & arge-sigal Moelig 4

3 MOS Basic Operati & arge-sigal Moelig (threshol voltage) th φ + φ ms f Q + b Q ss hael is preset for th th 5 MOS Basic Operati & arge-sigal Moelig (Output characteristic) f ( ) For s the chael charge is uiform a equals to: Q & Q T & ε t 6 3

4 MOS Basic Operati & arge-sigal Moelig (Output characteristic) The chael resistace is equal: t R s σa qµ t Q µ µ 7 MOS Basic Operati & arge-sigal Moelig (Output characteristic) f we apply verysmall voltage to the rai respect to the source we Still have almost uiform chael a the the curret ca be calculate as. s µ R s 3 A voltage ctrolle resistor s 8 4

5 MOS Basic Operati & arge-sigal Moelig (Output characteristic) By icreasig s the chael thickess will ecrease i rai sie a therefore the chael resistace will icrease. ( ( )) Q ( x) x Aqµ E t( x) qµ Q ( x) µ v x v x 9 MOS Basic Operati & arge-sigal Moelig (Output characteristic) ( ( x) ) µ v x s ( x ) x ( ) µ v µ ohmic s s 5

6 MOS Basic Operati & arge-sigal Moelig (Output characteristic) Ohmic regi 3 hat happes at > s? 3 s MOS Basic Operati & arge-sigal Moelig (Output characteristic) At s the chael i rai sies will piche off a therefore icreasig s caot Ohmic regi icrease the rai curret aymore. (The extra voltage will rop piche regi. 3 Active regi active µ ( ) th s 6

7 MOS Basic Operati & arge-sigal Moelig (chael shorteig effect ) 3 MOS Basic Operati & arge-sigal Moelig (chael shorteig effect ) 3 s 4 7

8 MOS Basic Operati & arge-sigal Moelig (chael shorteig effect ) ( ) ε + φ kt si s a φ l qna q i N N active s > active s + s ( ) s s ε qn ( + φ ) s si a 5 MOS Basic Operati & arge-sigal Moelig (chael shorteig effect ) active λ Early voltage: ( ) + λ( ) th µ ε qn ( + φ ) s si E a r s ( ) g ( +φ ) s ε si qn a s s s λ λ E 6 8

9 MOS Basic Operati & arge-sigal Moelig (chael shorteig effect ) For + φ -3 & 6 cm s N a E 8 µm E r s 7 th MOS Basic Operati & arge-sigal Moelig (Boy effect) As the source-bulk voltage, sb, becomes larger the epleti regi betwee the chael a the substrate becomes wier, a therefore Q b, i th compet will icrease which result to larger th. th Qb Qss φms + φ f + ( φ + φ ) th + f sb γ f γ qε N si a 8 9

10 MOS Basic Operati & Small-Sigal Moelig i active regi 9 MOS Basic Operati & Small-Sigal Moelig i active regi g ( ) µ th m µ g m ( ) th g s s th th s γ φ + f sb g m

11 MOS Basic Operati & Small-Sigal Moelig i active regi + 3 ov g ov sb ( A + A ) s ch j + φ sb + P s j sw b A j + P + φ b j sw MOS Basic Operati & Small-Sigal Moelig i ohmic regi g + ov sb b ( As + Ach ) j + Ps j sw + sb φ ( A + A ) ch + j b + P φ j sw

12 MOS Basic Operati & Small-Sigal Moelig i OFF regi g ov sb b A s A j + P s + sb φ j + P + φ b j sw j sw? gb 3 MOS Basic Operati & Small-Sigal Moelig i OFF regi gb is a ew capacitor which is the gate-to-substrate to capacitace. This capacitor is highly liear a epeet the gate voltage. i accumulati: gb 4

13 MOS Basic Operati & Small-Sigal Moelig i OFF regi f the gate-to-sourceto voltage is arou, the gb is equal to i series with the chael-to-bulk epleti capacitace a is much smaller, especially whe the substrate is lightly ope: ep. + 5 MOS Basic Operati & Small-Sigal Moelig i OFF regi Fially, for th, iversi layer exist a ay chage will chage the amout of charge i this layer. gb 6 3

14 MOS Basic Operati & Small-Sigal Moelig i OFF regi gb ow freq. accumulati Depl. iversi ow freq. high freq. 7 MOS Basic Operati (short-chael effect) The most importat short-chael effect i MOS is ue to elocity Saturati. At high electric fiels the carrier velocities approach thermal velocities. Subsequetly carrier velocity icreases less slowly tha it woul liearly at low electric fiel. oltage supply reucti is ot as fast as the feature size shrikig. So the effect of mobility egraati ca be see i more avace techology.. 8 4

15 MOS Basic Operati (weak iversi) Up to ow we ly csiere the rift curret of iverte chael. A therefore, the curret below threshol csiere to be zero. However eve below threshol (weak iversi) there is some iffusi curret ue to ifferece i surface potetial at rai a source sies. The rai curret i weak iversi ca be calculate as: t exp T th exp T s 9 MOS Basic Operati (weak iversi) For s >> T this curret ca be writte as: t th exp exp T T g m T gm T 3 5

16 MOS Basic Operati (weak iversi) But where is the borer of these two, strg iversi (si) a weak iversi (wi) regi. th > ( 7m) T si 3 MOS Basic Operati (weak iversi) cstat elocity saturati (S) 3 6

17 MOS Basic Operati (weak iversi) 33 g m MOS Basic Operati (weak iversi) gm T gm ater we will explai more about weak iversi with some example. t 34 7

18 MOS Basic Operati (weak iversi)simulati results 35 The MOS parameter for ha calculati mos moel T.7 [] GAMA.45 PH.9[] NSUB9e4 [cm-3] D.8e-6 [m] U 35[cm/vs] AMBDA. [v-] TOX9e-9[m] PB.9 [] J.56e-3[F/m] JS.35e- [F/m] MJ.45 MJS. GDO.4e-9 [F/m] pmos moel T-.8 [] GAMA.4 PH.8[] NSUB5e4 [cm-3] D.9e-6 [m] U [cm/vs] AMBDA. [v-] TOX9e-9[m] PB.9 [] J.94e-3[F/m] JS.3e- [F/m] MJ. 5 MJS.3 GDO.5e-8 [F/m] 36 8

Lecture 9. NMOS Field Effect Transistor (NMOSFET or NFET)

Lecture 9. NMOS Field Effect Transistor (NMOSFET or NFET) ecture 9 MOS Field ffect Trasistor (MOSFT or FT) this lecture you will lear: The oeratio ad workig of the MOS trasistor A MOS aacitor with a hael otact ( Si) metal cotact Si Si GB B versio layer PSi substrate

More information

Semiconductor Device Modeling and Characterization EE5342, Lecture 21 -Sp 2002

Semiconductor Device Modeling and Characterization EE5342, Lecture 21 -Sp 2002 Semicoductor Device Modelig ad Characterizatio EE5342 ecture 21 -Sp 2002 Professor Roald. Carter roc@uta.edu http://www.uta.edu/roc/ 21 02Apr02 1 Fully biased -MOS capacitor Chael if G > G S E x > 0 +

More information

2.CMOS Transistor Theory

2.CMOS Transistor Theory CMOS LSI esig.cmos rasistor heory Fu yuzhuo School of microelectroics,sju Itroductio omar fadhil,baghdad outlie PN juctio priciple CMOS trasistor itroductio Ideal I- characteristics uder static coditios

More information

Compact Modeling of Noise in the MOS Transistor

Compact Modeling of Noise in the MOS Transistor Compact Modelig of Noise i the MOS Trasistor Aada Roy, Christia Ez, ) Swiss Federal Istitute of Techology, ausae (EPF), Switzerlad ) Swiss Ceter for Electroics ad Microtechology (CSEM) Neuchâtel, Swtzerlad

More information

Overview of Silicon p-n Junctions

Overview of Silicon p-n Junctions Overview of Silico - Juctios r. avid W. Graham West irgiia Uiversity Lae eartmet of omuter Sciece ad Electrical Egieerig 9 avid W. Graham 1 - Juctios (iodes) - Juctios (iodes) Fudametal semicoductor device

More information

EE415/515 Fundamentals of Semiconductor Devices Fall 2012

EE415/515 Fundamentals of Semiconductor Devices Fall 2012 090 EE4555 Fudaetals of Seicoductor evices Fall 0 ecture : MOSFE hapter 0.3, 0.4 090 J. E. Morris Reider: Here is what the MOSFE looks like 090 N-chael MOSFEs: Ehaceet & epletio odes 090 J. E. Morris 3

More information

Mixed Signal IC Design Notes set 7: Electrical device noise models.

Mixed Signal IC Design Notes set 7: Electrical device noise models. C145C /18C otes, M. owell, copyrighte 007 Mixe Sigal C Desig Notes set 7: lectrical evice oise moels. Mark owell Uiversity of Califoria, Sata Barbara rowell@ece.ucsb.eu 805-893-344, 805-893-36 fax Topics

More information

CMOS. Dynamic Logic Circuits. Chapter 9. Digital Integrated Circuits Analysis and Design

CMOS. Dynamic Logic Circuits. Chapter 9. Digital Integrated Circuits Analysis and Design MOS Digital Itegrated ircuits Aalysis ad Desig hapter 9 Dyamic Logic ircuits 1 Itroductio Static logic circuit Output correspodig to the iput voltage after a certai time delay Preservig its output level

More information

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018 ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um

More information

ECE 145B / 218B, notes set 3: Electrical device noise models.

ECE 145B / 218B, notes set 3: Electrical device noise models. class otes, M. owell, copyrighte 2012 C 145B / 218B, otes set 3: lectrical evice oise moels. Mark owell Uiversity of Califoria, Sata Barbara rowell@ece.ucsb.eu 805-893-3244, 805-893-3262 fax class otes,

More information

Modulation Doping HEMT/HFET/MODFET

Modulation Doping HEMT/HFET/MODFET ecture 7: High lectro Mobility raitor Modulatio opig HM/HF/MOF evice tructure hrehold voltage Calculate the curret uig drit ect o velocity aturatio 04-0-30 ecture 7, High Speed evice 04 Fudametal MSF Problem

More information

Capacitors and PN Junctions. Lecture 8: Prof. Niknejad. Department of EECS University of California, Berkeley. EECS 105 Fall 2003, Lecture 8

Capacitors and PN Junctions. Lecture 8: Prof. Niknejad. Department of EECS University of California, Berkeley. EECS 105 Fall 2003, Lecture 8 CS 15 Fall 23, Lecture 8 Lecture 8: Capacitor ad PN Juctio Prof. Nikejad Lecture Outlie Review of lectrotatic IC MIM Capacitor No-Liear Capacitor PN Juctio Thermal quilibrium lectrotatic Review 1 lectric

More information

Lecture 9: Diffusion, Electrostatics review, and Capacitors. Context

Lecture 9: Diffusion, Electrostatics review, and Capacitors. Context EECS 5 Sprig 4, Lecture 9 Lecture 9: Diffusio, Electrostatics review, ad Capacitors EECS 5 Sprig 4, Lecture 9 Cotext I the last lecture, we looked at the carriers i a eutral semicoductor, ad drift currets

More information

Lecture 10: P-N Diodes. Announcements

Lecture 10: P-N Diodes. Announcements EECS 15 Sprig 4, Lecture 1 Lecture 1: P-N Diodes EECS 15 Sprig 4, Lecture 1 Aoucemets The Thursday lab sectio will be moved a hour later startig this week, so that the TA s ca atted lecture i aother class

More information

Parasitic Resistance L R W. Polysilicon gate. Drain. contact L D. V GS,eff R S R D. Drain

Parasitic Resistance L R W. Polysilicon gate. Drain. contact L D. V GS,eff R S R D. Drain Parasitic Resistace G Polysilico gate rai cotact V GS,eff S R S R S, R S, R + R C rai Short Chael Effects Chael-egth Modulatio Equatio k ( V V ) GS T suggests that the trasistor i the saturatio mode acts

More information

FIELD-EFFECT TRANSISTORS

FIELD-EFFECT TRANSISTORS FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

More information

Bipolar Junction Transistors

Bipolar Junction Transistors ipolar Juctio Trasistors ipolar juctio trasistor (JT) was iveted i 948 at ell Telephoe Laboratories Sice 97, the high desity ad low power advatage of the MOS techology steadily eroded the JT s early domiace.

More information

Summary of pn-junction (Lec )

Summary of pn-junction (Lec ) Lecture #12 OUTLNE Diode aalysis ad applicatios cotiued The MOFET The MOFET as a cotrolled resistor Pich-off ad curret saturatio Chael-legth modulatio Velocity saturatio i a short-chael MOFET Readig Howe

More information

Regenerative Property

Regenerative Property DESIGN OF LOGIC FAMILIES Some desirable characteristics to have: 1. Low ower dissiatio. High oise margi (Equal high ad low margis) 3. High seed 4. Low area 5. Low outut resistace 6. High iut resistace

More information

Lecture #25. Amplifier Types

Lecture #25. Amplifier Types ecture #5 Midterm # formatio ate: Moday November 3 rd oics to be covered: caacitors ad iductors 1 st -order circuits (trasiet resose) semicoductor material roerties juctios & their alicatios MOSFEs; commo-source

More information

Introduction to Microelectronics

Introduction to Microelectronics The iolar Juctio Trasistor Physical Structure of the iolar Trasistor Oeratio of the NPN Trasistor i the Active Mode Trasit Time ad Diffusio aacitace Ijectio fficiecy ad ase Trasort Factor The bers-moll

More information

Digital Integrated Circuits. Inverter. YuZhuo Fu. Digital IC. Introduction

Digital Integrated Circuits. Inverter. YuZhuo Fu. Digital IC. Introduction Digital Itegrated Circuits Iverter YuZhuo Fu Itroductio outlie CMOS at a glace CMOS static behavior CMOS dyamic behavior Power, Eergy, ad Eergy Delay Persective tech. /48 outlie CMOS at a glace CMOS static

More information

Electrical Resistance

Electrical Resistance Electrical Resistace I + V _ W Material with resistivity ρ t L Resistace R V I = L ρ Wt (Uit: ohms) where ρ is the electrical resistivity Addig parts/billio to parts/thousad of dopats to pure Si ca chage

More information

ECE606: Solid State Devices Lecture 19 Bipolar Transistors Design

ECE606: Solid State Devices Lecture 19 Bipolar Transistors Design 606: Solid State Devices Lecture 9 ipolar Trasistors Desig Gerhard Klimeck gekco@purdue.edu Outlie ) urret gai i JTs ) osideratios for base dopig 3) osideratios for collector dopig 4) termediate Summary

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Itegrated Circuits YuZhuo Fu cotact:fuyuzhuo@ic.sjtu.edu.c Office locatio:417 room WeiDiaZi buildig,no 800 DogChua road,mihag Camus Itroductio outlie CMOS at a glace CMOS static behavior CMOS dyamic

More information

EE C245 - ME C218 Introduction to MEMS Design Fall Today s Lecture

EE C245 - ME C218 Introduction to MEMS Design Fall Today s Lecture EE C45 ME C8 Itroductio to MEMS Desig Fall 003 Roger Howe ad Thara Sriiasa Lecture 3 Capacitie Positio Sesig: Electroic ad Mechaical Noise EE C45 ME C8 Fall 003 Lecture 3 Today s Lecture Basic CMOS buffer

More information

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @

More information

Crash course part 2. Frequency compensation

Crash course part 2. Frequency compensation Crash course part Frequecy compesatio Ageda Frequecy depedace Feedback amplifiers Frequecy depedace of the Trasistor Frequecy Compesatio Phatom Zero Examples Crash course part poles ad zeros I geeral a

More information

Semiconductors a brief introduction

Semiconductors a brief introduction Semicoductors a brief itroductio Bad structure from atom to crystal Fermi level carrier cocetratio Dopig Readig: (Sedra/Smith 7 th editio) 1.7-1.9 Trasport (drift-diffusio) Hyperphysics (lik o course homepage)

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF ALIFORNIA, BERELEY ollege of Egieerig Deartmet of Electrical Egieerig ad omuter Scieces Ja M. Rabaey Homework #5 EES 4 SP0) [PROBLEM Elmore Delay 30ts) Due Friday, March 5, 5m, box i 40 ory

More information

Chapter 9 - CD companion 1. A Generic Implementation; The Common-Merge Amplifier. 1 τ is. ω ch. τ io

Chapter 9 - CD companion 1. A Generic Implementation; The Common-Merge Amplifier. 1 τ is. ω ch. τ io Chapter 9 - CD compaio CHAPTER NINE CD-9.2 CD-9.2. Stages With Voltage ad Curret Gai A Geeric Implemetatio; The Commo-Merge Amplifier The advaced method preseted i the text for approximatig cutoff frequecies

More information

ELEC1200: A System View of Communications: from Signals to Packets Lecture 3

ELEC1200: A System View of Communications: from Signals to Packets Lecture 3 ELEC2: A System View of Commuicatios: from Sigals to Packets Lecture 3 Commuicatio chaels Discrete time Chael Modelig the chael Liear Time Ivariat Systems Step Respose Respose to sigle bit Respose to geeral

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

YuZhuo Fu Office location:417 room WeiDianZi building,no 800 DongChuan road,minhang Campus

YuZhuo Fu Office location:417 room WeiDianZi building,no 800 DongChuan road,minhang Campus Digital Itegrated Circuits YuZhuo Fu cotact:fuyuzhuo@ic.sjtu.edu.c Office locatio:417 room WeiDiaZi buildig,no 800 DogChua road,mihag Camus Itroductio Digital IC outlie CMOS at a glace CMOS static behavior

More information

Metal Gate. Insulator Semiconductor

Metal Gate. Insulator Semiconductor MO Capacitor MO Metal- Oxide- emicoductor MO actually refers to Metal ilico Diide ilico Other material systems have similar MI structures formed by Metal Isulator emicoductor The capacitor itself forms

More information

Sinusoidal stimulus. Sin in Sin at every node! Phasors. We are going to analyze circuits for a single sinusoid at a time which we are going to write:

Sinusoidal stimulus. Sin in Sin at every node! Phasors. We are going to analyze circuits for a single sinusoid at a time which we are going to write: Siusoidal stimulus Si i Si at every ode! We are goig to aalyze circuits for a sigle siusoid at a time which we are goig to write: vi ( t i si( t + φ But we are goig to use expoetial otatio v ( t si( t

More information

LECTURE 5 PART 2 MOS INVERTERS STATIC DESIGN CMOS. CMOS STATIC PARAMETERS The Inverter Circuit and Operating Regions

LECTURE 5 PART 2 MOS INVERTERS STATIC DESIGN CMOS. CMOS STATIC PARAMETERS The Inverter Circuit and Operating Regions LECTURE 5 PART 2 MOS INVERTERS STATIC ESIGN CMOS Objectives for Lecture 5 - Part 2* Uderstad the VTC of a CMOS iverter. Uderstad static aalysis of the CMOS iverter icludig breakpoits, VOL, V OH,, V IH,

More information

Butterworth LC Filter Designer

Butterworth LC Filter Designer Butterworth LC Filter Desiger R S = g g 4 g - V S g g 3 g R L = Fig. : LC filter used for odd-order aalysis g R S = g 4 g V S g g 3 g - R L = useful fuctios ad idetities Uits Costats Table of Cotets I.

More information

Formation of A Supergain Array and Its Application in Radar

Formation of A Supergain Array and Its Application in Radar Formatio of A Supergai Array ad ts Applicatio i Radar Tra Cao Quye, Do Trug Kie ad Bach Gia Duog. Research Ceter for Electroic ad Telecommuicatios, College of Techology (Coltech, Vietam atioal Uiversity,

More information

ln(i G ) 26.1 Review 26.2 Statistics of multiple breakdowns M Rows HBD SBD N Atoms Time

ln(i G ) 26.1 Review 26.2 Statistics of multiple breakdowns M Rows HBD SBD N Atoms Time EE650R: Reliability Physics of Naoelectroic Devices Lecture 26: TDDB: Statistics of Multiple Breadows Date: Nov 17, 2006 ClassNotes: Jaydeep P. Kulari Review: Pradeep R. Nair 26.1 Review I the last class

More information

Chapter 5 Carrier transport phenomena

Chapter 5 Carrier transport phenomena Chater 5 Carrier trasort heomea W.K. Che lectrohysics, NCTU Trasort The et flow of electros a holes i material is calle trasort Two basic trasort mechaisms Drift: movemet of charge ue to electric fiels

More information

1. pn junction under bias 2. I-Vcharacteristics

1. pn junction under bias 2. I-Vcharacteristics Lecture 10 The p Juctio (II) 1 Cotets 1. p juctio uder bias 2. I-Vcharacteristics 2 Key questios Why does the p juctio diode exhibit curret rectificatio? Why does the juctio curret i forward bias icrease

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 006 Microelectroic Devices ad Circuits Prof. Ja M. Rabaey (ja@eecs) Lecture 3: Semicoductor Basics (ctd) Semicoductor Maufacturig Overview Last lecture Carrier velocity ad mobility Drift currets

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

Minimum Source/Drain Area AS,AD = (0.48µm)(0.60µm) - (0.12µm)(0.12µm) = µm 2

Minimum Source/Drain Area AS,AD = (0.48µm)(0.60µm) - (0.12µm)(0.12µm) = µm 2 UNIERSITY OF CALIFORNIA College of Egieerig Departmet of Electrical Egieerig ad Computer Scieces Last modified o February 1 st, 005 by Chris Baer (crbaer@eecs Adrei ladimirescu Homewor #3 EECS141 Due Friday,

More information

Monolithic semiconductor technology

Monolithic semiconductor technology Moolithic semicoductor techology 1 Ageda Semicoductor techology: Backgroud o Silico ad Gallium Arseide (GaAs) roerties. Diode, BJT ad FET devices. Secod order effect ad High frequecy roerties. Modelig

More information

EE 505. Lecture 13. String DACs

EE 505. Lecture 13. String DACs EE 505 Lecture 13 Strig DACs -Strig DAC V FF S 1 S 2 Simple structure Iheretly mootoe Very low DNL Challeges: S N-2 S N-1 S N S k d k Maagig INL Large umber of devices for large outig thermometer/bubble

More information

Why analog microelectronics?

Why analog microelectronics? hy aalo microelectroics? iital is taki over? Yes, but electrical sials are fudametally aalo! Aalo desi has prove fudametal for hihquality desi of complex systems Mixed-mode systems Natural sials are aalo

More information

100m m 01.0

100m m 01.0 EKT Priciples of Measureet ad struetatio Se. 0/0 Solutio Tutorial (Chapter ) Q. (a) Briefly discuss the operatio of a Peraet Maget Movig Coil (PMMC) oveet ad also describe TWO() advatages of PMMC. PMMC

More information

ECE594I Notes set 13: Two-port Noise Parameters

ECE594I Notes set 13: Two-port Noise Parameters C594 otes, M. Rodwell, copyrighted C594 Notes set 13: Two-port Noise Parameters Mark Rodwell Uiversity of Califoria, Sata Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax Refereces ad Citatios:

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Basic Concepts of Electricity. n Force on positive charge is in direction of electric field, negative is opposite

Basic Concepts of Electricity. n Force on positive charge is in direction of electric field, negative is opposite Basic Cocepts of Electricity oltage E Curret I Ohm s Law Resistace R E = I R 1 Electric Fields A electric field applies a force to a charge Force o positive charge is i directio of electric field, egative

More information

EE 560 MOS TRANSISTOR THEORY

EE 560 MOS TRANSISTOR THEORY 1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

More information

CMOS Digital Integrated Circuits Analysis and Design

CMOS Digital Integrated Circuits Analysis and Design MOS igital ntegrated ircuits Analysis and esign hapter 4 Modeling of MOS ransistors Using SPE 1 ntroduction he SPE software that was distributed by U Berkeley beginning in the late 1970s had three built-in

More information

Semiconductor Electronic Devices

Semiconductor Electronic Devices Semicoductor lectroic evices Course Codes: 3 (UG) 818 (PG) Lecturer: Professor thoy O eill mail: athoy.oeill@cl.ac.uk ddress: 4.31, Merz Court ims: To provide a specialist kowledge of semicoductor devices.

More information

OBJECTIVES. Chapter 1 INTRODUCTION TO INSTRUMENTATION FUNCTION AND ADVANTAGES INTRODUCTION. At the end of this chapter, students should be able to:

OBJECTIVES. Chapter 1 INTRODUCTION TO INSTRUMENTATION FUNCTION AND ADVANTAGES INTRODUCTION. At the end of this chapter, students should be able to: OBJECTIVES Chapter 1 INTRODUCTION TO INSTRUMENTATION At the ed of this chapter, studets should be able to: 1. Explai the static ad dyamic characteristics of a istrumet. 2. Calculate ad aalyze the measuremet

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "

More information

EE 505. Lecture 28. ADC Design SAR

EE 505. Lecture 28. ADC Design SAR EE 505 Lecture 28 ADC Desig SAR Review from Last Lecture Elimiatio of Iput S/H C LK X IN S/H Stage 1 r 1 Stage 2 r 2 Stage k r k Stage m r m 1 2 k m Pipelied Assembler (Shift Register

More information

EE 130 Intro to MS Junctions Week 6 Notes. What is the work function? Energy to excite electron from Fermi level to the vacuum level

EE 130 Intro to MS Junctions Week 6 Notes. What is the work function? Energy to excite electron from Fermi level to the vacuum level EE 13 Intro to S Junctions eek 6 Notes Problem 1 hat is the work function? Energy to ecite electron from Fermi level to the vacuum level Electron affinity of 4.5eV Electron affinity of Ge 4.eV orkfunction

More information

Schottky diodes: I-V characteristics

Schottky diodes: I-V characteristics chottky diodes: - characteristics The geeral shape of the - curve i the M (-type) diode are very similar to that i the p + diode. However the domiat curret compoets are decidedly differet i the two diodes.

More information

Lecture 3. Electron and Hole Transport in Semiconductors

Lecture 3. Electron and Hole Transport in Semiconductors Lecture 3 lectro ad Hole Trasort i Semicoductors I this lecture you will lear: How electros ad holes move i semicoductors Thermal motio of electros ad holes lectric curret via lectric curret via usio Semicoductor

More information

EEC 118 Lecture #4: CMOS Inverters. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #4: CMOS Inverters. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #4: CMOS Iverters ajeeva Amirtharajah Uiversity of Califoria, Davis Jeff Parhurst Itel Cororatio Outlie eview: Iverter Trasfer Characteristics Lecture 3: Noise Margis, ise & Fall Times,

More information

Chapter 2 Motion and Recombination of Electrons and Holes

Chapter 2 Motion and Recombination of Electrons and Holes Chapter 2 Motio ad Recombiatio of Electros ad Holes 2.1 Thermal Eergy ad Thermal Velocity Average electro or hole kietic eergy 3 2 kt 1 2 2 mv th v th 3kT m eff 3 23 1.38 10 JK 0.26 9.1 10 1 31 300 kg

More information

D. A. D Ippolito, J. R. Myra, and D. A. Russell Lodestar Research Corporation

D. A. D Ippolito, J. R. Myra, and D. A. Russell Lodestar Research Corporation D. A. D Ippolito, J. R. Myra, ad D. A. Russell Research Corporatio Preseted at the 33rd EPS Coferece o Plasma Physics, Rome, Italy, Jue 9-3, 6 Coheret structures ( blobs ) created by edge turbulece covective

More information

Olli Simula T / Chapter 1 3. Olli Simula T / Chapter 1 5

Olli Simula T / Chapter 1 3. Olli Simula T / Chapter 1 5 Sigals ad Systems Sigals ad Systems Sigals are variables that carry iformatio Systemstake sigals as iputs ad produce sigals as outputs The course deals with the passage of sigals through systems T-6.4

More information

EE3310 Class notes Part 3. Solid State Electronic Devices - EE3310 Class notes Transistors

EE3310 Class notes Part 3. Solid State Electronic Devices - EE3310 Class notes Transistors EE3310 Class otes Part 3 Versio: Fall 2002 These class otes were origially based o the hadwritte otes of Larry Overzet. It is expected that they will be modified (improved?) as time goes o. This versio

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

Microelectronics Part 1: Main CMOS circuits design rules

Microelectronics Part 1: Main CMOS circuits design rules GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

More information

mx bx kx F t. dt IR I LI V t, Q LQ RQ V t,

mx bx kx F t. dt IR I LI V t, Q LQ RQ V t, Lecture 5 omplex Variables II (Applicatios i Physics) (See hapter i Boas) To see why complex variables are so useful cosider first the (liear) mechaics of a sigle particle described by Newto s equatio

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

ESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15

ESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15 ESE 570 MOS TRANSISTOR THEORY Part 1 TwoTerminal MOS Structure 2 GATE Si Oxide interface n n Mass Action Law VB 2 Chemical Periodic Table Donors American Chemical Society (ACS) Acceptors Metalloids 3 Ideal

More information

ELEG 4603/5173L Digital Signal Processing Ch. 1 Discrete-Time Signals and Systems

ELEG 4603/5173L Digital Signal Processing Ch. 1 Discrete-Time Signals and Systems Departmet of Electrical Egieerig Uiversity of Arasas ELEG 4603/5173L Digital Sigal Processig Ch. 1 Discrete-Time Sigals ad Systems Dr. Jigxia Wu wuj@uar.edu OUTLINE 2 Classificatios of discrete-time sigals

More information

Basic Physics of Semiconductors

Basic Physics of Semiconductors Chater 2 Basic Physics of Semicoductors 2.1 Semicoductor materials ad their roerties 2.2 PN-juctio diodes 2.3 Reverse Breakdow 1 Semicoductor Physics Semicoductor devices serve as heart of microelectroics.

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Itegrated Circuits YuZhuo Fu cotact:fuyuzhuo@ic.sjtu.edu.c Office locatio:417 room WeiDiaZi buildig,no 800 DogChua road,mihag Camus Itroductio Review cotet Tye Cocet 15, Comutig 10 hours Fri. 6

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

Analysis of MOS Capacitor Loaded Annular Ring MICROSTRIP Antenna

Analysis of MOS Capacitor Loaded Annular Ring MICROSTRIP Antenna Iteratioal OPEN AESS Joural Of Moder Egieerig Research (IJMER Aalysis of MOS apacitor Loaded Aular Rig MIROSTRIP Atea Mohit Kumar, Suredra Kumar, Devedra Kumar 3, Ravi Kumar 4,, 3, 4 (Assistat Professor,

More information

The Scattering Matrix

The Scattering Matrix 2/23/7 The Scatterig Matrix 723 1/13 The Scatterig Matrix At low frequecies, we ca completely characterize a liear device or etwork usig a impedace matrix, which relates the currets ad voltages at each

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

VCC operational principle explained

VCC operational principle explained APPNIX Voltage-cotrolle capacitors (capacitace trasformers) From a circuit esiger s poit of view ay ioe is o more tha a o-liear resistor whereas a trasistor is simply a voltage-cotrolle o-liear resistor

More information

Time-Domain Representations of LTI Systems

Time-Domain Representations of LTI Systems 2.1 Itroductio Objectives: 1. Impulse resposes of LTI systems 2. Liear costat-coefficiets differetial or differece equatios of LTI systems 3. Bloc diagram represetatios of LTI systems 4. State-variable

More information

BLUE PRINT FOR MODEL QUESTION PAPER 3

BLUE PRINT FOR MODEL QUESTION PAPER 3 Uit Chapter Number Number of teachig Hours Weightage of marks Mark Marks Marks 5 Marks (Theory) 5 Marks (Numerical Problem) BLUE PNT FO MODEL QUESTON PAPE Class : PUC Subject : PHYSCS () CHAPTES Electric

More information

3. Modeling of MOSFET for analog design. Kanazawa University Microelectronics Research Lab. Akio Kitagawa

3. Modeling of MOSFET for analog design. Kanazawa University Microelectronics Research Lab. Akio Kitagawa 3. Modelig of MOSFET for aalog desig Kaazawa Uiversity Microelectroics Research Lab. Akio Kitagawa SPCE model of MOSFET Model Feature Level 1 Basic physical model(l > 10um Level 3 Basic semi-empirical

More information

Lecture 5: HBT DC Properties. Basic operation of a (Heterojunction) Bipolar Transistor

Lecture 5: HBT DC Properties. Basic operation of a (Heterojunction) Bipolar Transistor Lecture 5: HT C Properties asic operatio of a (Heterojuctio) ipolar Trasistor Abrupt ad graded juctios ase curret compoets Quasi-Electric Field Readig Guide: 143-16: 17-177 1 P p ++.53 Ga.47 As.53 Ga.47

More information

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania 1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION

More information

Introduction to Signals and Systems, Part V: Lecture Summary

Introduction to Signals and Systems, Part V: Lecture Summary EEL33: Discrete-Time Sigals ad Systems Itroductio to Sigals ad Systems, Part V: Lecture Summary Itroductio to Sigals ad Systems, Part V: Lecture Summary So far we have oly looked at examples of o-recursive

More information

MORE TUTORIALS FOR VERILOG DIGITAL ELECTRONICS SYSTEM DESIGN HOMEWORK ASSIGNMENTS DATASHEETS FOR PARTS 10/3/2018

MORE TUTORIALS FOR VERILOG DIGITAL ELECTRONICS SYSTEM DESIGN HOMEWORK ASSIGNMENTS DATASHEETS FOR PARTS 10/3/2018 //8 DIGITA EECTRONICS SYSTEM DESIGN FA 8 PROFS. IRIS BAHAR & ROD BERESFORD OCTOBER, 8 ECTURE 9: CMOS TRANSIENT BEHAIOR MORE TUTORIAS FOR ERIOG O the course website you ca fid some useful liks to additioal

More information

FYS Vår 2016 (Kondenserte fasers fysikk)

FYS Vår 2016 (Kondenserte fasers fysikk) FYS3410 - Vår 2016 (Kodeserte fasers fysikk) http://www.uio.o/studier/emer/matat/fys/fys3410/v16/idex.html Pesum: Itroductio to Solid State Physics by Charles Kittel (Chapters 1-9 ad 17, 18, 20) Adrej

More information

Transistors - CPE213 - [4] Bipolar Junction Transistors. Bipolar Junction Transistors (BJTs) Modes of Operation

Transistors - CPE213 - [4] Bipolar Junction Transistors. Bipolar Junction Transistors (BJTs) Modes of Operation P1 lectroic evices for omuter gieerig [4] iolar Juctio Trasistors Trasistors Threetermial device otrolled source Fuctios Amlificatio Switchig Tyes iolar juctio trasistor (JT) Field effect trasistor (FT)

More information

Magnetic Length Sensor MLS (Hybrid)

Magnetic Length Sensor MLS (Hybrid) Small Hybride Large Hybride AMR gradiet sesor Liear displacemet, movemets, velocities High precisio Various pole pitches available DESCRIPTION Slidig the MLS-Sesors alog a magetic scale will produce a

More information

istributed by: www.ameco.com -800-83-4242 The content and copyrights of the attached material are the property of its owner. 27002T -CHAEL EHACEMET MOE FIEL EFFECT TRASISTOR Features EW PROUCT Low On-Resistance

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects

More information

First, note that the LS residuals are orthogonal to the regressors. X Xb X y = 0 ( normal equations ; (k 1) ) So,

First, note that the LS residuals are orthogonal to the regressors. X Xb X y = 0 ( normal equations ; (k 1) ) So, 0 2. OLS Part II The OLS residuals are orthogoal to the regressors. If the model icludes a itercept, the orthogoality of the residuals ad regressors gives rise to three results, which have limited practical

More information

Chapter 2 MOS Transistor theory

Chapter 2 MOS Transistor theory Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the

More information

Lecture 010 ECE4430 Review I (12/29/01) Page 010-1

Lecture 010 ECE4430 Review I (12/29/01) Page 010-1 Lecture 010 4430 Review I (12/29/01) Page 0101 LTUR 010 4430 RVIW I (RAIN: HLM hap. 1) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught in 4430 2.) Insure

More information

EE 505. Lecture 29. ADC Design. Oversampled

EE 505. Lecture 29. ADC Design. Oversampled EE 505 Lecture 29 ADC Desig Oversampled Review from Last Lecture SAR ADC V IN Sample Hold C LK V REF DAC DAC Cotroller DAC Cotroller stores estimates of iput i Successive Approximatio Register (SAR) At

More information