Combinational & Sequential Logic

Transcription

1 Combiatioal & Sequetial Logic ENGG23 2 d Semester, 27/8 Dr. Hade So Departmet of Electrical ad Electroic Egieerig Outlie Simplifig logic circuits Miimizatio b Boolea algebra Miimizatio b Karaugh maps Adders, mues ad other Sequetial circuits Output depeds o both the curret iput ad the state of the circuit Output of combiatioal circuit depeds ol o the curret iput Flip-Flops ENGG23 - H. So 2 3 Represetatios of Logic Fuctios Ol truth table represetatio is uique Boolea epressio ad schematics ca be rearraged to suit actual egieerig requiremet Truth Table LOGIC MINIMIZATION Schematics Boolea Epressio ENGG23 - H. So 3 ENGG23 - H. So 4

2 Wh rearrage logic circuits? I digital sstems: é o. of logic gates è é area è é power cosumptio é o. of logic gates usuall icreases dela of circuit è slower circuit Logic miimizatio helps to make logic circuits smaller, faster ad lower power cosumptio Two was to simplif logic circuits: Boolea Algebra K-Map ENGG23 - H. So 5 ENGG23 - H. So 6 Miimizatio b Algebra Make use of relatioships ad theorems of Boolea algebra to simplif the epressios this method relies o our algebraic skill E.g. Simplif ABC + AB (AC) = ABC + AB (A +C) [b DeMorga thm] = ABC + AB (A + C) [cacel double iverios] = ABC + ABA+ ABC [multipl out] = ABC + AB + ABC [A A = A] = AC(B + B) + AB = AC + AB [B + B =] Karaugh Map (K-map) A graphical tool to facilitate logic miimizatio Derive simplest SOP epressio b sstematicall loopig s i the K-map ABC + ABC + ABC + ABC A B C Y A Gra Code BC ENGG23 - H. So 7 ENGG23 - H. So 8

3 Loopig i K-Map To simplif logic epress, make loops aroud all s Rules: Loops cosist of rectagle blocks of adjacet s Size of a loop must be power of 2:, 2, 4, 8, 6, Use miimum umber of loops (use loops as big as possible) Loops ma overlap NOTE: Edges of K-map wrap aroud ABC + ABC + ABC + ABC BC Write out simplified epressio The simplified logic epressio is a sum of the epressio for each loop The epressio for each loop is the product of the commo terms ABC + ABC + ABC + ABC A BC A Simplified Epressio AC + BC ENGG23 - H. So 9 K-map with 4 iputs K-map ca be eteded to 4 or more iputs 4-iput K-map is similar to 3-iput K-map ecept both aes represet 2 variables each 5 or more iput rarel used as the require drawig map i 3D, 4D, or higher AB CD ENGG23 - H. So ENGG23 - H. So Eample: 4-iput K-map A B C D Y CD AB ENGG23 - H. So 2

4 More eamples o loopig of two Loopig group of four (quads) A K map ma cotai a group of four s that are adjacet to each other. This group is called quad Loopig a quad of adjacet s elimiates the two variables that appear i both complemeted ad ucomplemeted form Eamples: ENGG23 - H. So 3 ENGG23 - H. So 4 Loopig group of eight (Octets) A group of eight s that are adjacet to oe aother is called a octet Loopig a octet of adjacet s elimiates the three variables that appear i both complemeted ad ucomplemeted form Eamples: How K-map Works? Gra code ecodig i K-map esures that ol variable differs betwee ever two adjacet cells The loops help to etract commo terms i Boolea epressio Result is i simplest caoical SOP form A BC ABC + ABC = AC(B + B) = AC ENGG23 - H. So 5 ENGG23 - H. So 6

5 More eamples BC A Eamples: AB\CD AB\CD ABC + ABC + ABC = ABC + ABC + ABC + ABC = AC(B + B)+ BC(A + A) = AC + BC AB + CD BD + ABC ENGG23 - H. So 7 ENGG23 - H. So 8 Fillig out a Karaugh Map Give a iitial (usimplified) logic Boolea epressio Write the epressio i SOP form For each product term, write a i all the squares which are icluded i the term, elsewhere All variables preset i the product term: oe square Oe variable missig: two adjacet squares Two terms missig: 4 adjacet squares Eample : X = ABC+ ABC+ ABC+ ABC Eample 2: X = BC+ ABC+ AC Eample 3: X = B+ ABC+ A A\BC A\BC A\BC Do t Care Coditios I certai cases, some of the iput coditios ma ever occur or it ma ot matter what happes eve if the do I such cases we fill i the K map with a X meaig do't care Whe miimizig a X is like a "joker" X ca be or - whatever helps best with the miimizatio E.g.,: ABC will ever occur or we do t care what is the output eve if it occur A\BC X simplifies to B if X is assumed If we assume X =, the output becomes AB+BC, which is more complicated ENGG23 - H. So 9 ENGG23 - H. So 2

6 Quick Quiz AB\CD X X AB\CD X X 2 3 BCD + BD BCD + BD ABCD + BD 2 3 ABC + ACD + ACD + ABC ABC + ACD + ABC + BD ABC + ACD + ABC Puttig It Together MULTI-BIT ADDER 4 ABCD + BD 4 ABC + ACD + ACD + ABC ENGG23 - H. So 2 ENGG23 - H. So 22 Biar Numbers Represets umbers i base 2 E.g.: 23 = 2 Almost all computers toda utilize biar represetatio of umbers iterall Decimal Biar From Biar to Decimal Note that the value of a biar umber is give b: 2 i b i i= where b i is the digital at positio i, startig coutig from zero from the far right. Covertig from biar to decimal ca be doe b addig the power-of-2 where there is a ENGG23 - H. So 23 ENGG23 - H. So 24

7 Eample Covert the biar umber ito decimal represetatio Similar to Decimal = = = = = = = 238 ENGG23 - H. So 25 ENGG23 - H. So 26 From Decimal to Biar Ca be foud usig short divisio : Successivel divide the divided b 2 The remaiders form the resultig biar umber whe couted from the bottom Eample: Coverts 9 ito biar è 9 = 2 Positive Itegers No-egative biar umbers (,, 2, 3, ) ca be represeted aturall with bitstrigs that correspods to their biar represetatio Represets equall spaced itegers o the umber lie Sometimes called usiged iteger Value Biar Bitstrig (8- bit) ENGG23 - H. So 27 ENGG23 - H. So 28

8 Positive Itegers With a bitstrig of width, the followig properties hold: mi value : ma value : 2 The value of a bistrig { b b 2 b } ca be calculated as: 2 i b i E.g. The value of i= 2 = = = 23 ENGG23 - H. So 29 Positive Itegers Additio Two +ve itegers ca be added similar to the wa decimal umbers are added i log additio How do we implemet biar additio i hardware? ENGG23 - H. So 3 Half Adder Basic additio of two -bit values Geerate a carr out to the et bit if the result is 2 a b co s s = a b co = a b ENGG23 - H. So 3 + Full Adder The subsequet bits eed to be slightl smarter tha a half adder There ma be carr iput from the bit to the right A 3-iput fuctio (a, b, ci) ci a b co s s = a b ci co = a b + ci a + b ( ) + ENGG23 - H. So 32

9 Multi-bit Adder Both HA ad FA ca add bit ol A half-adder is simpl a full-adder with the carr iput tied to To make a multi-bit adder, we ca coect the carr output from oe FA to the carr iput of aother oe Start from least sigificat bit (usuall rightmost bit) ad propagate the carr to the left (the most sigificat bit) Mimic the actio of a log additio ENGG23 - H. So 33 + Multi-bit Adder Carr out a<3> b<3> a co FA s s<3> b ci a<2> b<2> a co FA s s<2> b ci a<> b<> a<> b<> Note: the <> otatio is a shorthad to deote a bit withi a multi-bit sigal. Other commo otatio: a(), a[], a, etc Egieer sometimes call multi-bit sigal a bus, or a sigal bus. ENGG23 - H. So 34 a co FA s s<> b ci a co FA s s<> b ci Bus Notatio 3 2 [3:] = 2 = 3 Bus Notatio Eample cout A bus is a budle of wire sigals that work idepedetl Most ofte used to deote a sigal with more tha bit e.g. a 32-bit value has 32 wires For a 32 bit sigal X, we use this otatio: X[3:] or X To refer to a particular bit of the bus, we use these otatios: X[2:] (3 bits startig from positio 2 dow to ) X[4] X4 As a covetio, we alwas deote the leftmost, aka most sigificat bit (MSB) with the largest ide i a bus. The rightmost, aka least sigificat bit (LSB) alwas has ide e.g. [3:] deotes a 4 bit sigals with the followig positio i a actual umber: a[3] a[2] a[] a[] b[3] b[2] b[] b[] ci s[3] s[2] s[] s[] a[3:] b[3:] cout ci s[3:] ENGG23 - H. So 35 ENGG23 - H. So 36

10 Multipleer (Mu) A B sel 2-to- mu if sel== { out=a } else { out=b } out sel[:] 4-to- mu out A mu passes oe of its N iputs to the output accordig to the value of its sel iput ENGG23 - H. So 37 A B C D 2 3 if sel== { out=a } else if sel== { out=b } else if sel==2 { out=c } else if sel==3 { out=d } Implemetig a 2-to- Mu Oe wa to implemet a mu is to treat it as a simple combiatioal logic: determie its truth table implemet the truth table usig logic gates Eample, a 2-to- mu sel a b out out = sel a + sel b ENGG23 - H. So 38 Short Summar Truth Table, Schematics ad Boolea Epressio are 3 differet was to represet the same fuctioalit Coversio betwee the 3 is relativel straight-forward TT is the ol represetatio that is uique Logic circuits ca be miimized/maipulated b Boolea algebra Ma use TTs for proofs as the are uique K map is a had graphical was to obtai miimized logic fuctios Combiatioal techiques allow us to build large circuits Multi-bit Adder from sigle-bit HA ad FA ENGG23 - H. So 39 ENGG23 - H. So 4

11 Combiatioal vs Sequetial Sequetial Combiatioal I combiatioal logic, the output is a pure fuctio of the preset iput ol, i.e. o memor effect I sequetial logic, the output depeds ot ol o the preset iput, but also o the histor of the iput, i.e. memor effect Sequetial Logic Sequetial logic circuits are circuits that cotais state elemets State elemets are circuits that remember its iput Allow a circuit to have memor of its past All state elemets of a circuit collectivel store the curret state of the circuit The output of the circuit depeds o both Curret Iput State (memor) of circuit ENGG23 - H. So 4 ENGG23 - H. So 42 Wh Sequetial Circuit? Itroduces the otio of time i the circuit Provide order to the operatio of the circuit E.g. part of a circuit must ot start computig util the iputs are read Coordiate differet parts of circuit to operate o the correct set of data E.g. A circuit that computes the fial grade should take iput (homework, eam grades, etc) of the same studet Recall previous values E.g. Echo cacellatio b subtractig previous output soud wave ms ago from iput sigals State Elemets A state elemet (circuit compoet) stores a or permaetl regardless of the chages i iput Simple eample (but ot quite useful): If is, the is, the is, If is, the is, the is, The value stored iside the circuit will ot chage To be useful: Need a wa to chage the state ENGG23 - H. So 43 ENGG23 - H. So 44

12 Flip-Flops A edge-trigger flip-flop (FF) is a circuit that chages it output ol whe the value of it s clock iput chages è = Risig Edge è = Fallig Edge Igore iput whe clock is ot chagig For simplicit, we will ol use risig edge triggered FF i this class A edge-triggerig sigal pi is usuall deoted b a wedge i the schematic smbol. D Flip-Flop Timig Diagram oe sigal per row D Q A D-FF has data iput port D, ad a sigle output port Q, plus Clock iput Optioal: reset (clear) iput Optioal: eable At the risig edge of clock sigal, the value at iput D is captured. Captured data is output at Q after a small dela I this class, it is deoted: T Q Igore all iput betwee clock edges time Schematic Smbol ENGG23 - H. So 45 ENGG23 - H. So 46 E Dela Lie/Shift Register a b a c b c Oe simple (but useful) wa to use DFFs is to form a dela lie. A dela lie with DFFs delas the iput sigal b clock ccles Note: I hardware desigs, all parts of the circuit operate i parallel Sice the same is coected to both DFFs, both of them operate schroousl Quick Quiz Which of the followig best describes the fuctio of the circuit above? alwas output the iverse of alwas output value of from previous ccle 2 outputs whe chages its value from previous ccle 3 4 outputs whe stas for 2 ccles ENGG23 - H. So 47 ENGG23 - H. So 48

13 Timig Timig is a delaed versio of = " combiatioal (regardless of ) time time ENGG23 - H. So 49 ENGG23 - H. So 5 Timig time if was i last clock ccle, but ow is, the becomes if was i last clock ccle, but ow is, the becomes Quick Quiz Eplaied The value at cotais the value of from previous ccle = " =, = =, = = TRUE iff eactl oe of the two is TRUE is TRUE if the value of chages from its value i previous ccle Note the DFF has give us memor of from previous ccle ENGG23 - H. So 5 ENGG23 - H. So 52

14 Eample Implemet Toggle FF with DFF A toggle flip-flop (T-flip-flop) toggles the output at risig clock edge whe the toggle sigal (T) is HIGH. Otherwise, the output remais uchaged. T Q T Q Ca we use a DFF to implemet a TFF? E: Implemetig TFF with DFF Step : Defie a sigal etq etq deotes the value that should be output at Q after the et clock edge Step : Epress etq as a fuctio of iput T ad Q Give the curret output Q is ad the iput at T is, the the et value of Q after the clock edge should be etq is a combiatioal fuctio o T,Q. Use a truth table to list out its behavior Q T T Q etq etq Curret ccle T Q Net ccle ENGG23 - H. So 53 ENGG23 - H. So 54 E: Implemet TFF usig DFF Step 2: Use a DFF to implemet the fuctio of storig etq ito Q after the et clock edge Q T etq Q Register A register is a parallel compositio of D-flip-flops. A -bit register cotais DFFs A register stores multi-bit values d3 d2 d q3 q2 q T Q etq ENGG23 - H. So 55 d q d q d ENGG23 - H. So q 56

15 Accumulator Accumulator A accumulator accumulates the iput values () ito the iterall stored sum o ever clock edge. NOTE X 2 curret_sum A B S et_sum sum sum Istead of simple ad, the value i the sigal X ad S are used The iitial value of S must be reset to the value zero for correct behavior It ca be costructed usig a adder with a register: Step : the et value of sum after the clock edge should be the sum of iput ad the curret_sum Step 2: At clock edge, we store the value of et_sum usig a register Step 3: the ewl stored value becomes the curret_sum after the clock edge ENGG23 - H. So 57 ENGG23 - H. So 58 Schroous vs Aschroous Sequetial Circuit This Course schroous Sequetial aschroous Combiatioal Schroous Sequetial Circuits A schroous sequetial circuit cotais eactl clock sigal All state elemets are coected to the same clock sigal è the state of the etire circuit is updated at the same time Commo form of schroous sequetial circuits: I schroous sequetial circuits, all state elemets are updated schroousl accordig to a sigle clock sigal iput Comb Logic Comb Logic Comb Logic Comb Logic output I aschroous sequetial circuits, state elemets ma be updated with multiple clocks, o clock sigal, or a other schemes. ENGG23 - H. So 59 ENGG23 - H. So 6

16 Clock Sigal A clock sigal is particularl importat sigal i a schroous sequetial circuit It cotrols the actio of all DFFs A clock sigal toggles betwee ad periodicall The frequec of the togglig determies the maimum speed of the circuit E.g.: i the accumulator eample earlier, the output S caot chage faster tha the clock frequec X 2 S clock period = clock frequec clock period e.g. Itel CPU rus at 3 GHz, Mobile phoe processors at GHz Lab FPGA board at 5 MHz Timig of Circuits So far, we have assumed: output of a combiatioal circuit chages istataeous w.r.t. iput Output of a FF chages istataeousl w.r.t. clock edge I realit, it takes fiite amout of time for a sigal to travel through a circuit. The timig of differet parts of a circuit ma cause glitches i output, limit the maimum speed of a desig ENGG23 - H. So 6 ENGG23 - H. So 62 Propagatio Dela a b c d Each logic gate icurs dela betwee the iput ad output to allow sigal to propagate Usuall referred as propagatio dela or gate dela Eact value is techolog-depedet I this class, we assume all gates have the same uit propagatio dela. The speed of a circuit is alwas limited b the slowest path 3 uits of dela from a to uit of dela from d to Worst case dela = 3 uits Timig i Schroous Circuits a b c d I a schroous sequetial circuit, sigal chages occur ol durig clock edge All sigals are therefore schroized to chage values right after a clock edge I the above eample, eed to make sure correct value of available BEFORE et clock edge Avoid glitches ENGG23 - H. So 63 ENGG23 - H. So 64

17 Timig i Schroous Circuits I geeral, the propagatio dela through the combiatioal logic betwee a two registers must be shorter tha the clock period The logest such path is called the critical path of the circuit The critical path determies the maimum clock speed Schroous Circuits Timig Comb Logic All chages betwee clock edges are igored a b Sice ol values right before the clock edge i the iput ports are captured A short period of time before a clock edge must be allocated to esure stable iputs Too small è Chace of failig circuit Too big è Wasted idle time Stable before clock edge ENGG23 - H. So 65 Sice all circuit rus o the same clock, clock frequec limited b the logest critical path ENGG23 - H. So 66 Google TPU Tesor Processig Uit A dedicated hardware accelerator to accelerate machie learig applicatios High performace, Low Power Deploed i global dataceters Where are these materials beig used i our everda lives? ENGG23 - H. So 67 ENGG23 - H. So 68

18 Summar Simplifig logic circuits Miimizatio b Boolea algebra Miimizatio b Karaugh maps Adders I sequetial circuits, output depeds o both the curret iput ad the state of the circuit Output of combiatioal circuit depeds ol o the curret iput D-Flip-Flops are the most commo state elemet to hold states i a circuit The output value of ad edge-triggered DFF ol chages at positive clock edge. A multi-bit DFF is sometimes referred as a register ENGG23 - H. So 69