Structure of a Typical Digital System Data Inputs

Transcription

1 ecture RT Desig Methodology Trasitio from the & Iterface to a Correspodig Block Diagram Structure of a Typical Digital System Data Iputs Datapath (Executio Uit) Data Outputs Cotrol Sigals Status Sigals Cotrol & Status Iputs Cotroller (Cotrol Uit) Cotrol & Status Outputs Hardware Desig with RT VHD Datapath Block diagram VHD code Iterface ASM chart Cotroller VHD code 3 Steps of the Desig Process 1. Text descriptio. Iterface Block diagram of the Datapath 5. Iterface divided ito the Datapath ad Cotroller 6. ASM chart of the Cotroller 7. RT VHD code of the Datapath, Cotroller, ad Top-evel Uit 8. Testbech for the Datapath, Cotroller, ad Top-evel Uit 9. Fuctioal simulatio ad debuggig 1. Sythesis ad post-sythesis simulatio 11. Implemetatio ad timig simulatio 1. Experimetal testig usig FPGA board 4 Steps of the Desig Process Itroduced i Class Today 1. Text descriptio. Iterface Block diagram of the Datapath 5. Iterface divided ito the Datapath ad Cotroller 6. ASM chart of the Cotroller 7. RT VHD code of the Datapath, Cotroller, ad Toplevel Uit 8. Testbech for the Datapath, Cotroller, ad Top-evel Uit 9. Fuctioal simulatio ad debuggig 1. Sythesis ad post-sythesis simulatio 11. Implemetatio ad timig simulatio 1. Experimetal testig usig FPGA board 5 Class Exercise 1 STATISTICS 6 1

2 Circuit Iterface o_1 = o_ = o_3 = sum = for i= to k-1 do sum = sum + di if di > o_1 the o_3 = o_ o_ = o_1 o_1 = di elseif (di > o_) the o_3 = o_ o_ = di elseif (di > o_3) the o_3 = di ed if ed for avr = sum / k 7 di go Statistics doe dout dout_mode 8 Iterface Table Port Width Meaig 1 System clock. 1 System. di Iput Data. go 1 Cotrol sigal idicatig that the first iput is ready. Active for oe clock cycle. doe 1 Sigal set to high after the output is ready. dout Output depedet o the dout_mode iput. dout_mode Cotrol sigal determiig value available at the output. : avr, 1: o_1, 1: o_, 11: o_3. STATISTICS: Solutios 9 1 di Alterative Couters +m esum e +m sum +m +m rst e1 e e rst 1 s e o_1 rst o_ 1 s3 A A>B B A A>B B gt1 gt ec e rst m i m >> m avr o_1 o_ o_ e3 dout_mode e rst o_3 A A>B B gt3 == k-1 zi dout Block diagram of the Datapath 1

3 Iterface with the divisio ito the Datapath ad Cotroller di dout_mode go Datapath gt1 gt gt3 zi e1 e e3 Cotroller Class Exercise CIPHER esum ec s s3 dout doe 13 (Rivest Cipher 6) - symmetric key block cipher Security Margi IST Report: Security Desigers: Ro Rivest, Matt Robshaw, Ray Sidey, ad Yiqu isa Yi Oe of five fialists of the cotest for the Advaced Ecryptio Stadard (AES) Cadidate algorithm i the followig other cotests: ESSIE for Europea stadards (-3) CRYPTREC for Japaese stadards (-3) 15 High Adequate Serpet Rijdael Simple MARS Twofish Complex Complexity high medium low IST Report: Software Efficiecy Ecryptio ad Decryptio Speed 3-bit processors Rijdael Mars Twofish Serpet 64-bit processors Rijdael Twofish Mars Serpet DSPs Rijdael Twofish Mars Serpet Efficiecy i hardware: FPGA Virtex 1: Speed Throughput [Mbit/s] Serpet I George Maso Uiversity Uiversity of Souther Califoria Worcester Polytechic Istitute 149 Rijdael Twofish Serpet Mars I

4 Split iput I ito four words, I3, I, I1, I, of the size of w bits each A = I3; B = I; C = I1; D=I B = B + S[] D = D + S[1] for i = 1 to r do { T = (B*(B + 1)) <<< k U = (D*(D + 1)) <<< k A = ((A T) <<< U) + S[i] C = ((C U) <<< T) + S[i + 1] (A, B, C, D) = (B, C, D, A) } A = A + S[r + ] C = C + S[r + 3] O = (A, B, C, D) otatio w: word size, e.g., w=3 (costat) k: log (w) (costat) A, B, C, D, U, T: w-bit variables I3, I, I1, I: Four w-bit words of the iput I r: umber of rouds (costat) O: output of the size of 4w bits S[j] : r+4 roud keys stored i two RAMs. Each key is a w-bit word. The first RAM stores values of S[j=i], i.e., oly roud keys with eve idices. The secod memory stores values of S[j=i+1], i.e., oly roud keys with odd idices. 19 Operatios Modular Arithmetic : XOR + : additio modulo w : subtractio modulo w * : multiplicatio modulo w X <<< Y : rotatio of X to the left by the umber of positios give i Y X >>> Y : rotatio of X to the right by the umber of positios give i Y (A, B, C, D) : Cocateatio of A, B, C, ad D mod 1 = 3 Circuit Iterface Iterface Table I write_i 4w CIPHER 4w O DOE Sj w Write_Sj j m ote: m is a size of idex j. It is a miimum iteger, such that m -1 ³ r

5 Protocol (1) A exteral circuit first loads all roud keys S[], S[1], S[],, S[r+], [r+3] to the two iteral memories of the CIPHER uit. The first memory stores values of S[j=i], i.e., oly roud keys with eve idices. The secod memory stores values of S[j=i+1], i.e. oly roud keys with odd idices. Protocol () Whe the ecryptio is completed, sigal DOE becomes active, ad the output O chages to the ew value of the ciphertext. The output O keeps the last value of the ciphertext at the output, util the ext ecryptio is completed. Before the first ecryptio is completed, this output should be equal to zero. oadig roud keys is performed usig iputs: Sj, j, write_sj,. The, the exteral circuits, loads a iput block I to the CIPHER uit, usig iputs: I, write_i,. After the iput block I is loaded to the CIPHER uit, the ecryptio starts automatically. 5 6 Assumptios r+4 clock cycles are used to load roud keys to iteral RAMs oe roud of the mai for loop of the pseudocode executes i oe clock cycle you ca access oly oe positio of each iteral memory of roud keys per clock cycle CIPHER: Buildig Blocks As a result, the ecryptio of a sigle iput block I should last r+ clock cycles. 7 8 Additio mod w XOR Multiplicatio mod w 9 3 5

6 Variable Rotatio X<<<Y CIPHER Solutios 31 Datapath Iitializatio & Mai oop 3 Datapath PostProcessig & oop Couter 33 Memories of Roud Keys Cotets 34 Datapath Memories of Roud Keys

7 Iterface with the Divisio ito the Datapath ad Cotroller Timig Aalysis Key Setup & Ecryptio otatio: T CK clock period i s M umber of ecrypted message blocks I T KeySetup[cycles] = r+4 T KeySetup[s] = (r+4) T CK T Ecryptio( M)[cycles] = (r+) M T Ecryptio( M)[s] = (r+) M T CK Timig Aalysis - Throughput otatio: T CK clock period i s M umber of ecrypted message blocks I w word size Thr Ecryptio( M)[Gbit/s] = (r+) M T CK 4 w 4 w M = (r+) TCK r & w costats, determied by the security aalysis of the cipher For the security equivalet to AES-18, r= & w=3 Timig Aalysis Critical Path T CK-mi = d R + d logic-max + t setup Critical Path a path from a output of a register to a iput of a register with the maximum value of the delay (deoted as d logic-max) d R delay of a register t setup setup time of a register T CK depedet o w, retured by the FPGA tools based o the static timig aalysis of the critical path 39 4 Setup & Hold Time of a Register Datapath Critical Path tsetup dr Setup time - the amout of time the data at the sychroous iput must be stable before the ext active edge of clock Hold time - the amout of time the data at the sychroous iput must be stable after the last active edge of clock 41 dlogic-max Critical Path marked i red 4 7

8 Sortig - Required Iterface Class Exercise 3 SORTIG Reset DataI RAdd WrIit Sort DataOut Doe S (=iitializatio 1=computatios) Rd Sortig - Required Iterface Simulatio results for the sort operatio (1) oadig memory ad startig sortig Simulatio results for the sort operatio () Completig sortig ad readig out memory Address 1 3 Before sortig Sortig - Example Durig Sortig i= i= i= i=1 i=1 i= j=1 j= j=3 j= j=3 j=3 After sortig eged: positio of memory idexed by i M i positio of memory idexed by j M j

9 [load iput data] wait for s=1 for i = to do A = Mi ; for j = i + 1 to 3 do B = M j ; if B < A the Mi = B ; Mj = A ; A = Mi ; edif ; edfor; edfor; Doe wait for s= [read output data] go to the begiig FOR k = 4 FOR ay k [load iput data] wait for s=1 for i = to k - do A = Mi ; for j = i + 1 to k 1 do B = Mj ; if B < A the Mi = B ; Mj = A ; A = Mi ; edif ; edfor; edfor; Doe wait for s= [read output data] go to the begiig 49 wait for s=1 for i= to k- do A = M i for j=i+1 to k-1 do B = M j if A > B the M i = B M j = A A = M i ed if ed for ed for Doe wait for s= go to the begiig 5 SORTIG Solutios ABMux WrIit Wr We WE CK 1 s DI DOUT Addr ADDR EA EB E CK RST Reset E CK RST Reset 1 Bout A A>B DataI Di Mij B s 1 RAdd Csel 1 i D Ei E CK Rd i j DataOut RST Reset j Ej D E CK = k- = k-1 zi +1 zj RST Reset AgtB Block diagram of the Datapath 51 Iterface divided ito the Datapath ad Cotroller DataI RAddr WrIit Rd Reset s AgtB zi Datapath zj Wr i Cotroller Ei j Ej EA EB Bout Csel DataOut Doe 53 9