Basic Computer Organization and Design Part 3/3

Transcription

1 Basic Computer Organization and Design Part 3/3 Adapted by Dr. Adel Ammar Computer Organization

2 Interrupt Initiated Input/Output Open communication only when some data has to be passed --> interrupt. The I/O interface, instead of the CPU, monitors the I/O device. When the interface founds that the I/O device is ready for data transfer, it generates an interrupt request to the CPU Upon detecting an interrupt, the CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing. IEN (Interrupt-enable flip-flop) can be set and cleared by instructions when cleared, the computer cannot be interrupted Computer Organization 2

3 Flowchart for Interrupt Cycle R = Interrupt F/F Instruction cycle =0 R =1 Interrupt cycle Fetch and decode instructions Store return address in location 0 M[0] PC Execute instructions R 1 =1 =1 IEN =1 FGI =0 FGO =0 =0 Branch to location 1 PC 1 IEN 0 R 0 v The interrupt cycle is a HW implementation of a branch and save return address operation. v At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1. v At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine v The instruction that returns the control to the original program is "indirect BUN 0" Computer Organization 3

4 Register Transfer Microoperations in Interrupt Cycle Memory Before interrupt After interrupt cycle BUN PC = BUN PC = Main Program I/O Program Main Program I/O Program 1 BUN 0 Register Transfer Statements for Interrupt Cycle R F/F 1 if IEN (FGI + FGO)T0 T1 T2 T0 T1 T2 (IEN)(FGI + FGO): R 1 1 BUN 0 The fetch and decode phases of the instruction cycle must be modified Replace T0, T1, T2 with R'T0, R'T1, R'T2 The interrupt cycle : RT0: AR 0, TR PC RT1: M[AR] TR, PC 0 RT2: PC PC+1 Computer Organization 4

5 Complete Computer Description Flowchart of Operations start SC 0, IEN 0, R 0 =0(Instruction Cycle) R T 0 AR PC R T 1 IR M[AR], PC PC + 1 R =1(Interrupt Cycle) RT 0 AR 0, TR PC M[AR] TR, PC 0 RT 1 R T 2 AR IR(0~11), I IR(15) D 0...D 7 Decode IR(12 ~ 14) PC PC + 1, IEN 0 R 0, SC 0 RT 2 =1(Register or I/O) D 7 =0(Memory Ref) =1 (I/O) =0 (Register) =1(Indir) =0(Dir) I I D 7 IT 3 D 7 I T 3 D 7 IT3 D 7 I T3 Execute I/O Instruction Execute RR Instruction AR <- M[AR] Idle Execute MR D 7 T4 Instruction Computer Organization 5

6 Further Questions on Interrupt v How can the CPU recognize the device requesting an interrupt? v Since different devices are likely to require different interrupt service routines, how can the CPU obtain the starting address of the appropriate routine in each case? v Should any device be allowed to interrupt the CPU while another interrupt is being serviced? v How can the situation be handled when two or more interrupt requests occur simultaneously? Computer Organization 6

7 Fetch Decode Complete Computer Description Microoperations R T 0 : R T 1 : R T 2 : Indirect D 7 IT 3 : Interrupt T 0 T 1 T 2 (IEN)(FGI + FGO): RT 0 : RT 1 : RT 2 : Memory-Reference AND D 0 T 4 : D 0 T 5 : ADD D 1 T 4 : D 1 T 5 : LDA D 2 T 4 : D 2 T 5 : STA D 3 T 4 : BUN D 4 T 4 : BSA D 5 T 4 : D 5 T 5 : ISZ D 6 T 4 : D 6 T 5 : D 6 T 6 : AR PC IR M[AR], PC PC + 1 D0,..., D7 Decode IR(12 ~ 14), AR IR(0 ~ 11), I IR(15) AR M[AR] R 1 AR 0, TR PC M[AR] TR, PC 0 PC PC + 1, IEN 0, R 0, SC 0 DR M[AR] AC AC DR, SC 0 DR M[AR] AC AC + DR, E C out, SC 0 DR M[AR] AC DR, SC 0 M[AR] AC, SC 0 PC AR, SC 0 M[AR] PC, AR AR + 1 PC AR, SC 0 DR M[AR] DR DR + 1 M[AR] DR, if(dr=0) then (PC PC + 1), SC 0 Computer Organization 7

8 Complete Computer Description Microoperations Register-Reference CLA CLE CMA CME CIR CIL INC SPA SNA SZA SZE HLT Input-Output INP OUT SKI SKO ION IOF D 7 I T 3 = r IR(i) = B i r: rb 11 : rb 10 : rb 9 : rb 8 : rb 7 : rb 6 : rb 5 : rb 4 : rb 3 : rb 2 : rb 1 : rb 0 : D 7 IT 3 = p IR(i) = B i p: pb 11 : pb 10 : pb 9 : pb 8 : pb 7 : pb 6 : (Common to all register-reference instr) (i = 0,1,2,..., 11) SC 0 AC 0 E 0 AC AC E E AC shr AC, AC(15) E, E AC(0) AC shl AC, AC(0) E, E AC(15) AC AC + 1 If(AC(15) =0) then (PC PC + 1) If(AC(15) =1) then (PC PC + 1) If(AC = 0) then (PC PC + 1) If(E=0) then (PC PC + 1) S 0 (Common to all input-output instructions) (i = 6,7,8,9,10,11) SC 0 AC(0-7) INPR, FGI 0 OUTR AC(0-7), FGO 0 If(FGI=1) then (PC PC + 1) If(FGO=1) then (PC PC + 1) IEN 1 IEN 0 Computer Organization 8

9 Design of Basic Computer v Hardware Components of Basic Computer v A memory unit: 4096 x 16. v Registers: ð AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC v Flip-Flops (Status): ð I, S, E, R, IEN, FGI, and FGO v Decoders: ð a 3x8 Opcode decoder ð a 4x16 timing decoder v Common bus: 16 bits v Control logic gates: v Adder and Logic circuit: Connected to AC v Control Logic Gates - Input Controls of the nine registers - Read and Write Controls of memory - Set, Clear, or Complement Controls of the flip-flops - S2, S1, S0 Controls to select a register for the bus - AC, and Adder and Logic circuit Computer Organization 9

10 Control of Registers and Memory v Address Register: AR ð Scan all of the register transfer statements that change the content of AR: R T 0 : AR PC LD(AR) R T 2 : AR IR(0-11) LD(AR) D 7 IT 3 : AR M[AR] LD(AR) RT 0 : AR 0 CLR(AR) D 5 T 4 : AR AR + 1 INR(AR) LD(AR) = R'T 0 + R'T 2 + D' 7 IT 3 CLR(AR) = RT 0 T 2 R T 0 D' 7 I T 3 INR(AR) = D 5 T 4 From bus 12 LD AR INR CLR 12 To bus Clock D 5 T 4 Computer Organization 10

11 Control of Flags v IEN: Interrupt Enable Flag ð pb7: IEN 1 (I/O Instruction) ð pb6: IEN 0 (I/O Instruction) ð RT2: IEN 0 (Interrupt) ð p = D7IT3 (Input/Output Instruction) D 7 I T 3 p B 7 J Q IEN B 6 K R T 2 Computer Organization 11

12 Control of Common Bus x1 x2 x3 x4 x5 x6 x7 Encoder S 2 S 1 S 0 Multiplexer bus select inputs x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 selected register none AR PC DR AC IR TR Memory For AR D 4 T 4 : PC AR D 5 T 5 : PC AR x1 = D 4 T 4 + D 5 T 5 Computer Organization 12

13 Design of Accumulator Logic Circuits associated with AC 16 From DR From INPR 16 8 Adder and logic circuit 16 AC 16 To bus LD INR CLR Clock All the statements that change AC Control gates D 0 T 5 : AC AC DR AND with DR D 1 T 5 : AC AC + DR Add with DR D 2 T 5 : AC DR Transfer from DR pb 11 : AC(0-7) INPR Transfer from INPR rb 9 : AC AC Complement rb 7 : AC shr AC, AC(15) E Shift right rb 6 : AC shl AC, AC(0) E Shift left rb 11 : AC 0 Clear rb 5 : AC AC + 1 Increment Computer Organization 13

14 Control of AC Register Gate structures for controlling the LD, INR, and CLR of AC From Adder and Logic 16 AC 16 To bus D 0 T 5 D 1 AND ADD LD INR CLR Clock D 2 T 5 p B 11 r B 9 B 7 B 6 B 5 B 11 DR INPR COM SHR SHL INC CLR Computer Organization 14

15 ALU (Adder and Logic Circuit) One stage of Adder and Logic circuit DR(i) AC(i) AND FA C C i i+1 ADD DR I i LD J Q AC(i) From INPR bit(i) INPR COM K SHR AC(i+1) SHL AC(i-1) Computer Organization 15

16 Announcements v Readings ð Chapter 5 of the textbook: Computer System Architecture, M. Mano ð 5-3, 5-4, 5-6, 5-9, 5-10, 5-11, 5-12, 5-15, 5-16, 5-17, 5-18 Computer Organization 16