Chapter 9. Counters and Shift Registers. Counters and Shift Registers

Size: px

Start display at page:

Download "Chapter 9. Counters and Shift Registers. Counters and Shift Registers"

Lynne Arnold
5 years ago
Views:

1 Chapter 9 Counters and Shift Registers Counters and Shift Registers Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations. Shift Register: A Sequential Circuit that moves stored data bits in a specific direction. Used in Serial Data Transfers, SIPO/PISO Conversions, Arithmetic, and Delays. SIPO: Serial In, Parallel Out PISO: Parallel In, Serial Out 2 1

2 Counter Terminology 1 A Counter is a digital circuit whose outputs progress in a predictable repeating pattern. It advances on state for each clock pulse. State Diagram: A graphical diagram showing the progression of states in a sequential circuit such as a counter. 3 Counter Terminology 2 Count Sequence: The specific series of output states through which a counter progresses. Modulus: The number of states through which a counter sequences before repeating (mod-n). Counter directions: UP - count low to high (LSB to MSB). DOWN - count high to low (MSB to LSB) 原講義將 Up and Down 的定義誤植 / 錯置 4 2

3 Counter Modulus Modulus of a counter is the number of states through which a counter progresses. A Mod-12 UP Counter counts 12 states from 0000 (0010) to 1011 (1101). The process then repeats.( 也可由 2 上數到 13) A Mod-12 DOWN counter counts from 1011 (1101) to 0000 (0010), then repeats.( 也可由 13 下數到 2) 5 State Diagram A diagram that shows the progressive states of a sequential circuit. The progression from one state to the next state is shown by an arrow. ( ). Each state progression is caused by a pulse on the clock to the sequential circuit. 6 3

4 MOD 12 Counter State Diagram With each clock pulse the counter progresses by one state from its present position on the state diagram to the next state in the sequence. This close system of counting and adding is known as modulo arithmetic. 7 MOD 12 Counter State Diagram 8 4

5 Truncated Counters 1 An n-bit counter that counts the maximum modulus (2 n ) is called a fullsequence counter such as Mod 2, Mod 4, Mod 8, etc. An n-bit counter whose modulus is less than the maximum possible is called a truncated sequence counter, such as mod 3 (n = 2), mod 12 (n = 4). 9 Truncated Counters 2 A 4-bit mod 12 UP counter that counts from 0000 to 1011 is an example of a truncated counter. A 4-bit mod 16 UP counter that counts up from 0000 to 1111 is an example of a full-sequence counter. 10 5

6 Truncated Counters 3 Mod 16 Up counter, a full-sequence counter 11 Counter Timing Diagrams 1 Shows the timing relationships between the input clock and the outputs Q 3, Q 2, Q 1, Q n of a counter. For a 4-bit mod 16 counter, the output Q 0 changes for every clock pulse, Q 1 changes on every two clock pulses, Q 2 on four, and Q 3 on 8 clocks. 12 6

7 Counter Timing Diagrams 2 The outputs (Q 0 Q 3 ) of the counter can be used as frequency dividers with Q 0 = clock 2, Q 1 = clock 4, Q 2 = clock 8, and Q 3 = clock 16. The frequency is based on T of the output, not a transition on the output. The same is true for a mod 12, except Q 3 = clock Counter Timing Diagrams 3 Mod 16 timing diagram 14 7

8 Counter Timing Diagrams 4 Mod 12 timing diagram Note: Q 2 and Q 3 have the same frequency f c /12, but are out of phase with one another 15 Synchronous Counters A counter whose flip-flops are all clocked by the same source and change state in synchronization. The memory section keeps track of( 紀錄 ) the present state. The control section directs the counter to the next state using command and status lines. 16 8

9 某些電路不需輸入, 例如 Counter, 不需輸入就可以自己 Count! Synchronous Counters 整體電路輸出不一定要是正反器的輸出, 可以是 Qs 的函數 Status lines 就是 Flip Flop 的 Output Q Command lines 就是 Flip Flop 的 Input! 17 Analysis of Synchronous Counters 1 Set equations for the (JK, D, T) inputs in terms of the Q outputs for the counter.( 亦即將 Flip- Flop 的 Q 當作 JK, D, T 等之輸入變數 ) Set up a table similar to the one in Table 9.5( See P.21 of the slide) and place the first initial state in the present state column (usually all 000). Use the initial state to fill in the Inputs, i.e, Js and Ks, that will cause this state on a clock pulse. An approach to determine the sequence of a synchronous counter of unknown modulus 18 9

10 Analysis of Synchronous Counters 2 Determine the result on each FF in the counter and place this in the next state. Enter the next state on the present state line 2 and repeat the process until you cycle back to the first initial state. An approach to determine the sequence of a synchronous counter of unknown modulus 19 Analysis of Synchronous Counters 3 J K 0 = Q = 1 2 J 1 K = Q 0 = Q J = Q Q An approach to determine the sequence of a synchronous counter of unknown modulus 20 K 2 1 =

11 State Table For Figure 9.11 in P.21 Present State Synchronous Inputs J 0 K Next State Q2Q 1Q J K J K Q2Q 1Q ( R ) 00 (NC) 11 ( T ) ( R ) 11 (T) 11 ( T ) ( R ) 00 (NC) 11 ( T ) ( T ) 11 (T) 11 ( T ) ( R ) 00 (NC) 01 ( R ) 000 An approach to determine the sequence of a synchronous counter of unknown modulus 21 Basic Design Approach 1 Draw a state diagram showing state changes and inputs and outputs. Create a present/next state table. List present states in binary order and next states based on the state diagram

12 Basic Design Approach 2 Use FF Excitation Tables( 激勵表 )to determine FF (JK, D, T) inputs for each present next state transition. Specify inputs equations for each input and simplify using Boolean reductions. 23 Basic Design Approach 3 The previous two slides describe the process for designing counters by deriving and simplifying Boolean equations for a counter (classical approach). VHDL design for counters is done more easily and is not as time consuming

13 VHDL Process Statements Sequential counters use a process statement to control transitions to the next count state. A VHDL Attribute is used with an identifier (signal) to define clock edges. Clock uses an attribute called EVENT such as (clk EVENT AND clk= 1) to define a rising edge clock event. 25 VHDL UP Counter -- simple_int_counter.vhd -- 8-bit synchronous counter with asynchronous clear. -- Uses INTEGER type for counter output. LIBRARY ieee; USE ieee.std_logic_1164.all; 26 13

14 VHDL UP Counter Entity ENTITY simple_int_counter IS PORT( clock : IN STD_LOGIC; reset : IN_STD_LOGIC; q : OUT INTEGER RANGE 0 TO 255); END simple_int_counter; 27 VHDL UP Counter Architecture 1 ARCHITECTURE counter OF simple_int_counter IS BEGIN PROCESS (clock, reset) VARIABLE count : INTEGER RANGE 0 to 255; BEGIN IF (reset = 0 ) THEN COUNT : = 0; 28 14

15 VHDL UP Counter Architecture 2 ELSE IF (clock EVENT AND clock = 1 ) THEN count := count +1; END IF; END IF; q <= count; END PROCESS; END counter; 29 VHDL UP Counter Summary PROCESS statement monitors the two inputs clock and reset, which controls the state of the counter. A variable count holds the present value of the counter. The IF statement evaluates the clock and reset inputs to determine whether the counter should increment or clear

16 LPM Counters 1 The Altera LPM (Library of Parameterized Modules) counter can be used to create counter designs in VHDL. This is a structured design approach that uses the LPM-counter as a component in a hierarchy. The LPM counter is instantiated in the structured design. 31 LPM Counters 2 The basic parameters of the LPM counter, such as width, are defined with a generic map. The port map is used to connect LPM counter I/O to the actual VHDL design entity

17 VHDL LPM Library Declaration The Altera LPM Library must be added to the usual STD_LOGIC after the ieee library has been declared LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; 33 VHDL LPM Entity Entity for an 8-bit mod 256 counter. LPM requires the use of STD_LOGIC data types. ENTITY simple_lpm_counter IS PORT( clk, clear : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (7 downto 0)); END simple_lpm_counter; 34 17

18 VHDL LPM Architecture ARCHITECTURE count OF simple_lpm_counter IS SIGNAL clrn : STD_LOGIC;--internal signal for active low clr. BEGIN -- Instantiate 8-bit counter. count : lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP (clock => clk, aclr => clrn,--intrnal clear mapped to async. clr. q => q_out (7 downto 0 )); clrn <= not clear;--input port inverted mapped to internal clr. END count; 35 Entering Simple LPM Counters in Quartus II Use either the MegaWizard Plug in Manager or manually enter the LPM component. Refer to Chapter 9, Entering Simple LPM Counters with the Quartus II Block Editor

19 Entering Simple LPM Counters in Quartus II 37 Entering Simple LPM Counters in Quartus II 38 19

20 LPM Counter Features 1 Parallel Load: A function (syn/asyn) that allows loading of a binary value into the counter FF. Clear: asynchronous or synchronous reset. Preset: A set (syn. Or asyn.). 39 LPM Counter Features 2 Counter Enable: A control function that allows a counter to count the sequences or disable the count. Bi-Directional: A control line to switch the counter from a count up to a count down

21 LPM Counter Features 3 There are other features for LPM counters that are given in the Altera Reference Data Sheets. The same holds true for other LPM functions, such as arithmetic and memory Bit Parallel Load Counter 1 A preset counter (parallel load) has an additional input (load) that can be synchronous or asynchronous and four parallel data inputs. The load pulse selects whether the synchronous counter inputs are generated by count logic or parallel load data.( 決定資料係由 Parallel In 或是由 Counter 自行產生 ) 42 21

22 4-Bit Parallel Load Counter 2 An asynchronous load counter uses an asynchronous clear or preset to force the counter to a known state (usually 0000 or 1111) Bit Parallel Load Counter

23 4-Bit Parallel Load Counter 4 Counter/Load Selection 當 Load 為 1 時載入 Parallel In 之資料 45 4-Bit Parallel Load Counter 5 Fig. Counter element with synchronous load and asynchronous clear T Flip-Flop 46 23

24 4-Bit Parallel Load Counter 6 Fig. 4-bit counter with synchronous load and asynchronous reset 47 Count Enable Logic As shown in Figure 9.46, adding another AND gate to each FF input inhibits the count function(fig is shown in next page; See next page for details). This has the effect of inhibiting the clock to the counter (a clock pulse has no effect). Outputs remain at the last state until the counter is enabled again

25 49 Bi-Directional Counter Adds a direction Input (DIR) to the counter and the control logic for up or down counting. Basic counter element is shown in Figure The control logic selects the up or down count logic depending on the state of DIR

26 Terminal Count Decoding 1 Uses a combinational decoder to detect when the last state of a counter is reached (terminal count). Determines a maximum count out for an UP counter and a minimum for a DOWN counter. 51 Terminal Count Decoding

27 Terminal Count Decoding 3 RCO: Ripple Carry Out Fig. 4-bit Bidirectional Counter with Terminal Count Detection 53 Terminal Count Decoding 2 The terminal count decoder generates a RCO (Ripple Carry Out, or Ripple Clock Out) when the terminal count is reached (a Low pulse for 1/2 clock period). Generate positive edge of RCO at the end of the counter, for a counter that has a positive edge-triggered clock (See next page for details)

28 Terminal Count Decoding 3 55 VHDL Counter (8-Bit) 1 -- Pre-settable_8bit_counter_sync_load -- 8-bit pre-settable counter with synchronous -- clear and load and terminal count decoding -- using STD_LOGIC types LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; 56 28

29 VHDL Counter (8-Bit) 2 ENTITY presettable_8bit_counter_sync_load IS PORT( clk, count_ena : IN STD_LOGIC; clear, load, direction : IN STD_LOGIC; p : IN STD_LOGIC_VECTOR (7 downto 0); max_min :OUT STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR (7 downto 0)); END presettable_8bit_counter_sync_load; 57 VHDL Counter (8-Bit) 3 ARCHITECTURE a OF presettable_8bit_counter_sync_load IS SIGNAL terminal_count : STD_LOGIC_VECTOR (8 downto 0); BEGIN PROCESS (clk) -- Since all functions are synchronous only clk is on -- the sensitivity list. BEGIN IF (CLK EVENT AND clk = 1 ) THEN IF (clear = 0 ) THEN -- Synchronous clear. q <= (others => 0 ); ELSIF (load = 1 ) THEN Synchronous load. q <= p; 58 29

30 VHDL Counter (8-Bit) 3 ELSIF (count_ena = 1 and direction = 0 ) THEN q <= q 1; ELSIF (count_ena = 1 and direction = 1 ) THEN q <= q+1; END IF; END IF; END PROCESS; 59 Terminal Count Code -- Terminal count decoder (combinational) Terminal_count <= direction & q; WITH terminal_count SELECT max_min <= 1 WHEN , 1 WHEN , 0 WHEN others; 60 30

31 8-Bit Counter Summary 1 After the PROCESS statement. q = 0 (if clear = 0). q = p (if clear = 0 and load = 1) Bit Counter Summary 2 q increments if there is a + ve clk edge, count_ena = 1, and direction = 1). q decrements if there is a + ve clk edge, count_ena = 1, and direction = 0). q remains the same if above conditions are not met

32 8-Bit Counter Summary 3 63 LPM Counter Functions LPM counters can be used as a simple 8-bit counter. The component lpm_counter has a number of other functions that can be implemented using specific ports and parameters. These functions are indicated on Table

33 LPM Counter VHDL Code 1 -- pre_lpm bit presettable counter with asynchronous clear and load, -- count enable, and a directional control port. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.lpm_components.all; 65 LPM Counter VHDL Code 2 ENTITY pre_lpm8 IS PORT( clk, count_ena : IN STD_LOGIC; clear, load, direction : IN STD_LOGIC; p : IN STD_LOGIC_VECTOR (7 downto 0); q_out : IN STD_LOGIC_VECTOR (7 downto 0)); END PRE_LPM8; 66 33

34 LPM Counter VHDL Code 3 ARCHITECTURE a OF pre_lpm8 IS BEGIN counter 1: lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP (clock => clk, updown => direction, cnt_en => count_ena, data => p, aload => load, aclr => clear, q => q_out; END a; 67 Shift Register Terminology 1 Shift Register: A synchronous sequential circuit that will store and move n-bit data either serially or in parallel in a n-bit Register (FF). Left Shift: A movement of data from right to left in the shift register (toward the MSB). One bit shift per clock pulse

35 Shift Register Terminology 2 Right Shift: A movement of data from left to right in the shift register (toward the LSB). One bit shift per clock pulse. Rotation: Serial shifting (right or left) with the output of the last FF connected to the input of the first. Results in continuous circulation of SR data. 69 Shift Register Terminology

36 Shift Register Terminology 2 71 Serial Shift Register (SR) A 4-Bit Left Shift Register. D IN is shifted into the LSB FF and shifted toward the MSB. Q 3 D 3 Q 2 D 2 Q 1 D 1 Q 0 D 0 D IN MSB < < < LSB < CLK 72 36

37 SS Left Shift 1 Q 3 D 3 Q 2 D 2 Q 1 D 1 Q 0 D 0 D IN MSB < < < LSB < CLK 73 SS Left Shift 2 Q 3 D 3 Q 2 D 2 Q 1 D 1 Q 0 D 0 D IN MSB < < < LSB < CLK 74 37

38 SS Left Shift 3 Q 3 D 3 Q 2 D 2 Q 1 D 1 Q 0 D 0 D IN MSB < < < LSB < CLK 75 SS Left Shift 4 Q 3 D 3 Q 2 D 2 Q 1 D 1 Q 0 D 0 D IN MSB < < < LSB < CLK 76 38

39 Bi-Directional Shift Register 1 Uses a control input signal called direction to change circuit function from shift right to shift left. 4-bit bi-directional SR is shown in Figure Bi-Directional Shift Register 2 When DIR = 0, the path of Left_Shift_In is selected. Q Q Q Q0 When DIR = 1, it selects the Right Shift In Path. Q Q Q Q

40 SR with Parallel Load Similar to a Parallel Load Counter, the Shift Register is shown in Figure Uses a 2-to-1 Mux (AND/OR) to control inputs to the FF in the SR. The input choice is from the previous FF Output or the Parallel Input. When Load = 1, Parallel Data is loaded in on the next clock pulse. 79 Universal SR Combines the basic functions of a Parallel Load SR with a Bi-Directional SR. Uses Two Control Inputs (S 1,S 0 ) to select the function as shown in Figure

41 Universal SR 81 Universal SR Truth Table (S 1 /S 0 ) S 1 S 0 Function D 3 D 2 D 1 D Hold Q 3 Q 2 Q 1 Q Shif t Right Left RSI * Q 3 Q 2 Q Shif t Left Right Q 2 Q 1 Q 0 LSI ** 1 1 Load P 3 P 2 P 1 P 0 * RSI = Right-Shif t Input / ** LSI = Left-Shif t Input 講義錯誤 ( 上下顛倒錯置 ) 82 41

42 Structured VHDL SR Structured VHDL Design: A VHDL design technique that connects predesigned components using internal signals. Would use DFF primitives to construct different types such as LSR and RSR. A DFF Primitive Port Map is (D, CLK, Q). 83 VHDL SR Entity 1 Basic Entity for a Structural RSR Design LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera; USE altera.maxplus2.all; -- Note: IEEE is before Altera declarations -- maxplus2 is for the primitive DFF Design 84 42

43 VHDL SR Entity 2 Port description of RSR Entity ENTITY srg4strc IS PORT( serial_in, clk : IN STD_LOGIC; qo :BUFFER STD_LOGIC_VECTOR(3 downto 0)); END srg4strc; -- The 4 Bit Register is given a type Buffer to allow -- Q0 Q3 to be used as Input or Output 85 VHDL SR Component Description Structural Architecture Component DFF ARCHITECTURE right_shift OF srg4strc IS COMPONENT DFF PORT ( d : IN STD_LOGIC; clk : IN STD_LOGIC; q : OUT STD_LOGIC); END COMPONENT; 86 43

44 BEGIN VHDL RSR Architecture flipflop3: dff PORT MAP (serial_in, clk, qo(3) ); dffs: FOR i IN 2 downto 0 GENERATE flip_flops_2_ to_0: dff PORT MAP (qo(i + 1), clk, qo(i) ); END GENERATE; END right_shift; 87 Structured Architecture Example Four dff components are mapped to create a RSR, serial_in is to Q 3 and shift is toward Q 0. Uses a FOR GENERATE Loop to create and map the four dff (Flip Flops)

45 DataFlow Design Approach DataFlow Design: A VHDL design approach that uses Boolean Equations to define relationships between inputs and outputs. The Entity is the same as the Structured approach, except the Altera Library is not needed. The register q is still declared as a Buffer. 89 VHDL Dataflow RSR 1 Basic Process Type of Architecture ARCHITECTURE right_shift OF srg4dflw IS SIGNAL d : STD_LOGIC_VECTOR (3 downto 0); BEGIN PROCESS(clk) BEGIN IF clk EVENT AND clk = 1 THEN q <= d; END IF; 90 45

46 VHDL DataFlow RSR 2 Continuation of RSR Architecture END PROCESS; d <= serial_in & q(3 downto 1); END right_shift; -- The actual data flows on d(0-3) outside the process. -- d(0-3) uses the Concatenate Operator (&) to create -- the four bit RSR. The process and d assignment are -- both executed concurrently. 91 Bi-Directional SR VHDL 1 Adds a basic direction control to the dataflow architecture given earlier. PROCESS(clk, clear) BEGIN IF clear = 0 THEN q <= (others => 0 ); -- asynchronous clear ELSEIF (clk EVENT and clk = 1 ) THEN 92 46

47 Bi-Directional SR VHDL 2 VHDL Architecture Continued CASE direction IS WHEN 0 => q <= q(2 downto 0) & lsi; -- Left Shift WHEN 1 => q <= rsi & q(3 downto 1); -- Right Shift WHEN OTHERS => Null; END CASE; END IF; END PROCESS; END bidirectional_shift; 93 Generic Width Shift Register Uses a VHDL Generic Clause in the Entity to specify a Width Variable. General form is GENERIC (Clause := Value) For a 4-Bit SR we use GENERIC. (Width : Positive := 4)

48 Generic VHDL File Entity Width set to 4 Bits ENTITY srt_bhv IS GENERIC (Width : POSITIVE := 4); PORT ( serial_in, clk :IN STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR (width-1 downto 0)); END srt_bhv; 95 Generic VHDL Architecture ARCHTITECTURE right_shift of srt_bhv IS BEGIN PROCESS(clk) BEGIN IF(clk EVENT AND clk = 1 ) THEN q(width-1 downto 0) <= serial_in & q(width-1 downto 1); END IF; END PROCESS; END right_shift; 96 48

49 LPM Shift Registers Allows the use of a Programmable LPM shift register called lpm_shiftreg. Has various required and optional parameters that are defined, such as LPM_WIDTH (Table 9.16 in text). Design approach is the same as for Counters using Structured VHDL. 97 LPM Entity Statement Remember to declare lpm Library for use ENTITY srg8_lpm2 IS PORT( clk serial_in :IN STD_LOGIC :IN STD_LOGIC; serial_out:out STD_LOGIC); END srg8_lpm2; 98 49

50 LPM SR Architecture ARCHITECTURE lpm_shift OF srg8_lpm2 IS BEGIN Shift_8 : lpm_shiftreg GENERIC MAP (LPM_WIDTH => 8, LPM_DIRECTION => RIGHT ) PORT MAP (clock => clk, shiftin => serial_in, shiftout => serial_out); END lpm_shift; 99 Shift Register Counters Two types: Ring and Johnson Ring Counter: A serial Shift Register with feedback from the output of the last FF to the input of the first FF. Counter sequences are based on a continuous rotation of data through the SR

51 Ring Counters 1 A basic Ring Counter (Figure 9.102) is constructed of D-FF with a Feedback Loop. Data is initially loaded into the SR by using either Resets or Presets. The counter can circulate a 0 or 1 by loading a 1000 or Ring Counters 2 The Modulus of a Ring Counter is defined as the maximum number of unique states. Modulus is dependent on the initial load value {1000, 0100, 0010, 0001} = Mod4 while {1010, 0101} = Mod2. Typically an N-FF Ring Counter has N-States, not 2 N like a binary counter

52 Ring Counters Circulating a 1 in a Ring Counter

53 Circulating a 0 in a Ring Counter 105 Johnson Counters 1 Johnson Counter: A serial shift register with the complemented feedback from the output of the last FF to the input of the first FF. Same as the Ring Counter sequences based on a continuous rotation of data through the SR

54 Johnson Counters 2 Same as a Ring (Figure 9.106) except that Q 0 (Complement) is fed back to D 3, not to Q 0. Adds a complement or twist to the data and is called a Twisted Ring Counter. Usually Initialized with 0000 by a Clear. 107 Johnson Counters 3 Typically has more states than a ring counter. Sequence of states = {0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001}. Maximum Modulus is 2n for a circuit with n flip-flops

Johnson Counters 4 109 States of a Johnson

55 Johnson Counters States of a Johnson Counters 輸出端應是由 /Q 迴授, 這裡所有的分解圖都錯了!

Chapter 9. Counters and Shift Registers. Counters and Shift Registers

Chapter 9. Counters and Shift Registers. Counters and Shift Registers Chapter 9 Counters and Shift Registers Counters and Shift Registers Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations. Shift