A Guide. Logic Library

Transcription

1 Logic A Guide To The Logic Library

2 SystemView by ELANIX Copyright , Eagleware Corporation All rights reserved. Eagleware-Elanix Corporation 3585 Engineering Drive, Suite 150 Norcross, GA USA Phone: +1 (678) , Fax: +1 (678) Support Web: Unpublished work. All rights reserved under the U.S. Copyright Act. Restricted Rights Apply. This document may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without the prior written consent of Eagleware Corporation. This document and the associated software are proprietary to Eagleware Corporation. SystemView by ELANIX, and ELANIX are registered trademarks of Eagleware Corporation. MetaSystem is a trademark of Eagleware Corporation. Windows is a trademark of Microsoft Corporation. Other trademarks or registered trademarks used in this document are the property of their respective owners. Document Number SVU LOGIC1002 Printed in the United States of America 2

3 Table of Contents LOGIC LIBRARY listed by ALPHABETICAL ABBREVIATION...5 LOGIC LIBRARY listed by GENERIC, 74xxx, CUSTOM...6 LOGIC LIBRARY listed by FUNCTION...7 Introduction...9 A Note on Simulating a Complete Logic System...10 Description of PROPAGATION DELAY Time Description of SETUP Time for CLOCK DRIVEN Logic Tokens...13 Description of TRUE and FALSE...15 Description of THRESHOLD...15 Description of INITIAL OUTPUT...15 Unused Inputs...16 Router Tokens Bi-Directional Data Flow and 3-State...16 Description of SET* Description of RESET*, MASTER RESET*(MR), and CLEAR*...17 Description of RISE TIME and FALL TIME...18 The Buffer Logic Token - Special Uses...18 LOGIC LIBRARY - Token Descriptions...19 Logic 3

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5 LOGIC LIBRARY listed by ALPHABETICAL ABBREVIATION ABBREV TYPE TOKEN NAME ADC... Custom... n-bit Analog to Digital Converter...67 AnaCmp... Custom... Comparator (Differential Analog Input,Q and Q* Output)...72 AND... Generic... AND gate...20 Buffer... Generic... Buffer (non-inverting)...25 Cntr Bit Synchronous Pre-settable Binary Counter...42 Cntr Stage Binary Counter...58 Cntr-U/D Bit Synchronous Binary Up/Down Counter with One Clock...51 DAC... Custom... n-bit Digital to Analog Converter...70 DigCmp Bit Identity Comparator (Equality Detector)...54 dmux-d Line to 8-Line Decoder/Demultiplexer...36 DPDT... Custom... 2-Channel Analog Multiplexer/Demux (DPDT Analog Switch)...66 FF-D D-Type Flip-Flop, positive-edge-triggered...28 FF-D Quad D-Type Flip-Flop...48 FF-JK* J-K* Type Flip-Flop, positive-edge-triggered...30 Int/Dig... Custom... n-bit Integer to Digital Converter...68 Invert Inverter...26 Latch-8T Bit Transparent Latch with Q Output...56 Latch-SR... Custom... Set/Reset Latch (Two NAND gates, cross-coupled)...63 Mux-D Input Digital Multiplexer...39 NAND... Generic... NAND gate...21 NOR... Generic... NOR gate...24 One-shot Retriggerable Monostable Multivibrator...32 OR... Generic... OR gate...22 Ph/Frq... MC Phase-Frequency Detector...60 PROM... Custom... Programmable Read Only Memory(8 x 8) (no 3-state)...73 Schmitt Schmitt Trigger Inverter...27 Schmitt Input Schmitt Trigger NAND...35 Shft-8in Bit Serial-in/Parallel-out Shift Register...45 SPDT... Custom... 2-Channel Analog Multiplexer (SPDT AnalogSwitch)...65 XOR... Generic... Exclusive OR gate...23 Logic 5

6 LOGIC LIBRARY listed by GENERIC, 74xxx, CUSTOM ABBREV TYPE TOKEN NAME AND... Generic...AND gate NAND... Generic...NAND gate OR... Generic...OR gate XOR... Generic...Exclusive OR gate NOR... Generic...NOR gate Buffer... Generic...Buffer (non-inverting) Invert Inverter Schmitt Schmitt Trigger Inverter FF-D D-Type Flip-Flop, positive-edge-triggered FF-JK* J-K* Type Flip-Flop, positive-edge-triggered One-shot Retriggerable Monostable Multivibrator Schmitt Input Schmitt Trigger NAND dmux-d Line to 8-Line Decoder/Demultiplexer Mux-D Input Digital Multiplexer Cntr Bit Synchronous Presettable Binary Counter Shft-8in Bit Serial-in/Parallel-out Shift Register FF-D Quad D-Type Flip-Flop Cntr-U/D Bit Synchronous Binary Up/Down Counter with One Clock DigCmp Bit Identity Comparator (Equality Detector) Latch-8T Bit Transparent Latch with Q Output Cntr Stage Binary Counter Ph/Frq... MC Phase-Frequency Detector Latch-SR... Custom...Set/Reset Latch (Two NAND gates, cross-coupled) SPDT... Custom...2-Channel Analog Multiplexer (SPDT AnalogSwitch) DPDT... Custom...2-Channel Analog Multiplexer/Demux (DPDT Analog Switch) ADC... Custom...n-Bit Analog to Digital Converter Int/Dig... Custom...n-BIT Integer to Digital Converter DAC... Custom...n-Bit Digital to Analog Converter AnaCmp... Custom...Comparator (Differential Analog Input,Q and Q* Output) PROM... Custom...Programmable Read Only Memory(8 x 8) (no 3-state)

7 LOGIC LIBRARY listed by FUNCTION ABBREV. TYPE TOKEN NAME AND / NAND gates AND Generic AND gate NAND Generic NAND gate Logic OR / NOR gates OR Generic OR gate NOR Generic NOR gate Exclusive-OR gates XOR Generic Exclusive OR gate Buffers / Inverters Buffer Generic Buffer (non-inverting) Invert 7404 Inverter Schmitt Triggers Schmtt Schmitt Trigger Inverter Schmtt Input Schmitt Trigger NAND Flip-Flops FF-D D-Type Flip-Flop, positive-edge-triggered FF-JK* J-K* Type Flip-Flop, positive-edge-triggered FF-D Quad D-Type Flip-Flop 7

8 LOGIC LIBRARY listed by FUNCTION NAME TYPE DESCRIPTION Latches Latch-SR Custom Set / Reset Latch (Two NAND gate, cross-coupled) Latch-8T Bit Transparent Latch with Q Output Shift Registers Shft-8in Bit Serial-in / Parallel-out Shift Register Counters Cntr Bit Synchronous Presettable Binary Counter Cntr-U/D Bit Synchronous Binary Up/Down Counter, with One Clock Cntr Stage Binary Counter Digital Multiplexers Mux-D Input Digital Multiplexer Digital Decoders / Digital Demultiplexers DMux-D line to 8-Line Decoder/Demultiplexer Switches / Analog Multiplexers / Analog Demultiplexers SPDT Custom 2-Channel Analog Multiplexer (SPDT Analog Switch) DPDT Custom 2-Channel Analog Multiplexer/Demux (DPDT Analog Switch) Arithmetic Circuits DigCmp Bit Identity Comparator (Equality Detector) Miscellaneous One-Shot Retriggerable Monostable Multivibrator Ph/Frq MC4044 Phase-Frequency Detector ADC Custom n-bit Analog to Digital Converter Int/Dig Custom n-bit Integer to Digital converter DAC Custom n-bit Digital to Analog Converter AnaCmp Custom Comparator (Differential Analog Input, Q and Q* Output) PROM Custom Programmable Read Only Memory (8 x 8) 8

9 Introduction Logic Congratulations on selecting the option. Besides the convenience of having many familiar logic functions available at the click of the mouse, you will find the system simulation time to be shorter than if the function were implemented as a MetaSystem. The Logic Library has three token classifications, listed as the following: The Generic tokens, have well-known functions such as the NAND gate. Generic tokens can have any number of inputs. Thus the NAND gate token can have 2, 3, etc. inputs. The 74xxx tokens, simulate a particular function that is available as a purchased part. In System View 74xxx refers to a specific logic function and not to a family such as TTL or CMOS. The Custom tokens, implement logic functions, that are not generally available as a single part, or logic functions, that have inputs and/or outputs with mixed-signals, such as Digital to Analog Converters (DAC), or analog switches. 9

10 A NOTE ON SIMULATING A COMPLETE LOGIC SYSTEM Refer to the SystemView example file sld_cor_1_tr_tx.suv that shows an example of a sliding correlator logic feedback system. In SystemView, the system sample time is indicated as dt. In the referenced feedback system, a one-dt sample delay is included, and is indicated as Z-1 within a box. The example shows one way of compensating for this sample delay, so that the digital output waveforms are lined up perfectly. This example file also illustrates the use of router tokens, located at the top of the token reservoir. Router tokens help the user define connection paths between tokens that have multiple input/output connections 10

11 Description of PROPAGATION DELAY Time The following refers to all tokens: 1. There are two ways to enter data into a logic token: (a) A direct connection, as with a NAND gate, that has a zero input delay, or (b) Using a clocked input, as described in the SETUP time. Logic 2. Once data has been entered into a gate or register, there is a propagation delay before the output begins to change state. In SystemView, the default delay is zero seconds, as shown in the timing waveforms of Figure The delay value is entered as a time in seconds. It should be an integer multiple of the system s sample time dt. If the propagation delay is not an integer multiple of the systems dt, the value will be rounded up or down and may produce a different delay than expected. 11

12 Figure 1. Propagation Delay Waveforms 12

13 Description of SETUP Time for Clock Driven Logic Tokens: Clock driven Logic Tokens are Flip-Flops, Shift Registers, Binary Counters, and Transparent Latches. Timing diagrams are shown in figures 2 through 7. There is no interpolation of the time samples. The circles on the waveforms indicate system time samples at each dt. Logic 1. There is no hold time required for the data. 2. The logic level present at a DATA input, is entered into the logic token during the LOW-to-HIGH transition of the clock pulse. Data at the input may be changed while the clock is HIGH or LOW, but only data with a setup time of at least one dt will be entered. An example of not meeting the set up time requirement is a DATA input that has been LOW for several clock pulses, and then goes HIGH at the same instant the clock goes HIGH. The flip-flop output will remain unchanged at a LOW state, and the same rules apply for LOW going data. 3. For a LOW-to-HIGH clock to enter a data 1 or 0 into a logic token, Tsetup = dt (seconds). 4. A HIGH-to-LOW clock pulse has no effect on a token. 5. The Transparent Latch (Latch-8T) has a LATCH ENABLE input that follows the SETUP time rules, but the LATCH ENABLE input also has an active LOW function. 13

14 SETUP time with ZERO SETUP time with one dt output delay: (Figures 2, 3, 4) output delay: (Figures 5, 6, 7) 14

15 Description of TRUE and FALSE The following applies to all Logic Tokens: 1. The signals used in digital systems are described in several different and sometimes confusing terms. A logic signal can be either ACTIVE (=TRUE) or NOT ACTIVE (NOT TRUE = FALSE). Logic 2. Digital circuits are defined for voltage levels that are either HIGH (H) (more positive) or LOW (L) (less positive or more negative). Either of these levels can be considered ACTIVE (TRUE). The opposite level is then NOT ACTIVE (FALSE). 3. MIL Std. 806B has established clear symbology: The HIGH level is considered ACTIVE unless a circle is located at the input or output, which indicates the opposite assignment (LOW = ACTIVE). A circle at an external input indicates that the specific input is ACTIVE LOW; and that it will produce the desired function, in conjunction with other inputs, if its voltage is below the THRESHOLD of the device. A circle at the output indicates that when the function designated is TRUE, the output is LOW. 4. TRUE and FALSE may be set to any positive or negative value, including zero. When the TRUE value is specified less than the FALSE value, the OUTPUT logic of the token is inverted - a NOT gate becomes a BUFFER, a NAND gate becomes an AND gate, etc. Description of THRESHOLD The threshold, for a logic input or clock, is defined as an input that will be TRUE if it is THRESHOLD otherwise it is FALSE. Description of INITIAL OUTPUT The initial output of all logic tokens is zero volts. 15

16 Unused Inputs The complete behavior of tokens having disconnected inputs is not discussed here. It is recommended that a logic token have at least one input connection. In the case of a named token with multiple inputs, if at least one of the inputs is connected, the other disconnected inputs behave as if ZERO volts were applied to them. A Step Function Source token may be used as an input source, by setting the amplitude value to either a one or zero. (The DAC is an example of a named input token - D0, D1, D2, etc. The generic NAND gate is an example of an unnamed input token.) Router Tokens The token library includes a Router token, located at the top of the token symbols. This token is smaller than others, and is passive, without parameters. A router is typically used to help define signal paths in a particular system, by stretching a signal path into an area on the workspace other than the default path. Router tokens help the user define the signal paths between tokens that have multiple input/output connections. In SystemView, the input/output of a router token is fed into the input/output of other tokens; the router is used to help prevent line crossing and subsequent confusion. Bi-directional data flow, and 3-State (not supported) SystemView does not support bi-directional data flow, or the High Impedance Output State (3-State). For example, in a SPDT switch, a signal can only enter the input connection; it cannot exit the input connection. Another example is the Universal Shift Register, which is not supported because SystemView cannot preset (load) the register through the output connections. For the same reason, the register could not be instructed to shift left and then to shift right. Description of SET* The following applies to all tokens 16

17 Some logic tokens (Flip-Flops, Registers, Counters, etc.) have an input that sets all storage elements to a HIGH state. The SET* function is an active LOW. (Also, indicated with a line over the word SET.) When a SET* occurs, it is treated as a direct input, with no setup time. All other inputs and clocks to a logic token are ignored. When a token is not being SET*, a HIGH state should be applied to the token, instead of being disconnected. Logic Since SET* is treated as a direct input, its effect on the outputs follows the rules for PROPAGATION DELAY time as described above. Description of RESET*, MASTER RESET* (MR*), and CLEAR* Some logic tokens (Flip-Flops, Registers, Counters, etc.) have an input that clears all storage elements to a LOW state. The various names of this input may be referred to as RESET*, MASTER RESET* (MR*), or CLEAR*. All three types of these inputs follow the same rules, only the RESET* input will be described. Usually the RESET* function is an active LOW. (Also, indicated with a line over the word RESET.) When a RESET* occurs, it is treated as a direct input, with no setup time. All other inputs and clocks to a logic token are ignored. When RESET* is not being applied to a token, a HIGH state should be applied to the token, instead of being disconnected. Since RESET* is treated as a direct input, its effect on the outputs follows the rules for PROPAGATION DELAY time as described above. Occasionally, as in the Counter, RESET* will be an active HIGH. Description of Rise Time and Fall Time The delay value is entered as a time in seconds, and should be an integer multiple of the system sample time, dt. If the propagation delay is not an 17

18 integer multiple of the systems dt, the value will be rounded up or down and may produce a delay that is different than expected. Three tokens have a combined Rise/Fall Time parameter. For these tokens, the one entry sets the value for both parameters. The tokens are the One Shot, the PROM, and the A/D Converter. Four tokens have no Rise or Fall Time parameter; they are the D/A Converter, the Analog Comparator, the SPDT and the DPDT switches. The Buffer Logic Token Special Uses: In SystemView, Buffers are not required in the traditional sense. All logic tokens have infinite fan-out capability, and have no loading effects. A Buffer can be used to make a particular system more pleasing to look at by stretching a signal path into an area on the workspace other than the default path. A Buffer can be used to shift digital outputs to allow more readable waveforms in the PLOT window. In SystemView, an output of a token may not be fed directly back into the input of the same token. A buffer token may be used in this loop to allow a direct feedback, and can also be used as a one-bit Analog-to-Digital Converter (ADC), or a one-input Comparator. 18

19 Logic LOGIC LIBRARY TOKEN DESCRIPTIONS 19

20 Token Name: Abbreviation: Group: AND gate AND Generic Synopsis: This token implements the AND function. It may have two or more inputs. See Also: none Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Multiple logic level signals Token Outputs: Single logic level signal. Truth Table: Summarized in the discussion below. Discussion: All HIGH inputs give a HIGH output; any LOW input gives a LOW output. LOGIC SYMBOL 20

21 Token Name: Abbreviation: Group: NAND gate NAND Generic Synopsis: This token implements the NAND function. It may have two or more inputs. Logic See Also: Schmitt Input Schmitt NAND Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Multiple logic level signals Token Outputs: Single logic level signal. Truth Table: See Discussion Discussion: Any LOW input gives a HIGH output, all HIGH inputs gives a LOW output. LOGIC SYMBOL 21

22 Token Name: Abbreviation: Group: OR gate OR Generic Synopsis: This token implements the OR function. It may have two or more inputs. See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Multiple logic level signals Token Outputs: Single logic level signal. Truth Table: Summarized in the discussion below. Discussion: Any HIGH input gives a HIGH output, all LOW inputs gives a LOW output. LOGIC SYMBOL 22

23 Token Name: Abbreviation: Group: Exclusive OR gate XOR Generic Synopsis: This token implements the Exclusive OR function. Logic See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Multiple logic level signals Token Outputs: Single logic level signal. Truth Table: Summarized in the discussion below. Discussion: Two HIGHs in or two LOWs in gives a LOW output, while opposite inputs results in a HIGH output. LOGIC SYMBOL 23

24 Token Name: Abbreviation: Group: NOR gate NOR Generic Synopsis: This token implements the NOR function. See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Multiple logic level signals Token Outputs: Single logic level signal. Truth Table: Summarized in the discussion below. Discussion: Any HIGH input gives a LOW output, while all LOW inputs give a HIGH output. LOGIC SYMBOL 24

25 Token Name: Group: Type: Buffer (non-inverting) Buffer Generic Synopsis: This token implements the buffer logic function. Logic See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.8 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Single logic level input signal Token Outputs: Single logic level output signal. Truth Table: Input Output L L H H Discussion: None LOGIC SYMBOL 25

26 Token Name: Group: Type: Inverter Invert 7404 Synopsis: This token implements the inverter logic function. See Also: Schmitt Schmitt Trigger Inverter Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Single logic level input signal Token Outputs: Single logic level output signal. Truth Table: Input Output L H H L Discussion: None LOGIC SYMBOL 26

27 Token Name: Group: Type: Schmitt Trigger Inverter Schmitt Synopsis: This token implements the inverter logic function. Logic See Also: Invert 7404Inverter Parameters: (default values shown) Parameter Value Parameter Value Parameter Value Gate Delay (seconds) 0 True Output (v) 1 Fall Time 0 Upper Threshold (v).8 False Output (v) 0 Lower Threshold (v).2 Rise Time (s): 0 Token Inputs: Single logic level input signal Token Outputs: Single logic level output signal. Truth Table: Input Output L H H L Discussion: None LOGIC SYMBOL 27

28 Token Name: Abbreviation: Type: D-Type Flip-Flop, positive-edge-triggered FF-D Synopsis: This token implements the D-Type positive-edge-triggered flop-flop logic function. See Also: FF-JK* J-K* Type Flip-Flop, positive-edge-triggered Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: One DATA signal One Clock signal One SET* signal One CLEAR* signal Token Outputs: Two logic signals: Q, Q*. Truth Table: 28

29 Inputs Outputs Set* Clear* Clock D Q Q* L H X X H L H L X X L H L L X X H? H? H H Λ H H L H H Λ L L H H H L X Q 0 Q 0 * H = HIGH level (steady state), L=LOW level (steady state) X = Irrelevant (any input, including transitions) Λ = Transition from LOW-to-HIGH level. Q 0 = Q level before established steady state input conditions. Q 0 * =This condition is non-stable; that is, it will not persist when the preset and clear inputs return to their inactive HIGH level. Logic Discussion: Each LOW-to-HIGH clock pulse shifts the data into Q that existed before the rising clock edge. The Set and Clear inputs are independent of the clock, and are accomplished by a LOW level at the respective input. The token contains only one Flip-Flop. LOGIC SYMBOL 29

30 Token Name: Abbreviation: Group: J-K* Type Flip-Flop, positive-edge-triggered FF-JK* Synopsis: This token implements the J, positive-edge-triggered flop-flop logic function, not the K type. See Also: FF-D D-Type Flip-Flop, positive-edge-triggered Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: One DATA signal: J, K* One Clock signal One SET* signal One CLEAR* signal Token Outputs: Two logic signals: Q, Q*. 30

31 Truth Table: Inputs Outputs Set* Clear* Clock J K* Q Q* L H X X X H L H L X X X L H L L X X X H? H? H H Λ L L L H H H Λ H L Toggle H H Λ L H Q 0 Q 0 * H H Λ H H H L H H L X X Q 0 Q 0 * H = HIGH level (steady state), L=LOW level (steady state) X = Irrelevant (any input, including transitions) Λ = Transition from LOW-to-HIGH level. Q 0 = Q level before the established steady state input conditions. H? = This condition is non-stable; that is, it will not persist when the preset and clear inputs return to their inactive HIGH level. Logic Discussion: The Set and Clear inputs are independent of the clock and are accomplished by a LOW level at the respective input. The JK* design allows operation as a D flip-flop (7474) by connecting the D input signal to both J and K* inputs. LOGIC SYMBOL 31

32 Token Name: Abbreviation: Type: Retriggerable Monostable Multivibrator One-shot Synopsis: This One-Shot features both a negative (A*), and a positive (B), transition input, either of which can be used as an inhibit input. Also included is a CLEAR* input that when taken LOW resets the one-shot. The one-shot can be triggered on the positive transition of the CLEAR while A is held LOW, and B is held HIGH. The output pulse width is determined by an entered parameter (time in seconds). See Also: None. Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Pulse Width (s): 0 True Output (v): 1 Rise/Fall Time (s): 0 Token Inputs: Two Control signals: A*, B One CLEAR* signal Token Outputs: Two logic signals: Q, Q*. 32

33 Truth Table: Inputs Outputs A* B Clear Q Q* Function V H H P N Output Enable X L H L H Inhibit H X H L H Inhibit L Λ H P N Output Enable L H Λ P N Output Enable X X L L H Reset H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) Λ = Transition from LOW- to- HIGH level. V = Transition from HIGH-to-LOW level. P = Momentary POSITIVE going output pulse. N = Momentary NEGATIVE going output pulse. Logic LOGIC SYMBOL Discussion: A LOW on the CLEAR* input, overrides all other inputs asynchronously, forcing the Q output LOW. Shown are three ways the one-shot is triggered. 33

34 Timing Diagrams for the 3 Modes of Operation of the One-Shot 34

35 Token Name: Abbreviation: Type: 2-Input Schmitt Trigger NAND Schmitt Synopsis: This token implements the 2-Input Schmitt Trigger NAND Function. Logic See Also: Generic NAND Parameters: (default values shown) Parameter Value Parameter Value Parameter Value Gate Delay (seconds) 0 True Output (v) 1 Fall Time 0 Upper Threshold (v).8 False Output (v) 0 Lower Threshold (v).2 Rise Time (s): 0 Token Inputs: Two logic signals Token Outputs: One logic signal Truth Table: Summarized in the discussion below. Discussion: Any LOW in gives a HIGH output, and all HIGH inputs give a LOW output. LOGIC SYMBOL 35

36 Token Name: Abbreviation: Group: 3-Line to 8-Line Decoder/Demultiplexer dmux-d Synopsis: When disabled, all outputs are HIGH. When enabled the 3 address inputs select which one of the 8 outputs will go LOW. To enable the selected output, two LOWs and one HIGH are required on the appropriate inputs. See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Three Select signals: A 0, A 1, and A 2 Two Negative Enable signals: E 1 * and E 2 * One Positive Enable signal: E 3 Token Inputs: 8 Logic signals: Truth Table: 36

37 FUNCTION TABLE Enable Address Outputs Inputs Inputs E 1 * E 2 * E 3 A 2 A 1 A H X X X X X H H H H H H H H X H X X X X H H H H H H H H X X L X X X H H H H H H H H Logic L L H L L L L H H H H H H H L L H L L H H L H H H H H H L L H L H L H H L H H H H H L L H L H H H H H L H H H H L L H H L L H H H H L H H H L L H H L H H H H H H L H H L L H H H L H H H H H H L H L L H H H H H H H H H H H L H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) Discussion: None 37

38 38

39 Token Name: Abbreviation: Type: 8-Input Digital Multiplexor Mux-D Synopsis: The ENABLE* input is active LOW. When it is HIGH, the Z output is LOW and the Z* output is HIGH regardless of all other inputs. When the ENABLE* input is LOW, the 3 select inputs determine which one of the 8 inputs will be passed through to the output. Logic See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Eight Logic Inputs: I 0, I 1, I 2, I 3, I 4, I 5, I 6, I 7 Three Select Signals: S 0, S 1, S 2 One Enable Signal: ENABLE* Token Outputs: Two Logic Signals: Z, Z* 39

40 Function Table Enable Input Select Inputs Outputs ENABLE* S 2 S 1 S 0 Z Z* H X X X L H L L L L I 0 I 0 * L L L H I 1 I 1 * L L H L I 2 I 2 * L L H H I 3 I 3 * L H L L I 4 I 4 * L H L H I 5 I 5 * L H H L I 6 I 6 * L H H H I 7 I 7 * H = L = X = HIGH Level (steady state) LOW Level (steady state) Irrelevant (any input, including transitions. Discussion: None Logic Symbol 40

41 LOGIC DIAGRAM Logic 41

42 Token Name: Abbreviation: Group: 4-Bit Synchronous Pre-settable Binary Counter Cntr Synopsis: This token implements the Synchronous Pre-settable 4-bit Binary Counter. See Also: Cntr-U/D Bit Synchronous Binary Up/Down Counter, with One Clock Cntr Stage Binary Counter Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs Token Outputs PE* Parallel Enable Inputs Q 0 - Q 3 4 Parallel Outputs CEP Count Enable Parallel Input TC Terminal Count CET Count Enable Trickle Input CLK Clock Pulse Input MR* Master Reset P 0 - P 3 4 Parallel Inputs 42

43 Truth Table: CLK MR* CEP CET PE* Function X L X X X Clear X H H L H Count & Rip. Cary. disabled X H L H H Count disabled X H L L H Count & Rip. Cary. disabled Λ H X X L Load counter with data Λ H H H H Increment counter Logic H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) Λ = Transition from LOW-to- HIGH level. Discussion: None. 43

44 44

45 Token Name: Abbreviation: Type: 8-Bit Serial-in/Parallel-out Shift Register Shft-8in Logic Synopsis: This token implements the shift register logic function. See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Two logic signals One clock signal One Master Reset* A and B CLK MR* Token Outputs: 8 Logic signals: Q 0, Q 1, Q 2, Q 3, Q 4, Q 5, Q 6, Q 7 45

46 Truth Table: MR* CLK A B Q 0 Q 1 Q 7 L X X X L L L H Λ L L Q 0 Q 0 Q 6 H Λ L H Q 0 Q 0 Q 6 H Λ H L Q 0 Q 0 Q 6 H Λ H H Q 0 Q 0 Q 6 H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) Λ = Transition from LOW- to- HIGH level. Q = Lower case numbers indicate the state of the referenced input or output one setup time (dt) prior to the LOW-to-HIGH clock transition. Discussion: Each LOW-to-HIGH clock pulse shifts data one place to the right and enters into Q 0, the logical AND of the two data inputs A and B that existed before the rising clock edge. The two logic inputs allow for the control over data entering the register. A LOW on either or both of the inputs resets the 1 st stage of the register to a LOW level at the next LOW-to-HIGH clock pulse. A LOW on the Master Reset* (MR*) input, overrides all other inputs asynchronously, thus forcing all outputs LOW. 46

47 47 Logic

48 Token Name: Abbreviation: Type: Quad D-Type Flip-Flop FF-D Synopsis: This token implements 4 D-Type positive-edge triggered flop-flops with a common Clock and Master Reset*. See Also: FF-D D-Type Flip-Flop, positive-edge triggered Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Token Outputs: D 0, D 1, D 2, D 3 DATA inputs Q 0, Q 1, Q 2, Q 3 CLK Clock Q 0 *, Q 1 *, Q 2 *, Q 3 * MR* Master Reset* 48

49 Truth Table: Inputs t n, MR* = t n+1 Dn L L L L H H H L H = HIGH Level (steady state) L = LOW Level (steady state) tn = Irrelevant (any input, including transitions) t n = Bit time before Clock Pulse t n+1 = Bit time after Clock Pulse Logic Discussion: Each LOW-to-HIGH clock pulse shifts the data at the inputs to the outputs that existed before the rising clock edge. The Master Reset* input is independent of the clock and is accomplished by a LOW level at the input. 49

50 50

51 Token Name: Abbreviation: Type: 4-Bit Synchronous Binary Up/Down Counter with one clock. Cntr-U/D Logic Synopsis: This token implements the Synchronous Pre-settable 4-bit Binary Counter. See Also: Cntr Bit Synchronous Pre-settable Binary Counter Cntr Stage Binary Counter Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Token Outputs: P 0, P 3 4 Parallel Inputs Q 0, - Q 3 4 Parallel outputs PL* Parallel Load (active LOW) TC Terminal Count output U*/D Up*/Down RC Ripple Clock output CE* Count Enable (active LOW) CLK Clock Pulse input 51

52 Mode Select Truth Table: PL* CE* U*/D CLK Mode H L L Λ Count Up H L H Λ Count Down L X X X Preset (Asynchronous) H H X X No Change (Hold) H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant (any input, including transitions) Λ = Transition from LOW- to- HIGH level. Discussion: None. 52

53 53 Logic

54 Token Name: Abbreviation: Type: 8-Bit Identity Comparator (Equality Detector) DigCmp Synopsis: This token will compare two words of up to 8-bits each, and provides a LOW output when the words match bit for bit. See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Token Outputs: 17 Logic Signals Single Logic Signal Truth Table: Inputs Output ENA* A, B O A=B* L A = B L L A* = B H = Equal H A = B H *= Not equal H A* = B H Discussion: The active LOW enable input (ENA*) also serves as an expansion input. 54

55 55 Logic

56 Token Name: Abbreviation: Type: 8-Bit Transparent Latch with Q Output Latch-8T Synopsis: This token implements 8 Transparent Latches with a common LATCH ENABLE. Except for the 3-State output, this token implements the 74373/74573 Latch function. See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Token Outputs: LE Latch Enable Q 0 - Q 7 8 Data Outputs Q 0 - Q 7 Data Inputs Truth Table: LE Dn Qn Function H L L Transparent to a HIGH H H H Transparent to a LOW L X Q 0 Hold the previous output state H L X = HIGH Level (steady state) = LOW Level (steady state) = Immaterial 56

57 Discussion: None. Logic 57

58 Token Name: Abbreviation: Type: 12-Stage Binary Counter Cntr Synopsis: This token implements the , 12-Stage Binary Counter. See Also: Cntr Bit Synchronous Pre-settable Binary Counter Cntr-U/D Bit Synchronous Binary Up/Down Counter, with One Clock Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Token Outputs: CLK* Clock Pulse input Q 0 - Q Data Outputs MR Master Reset Truth Table: CLK MR Function * X H Clear to all LOWs out V L Increment counter H L V = HIGH Level (steady state) = LOW Level (steady state) = Transition from HIGH-to-LOW level. 58

59 Discussion: This part is unusual in that its CLK is an active HIGH-to-LOW going edge, and its Master Reset is an active HIGH state. In SystemView, this 12-stage binary counter is modeled as a synchronous counter. All outputs change at the same time relative to the clock edge. The ripple effect (the output of each stage is the clock for the following stage) is not modeled. Logic 59

60 Token Name: Abbreviation: Type: Phase-Frequency Detector Ph/Frq MC4044 Synopsis: This token implements the Motorola MC4044 Digital Phase-Frequency Detector. Both Detector #1 and Detector #2 are included. The Charge-Pump portion of the IC is not included. See Also: None. Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Token Outputs: R Reference Phase detector 1: U 1 and D 1 V Variable Phase detector 2: U 2 and D 2 Discussion: There are three types of phase detectors. (1) Analog multiplier or mixer. (2) Exclusive-OR (digital equivalent of the analog multiplier). (3) Digital phase-frequency detector (CD4046 or MC4044 type). The main advantage of the analog phase detector is its ability to recover a signal from a low signal-tonoise input. It will also lock in on harmonics of the desired input. 60

61 For the noise free TTL signals found in a frequency synthesizer, the third type of phase detector is a better choice. The MC4044 responds only to the falling edges of the inputs eliminating the harmonics problem. This type of phase detector isn t perfect. An extra or missing pulse generates a large error for a short time, and the polarity of its feedback connection is important. Logic Truth Table: Input State R V U 1 D 1 U 2 D X X X X X X X X X X X X

62 62

63 Token Name: Abbreviation: Type: Set/Reset Latch (Two NAND gates, Cross-coupled) Latch-SR Custom Synopsis: This implements the Set/Reset Latch, from two cross-coupled NAND gates. Logic See Also: None. Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds): 0 False Output (v): 0 Threshold (v):.5 Rise Time (s): 0 True Output (v): 1 Fall Time (s): 0 Token Inputs: Token Outputs: One SET* signal 2 Logic signals: Q and Q* One RESET* signal Truth Table: Inputs Outputs SET* RESET* Q Q* L L H H L H H L H L L H H H Q 0 Q 0 H = HIGH Level (steady state) L = LOW Level (steady state) Q = The level of Q before the SET* and RESET* input conditions were established. Discussion: The default parameter of zero Output Delay may be used. When the Output Delay is not zero (one dt or more), the two outputs are delayed from each other due to the propagation time of each gate. An exception is when both the SET* and the RESET* inputs arrive together and track each other in time. 63

64 64

65 Token Name: Abbreviation: Type: 2-Channel Analog Multiplexor (SPDT Analog Switch) SPDT Custom Synopsis: The analog output of this SPDT switch is controlled by a digital input that has both threshold and delay parameters. Logic See Also: DPDT Custom 2-Channel Analog Multiplexor/Demux (DPDT Analog Switch) Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds) 0 Threshold (v).5 Token Inputs: Two analog signals, Inputs 0 and 1 One digital signal, Control Truth Table: Control Output H Input 1 L = LOW Level L Input 0 H = HIGH Level Discussion: None Logic Symbol Token Outputs: One analog signal, Output 65

66 Token Name: 2-Channel Analog Multiplexor/Demux (DPDT Analog Switch) Abbreviation: DPDT Type: Custom Synopsis: The analog outputs of this DPDT switch are controlled by a digital input that has both threshold and delay parameters. See Also: SPDT Custom 2-Channel Analog Multiplexor (SPDT Analog Switch) Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds) 0 Threshold (v).5 Token Inputs: Token Outputs: Four analog signals, Inputs 0 and 1 Two analog signals Output 0 Inputs 2 and 3 Output 1 One digital signal Control Truth Table: Control Output 0 Output 1 H Input 1 Input 3 L = LOW Level L Input 0 Input 2 H = HIGH Level Logic Symbol 66

67 Token Name: Abbreviation: Type: n-bit Analog to Digital Converter ADC Custom Synopsis: This implements a FLASH ADC having 1 to 16 bits of digital output. Logic See Also: Int/Dig Quantizer Sampler Custom n-bit Integer to Digital Converter Found in the SystemView Function Library Found in the SystemView Function Library Parameters: (default values shown) Parameter Value Parameter Value Parameter Value Gate Delay (seconds) 0 False Output (v) 0 Max Input (v) 1.27 Threshold (v).5 No. Bits: 8 Rise/Fall Time (s): 00 True Output (v) 1 Min Input (v): Token Inputs: One analog signal. One Encode signal. (O0 to O15) Token Outputs: Up to 16 digital outputs. Discussion: For analog inputs exceeding the Min/Max. Parameter value, the input is clamped at the Parameter value. The ENCODE input may be a square wave or momentary high going pulse. For either, the analog input is sampled at the LOW-to-HIGH transition of the ENCODE input. When the Output Delay is set to greater than 0, the delay should be integer number of sample time dt. 67

68 Token Name: Abbreviation: Type: n-bit Integer to Digital Converter Int/Dig Custom Synopsis: This token implements an n-bit Integer to Digital Converter that has 1 to 16 bits of 2 s complement digital output. The conversion is immediate, at the incoming clock rate. See Also: ADC Quantizer Sampler Custom n-bit Analog to Digital Converter Found in the SystemView Function Library Found in the SystemView Function Library Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds) 0 Number of bits) 8 True Output (v) 1 Rise Time (s): 0 False Output (v) 0 Fall Time (s): 0 Token Inputs: Token Outputs: One integer signal. Up to 16 digital outputs, in 2 s complement. (From another token or a file.) (O0 to O15) 68

69 Discussion: For integer inputs exceeding the (2 n-bits)-1 or ((2 n-bits) value, the input is clamped. When the Output Delay is set to values greater than zero, the delay should be integer number of the system s sample time, dt. Logic A 3-bit converter example: Input MSB LSB 2 s complement output

70 Token Name: Abbreviation: Type: n-bit Digital to Analog Converter DAC Custom Synopsis: This token implements an n-bit Digital to Analog Converter that has 1 to 16 bits of digital input. The conversion is immediate, at the incoming clock rate. See Also: None Parameters: (default values shown) Parameter Value Parameter Value Gate Delay (seconds) 0 Min. Output (v) Threshold (v).5 Max. Output (v) 1.27 Number of bits) 8 Token Inputs: Up to 16 digital inputs. (D0 to D15) May be either 2 s Complement or Unsigned Integer. Token Outputs: One analog signal. Discussion: None 70

71 A 3-bit converter example: MSB LSB Output (v) 2 s complement input (3/4) Maximum Output: (2/4) Minimum Input (1/4) (-1/4) (-2/4) (-3/4) (-4/4) Logic 71

72 Token Name: Abbreviation: Type: Comparator (Differential Analog Input, Q and Q* Output) AnaCmp Custom Synopsis: This token implements a two-input analog comparator. See Also: None Parameters: (default values shown) Parameter Gate Delay (seconds) 0 True Output (v) 1 False Output (v) 0 Value Token Inputs: Token Outputs: Two analog inputs, +IN and -IN Two digital outputs, Q and Q* Logic Function: Outputs Inputs Q Q* +IN = -IN H L > +IN < -IN L H Discussion: None Logic Symbol 72

73 Token Name: Abbreviation: Type: Programmable Read Only Memory (8 x 8) (No 3-state) PROM Custom Synopsis: Three address inputs select which one of eight; 8-bit words will appear at the output of the PROM. The contents of the PROM are entered as 4 parameters; each parameter specifies the data at two address locations. Logic See Also: None Parameters: (default values shown) Parameter Value Parameter Value Parameter Value Gate Delay (seconds) 0 False Output (v) 0 D-2 (Hex) 0 Threshold (v).5 D-0 (Hex) 0 D-3 (Hex) 0 True Output (v) 1 D-1 (Hex) 0 Rise/Fall Time(s): 0 Token Inputs: Three Address signals: A 0 A 1 A 2 One ENABLE* signal ENA* Token Outputs 8 Logic Signals O 0 O 1 O 1 O 3 O 4 O 5 O 6 O 7 LSB MSB 73

74 Programmable Read Only Memory Discussion: An example PROM programming is shown below. Address O 7 O F (Parameter Bytes 1,0) (Parameter Bytes 3,2) 8765 (Parameter Bytes 5,4) FF00 (Parameter Bytes 7,6) When Hexadecimal data is entered into a Parameter Field, the 4-digit Hex number does not require a prefix. Example: 208F When the PROM is ENABLED (ENA* = LOW), the PROM operates normally. When the PROM is DISABLED (ENA* = HIGH), the PROM puts out all Zeros). Logic Symbol 74