邏輯設計 Hw#6 請於 6/13( 五 ) 下課前繳交

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Sabina McCoy
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1 邏輯設計 Hw#6 請於 6/3( 五 ) 下課前繳交

2 . A sequential circuit with two D flip-flops A and B, two inputs X and Y, and one output Z is specified by the following input equations: D A = X A + XY D B = X A + XB Z = XB (a) Draw the logic diagram of the circuit. (b) Derive the table. (c) Derive the diagram. (a) (b) Present A B Inputs X Y Next A + B + Output Z

3 (c) Format: XY/Z (x = don t care) x/, x/ / x/ / / / / x/ / x/, /

4 2. Starting from in the diagram of figure, determine the transitions and output sequence that will be generated when an input sequence of is applied. State 變化 Input Output

5 3. A sequential circuit has two SR flip-flops, one input X, and one output Y. The logic diagram of the circuit is shown in figure. Derive the table and diagram of the circuit. S A = B R A = B S B = (X + A) R B = X + A Y = A + B + X A + = S A + R A A = B + (B ) A = B B + = S B + R B B = (X + A) + ((X + A) ) B = (X + A) Present A B Input X Next A + B + Output Y / x/ / / x/ Format: X/Y (x = don t care) /

6 4. A sequential circuit is given in figure. The timing parameters for the gates and flip-flops are as follows: Inverter: t pd =.5 ns XOR Gate: t pd = 2. ns Flip-flop: t pd = 2. ns, t s =. ns and t h =.25 ns (a) Find the longest path delay from an external circuit input passing through gates only to an external circuit output. (b) Find the longest path delay in the circuit from an external input to positive clock edge. (c) Find the longest path delay from positive clock edge to output. (d) Find the longest path delay from positive clock edge to positive clock edge. (e) Determine the maximum frequency of operation of the circuit in megahertz (MHz). (a) t delay = t pdxor 2 = 4. ns (b) t delay = t pdxor + t pbinv + t sff = 3.5 ns

7 4. (c) Find the longest path delay from positive clock edge to output. (d) Find the longest path delay from positive clock edge to positive clock edge. (e) Determine the maximum frequency of operation of the circuit in megahertz (MHz). (c) t delay = t pdff + t pdxor + t pdxor = 6. ns (d) t delay = t pdff + t pdxor + t pdinv + t sff = 2. ns + 2. ns +.5 ns +. ns = 5.5 ns (e) Maximum frequency = / t delay_max = / 6. ns = MHz

8 5. A Universal Serial Bus (USB) communication link requires a circuit that produces the sequence. You are to design a synchronous sequential circuit that starts producing this sequence for input E =. Once the sequence starts, it completes. If E =, during the last output in the sequence, the sequence repeats. Otherwise, if E =, the output remains constant at. (a) Draw the Moore diagram for the circuit. (b) Find the table and make a assignment. (c) Design the circuit using D flip-flops and logic gates. A reset should be include to place the circuit in the appropriate initial at which E is examined to determine if the sequence or constant s is to be produced. (a) E = E = S/ S7/ S/ S6/ S2/ S5/ (b) 因為有 ~7 共 8 個 s, 所以用 D 2 D D 3 bits 表示 Present Next S3/ For input Output D 2 D D E = E = Z S4/ Format: /output

9 5. (c) Design the circuit using D flip-flops and logic gates. A reset should be include to place the circuit in the appropriate initial at which E is examined to determine if the sequence or constant s is to be produced. (c) 根據 (b) Z = D 2 D D D 2+ = D 2 D + D 2 D + D 2 D D + D 2 D D E D + = D D + D 2 D D E D + = D + D 2 D D E 題目要求 reset 的作用是讓初始化成, 看 E 等於多少決定要產生還是一直是, 這跟 7 的行為完全相同, 所以將 reset 接到每個 D flip-flop 的 set

10 6. Find the logic diagram for the circuit having the table given in table. Use J-K flip-flops. Present Next Flip-Flop Input Output Inputs A B X A + B + Z J A K A J B K B 先寫出右圖的 flip-flop inputs X X 再寫出 input output equations X X J A = BX X X K A = B X X J B = X X X K B = X X X Z = AB X X X X X

發現沒有再打 X => A = C = F, D = E C = F B = D A = C D = E A = F B = E Present A B D Next I = I = A D A B B A

11 補充題 :State Reduction 化簡下列 diagram, 求出化簡後的 table B C Step. 根據右圖列出 table Step. I/O behavior 不同者打 X Step 2. 列出 next 關係 Step 3. 持續檢查因既有的 X 而不可能相同者打 X round. 綠色 X round 2. 發現沒有再打 X => A = C = F, D = E C = F B = D A = C D = E A = F B = E Present A B D Next I = I = A D A B B A Output I = I = Present A B C D E F Next I = I = C D F B A E B C B F A E Output I = I = D E B = B C = F F A = C D = E A = F B = E A = A E = E A B C D E

12 補充題 2:State Assignment Given the following diagram, select a good assignment. Show your assignment in a map and justify your answer in terms of the assignment guidelines. Present a b c d e Next I = I = a b c d a d e d a d Output I = I = Highest: s that share a common next (b, c, d, e) (a, c, e) Medium: s that share a common ancestor (a, b) (c, d) (a, d) (d, e) (a, d) => (a, b) (a, d) 2 (c, d) (d, e) Lowest: s that have common output behavior (a, b, c, d, e) (a, b, c) (d, e) Q Q Q 2 * 紅色底線表可符合之條件 * 答案非唯一 a d c e b

0 0 = 1 0 = 0 1 = = 1 1 = 0 0 = 1

0 0 = 1 0 = 0 1 = = 1 1 = 0 0 = 1 0 0 = 1 0 = 0 1 = 0 1 1 = 1 1 = 0 0 = 1 : = {0, 1} : 3 (,, ) = + (,, ) = + + (, ) = + (,,, ) = ( + )( + ) + ( + )( + ) + = + = = + + = + = ( + ) + = + ( + ) () = () ( + ) = + + = ( + )( + ) + = = + 0