CB2CE, CB4CE, CB8CE, CB16CE

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Allan Sullivan
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1 B2E, B4E, B8E, B16E R B2E, B4E, B8E, B16E 2-, 4-, 8-,16-Bit ascadable Binary ounters with lock Enable and Asynchronous lear Architectures Supported B2E, B4E, B8E, B16E Spartan-II, Spartan-IIE Spartan-3 Virtex, Virtex-E Virtex-II, Virtex-II Pro, Virtex-II Pro X X9500, X9500XV, X9500XL oolrunner XPLA3 oolrunner-ii oolrunner-iis No E B2E EO T X4353 B2E, B4E, B8E, and B16E are, respectively, 2-, 4-, 8-, and 16-bit (stage), asynchronous, clearable, cascadable binary counters. The asynchronous clear () is the highest priority input. When is High, all other inputs are ignored; the Q outputs, terminal count (T), and clock enable out (EO) go to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input (E) is High during the Low-to-High clock () transition. The counter ignores clock transitions when E is Low. The T output is High when all Q outputs are High. E B4E EO T X4357 Larger counters are created by connecting the EO output of the first stage to the E input of the next stage and connecting the and inputs in parallel. EO is active (High) when T and E are High. The maximum length of the counter is determined by the accumulated E-to-T propagation delays versus the clock period. The clock period must be greater than n(t E-T ), where n is the number of stages and the time t E-T is the E-to-T propagation delay of each stage. When cascading counters, use the EO output if the counter uses the E input; use the T output if it does not. The counter is asynchronously cleared, outputs Low, when power is applied. E B8E Q[7:0] EO T For X9500/XV/XL, oolrunner XPLA3, and oolrunner-ii, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. X4361 Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex- II Pro X simulate power-on when global set/reset (GSR) is active. E B16E Q[15:0] EO GSR defaults to active-high but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol. T Inputs Outputs X4365 E Qz- T EO 1 X X X No hg No hg 0 Libraries Guide ISE 6.li

2 R B2E, B4E, B8E, B16E Inputs Outputs E Qz- T EO 0 1 Inc T EO z= 1 for B2E; z = 3 for B4E; z = 7 for B8E; z = 15 for B16E T = Qz Q(z-1) Q(z-2)... EO = T E Libraries Guide ISE 6.li

3 B2E, B4E, B8E, B16E R V FTE Q[7:0] T Q E FTE E T2 FTE E AND3 T3 FTE E AND4 T4 FTE E Q4 T5 Q4 FTE E Q5 AND3 T6 Q5 FTE E Q6 AND4 T7 Q6 FTE E E Q7 Q7 T AND5 X8136 EO B8E Implementation Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Libraries Guide ISE 6.li

4 R B2E, B4E, B8E, B16E Virtex-II, Virtex-II Pro, Virtex-II Pro X V E FD D Q XOR2 AND3 EO T FD D Q XOR2 B2E Implementation X9500/XV/XL, oolrunner XPLA3, oolrunner-ii X Libraries Guide ISE 6.li

5 B2E, B4E, B8E, B16E R E B2E E EO T B0 B2E E EO T B2 B2E E EO T B4 Q4 Q5 B2E E EO T B6 Q6 Q7 EO T X7783 AND4 B8E Implementation X9500/XV/XL, oolrunner XPLA3, oolrunner-ii Usage For HDL, these design elements are inferred rather than instantiated. VHDL Inference ode architecture Behavioral of cb2ce is constant TERMINAL_OUNT : std_logic_vector(width-1 downto 0) := (others => 1 ); process(, ) if (= 1 ) then Q <= (others => 0 ); elsif ( event and = 1 ) then Libraries Guide ISE 6.li

6 R B2E, B4E, B8E, B16E if (E= 1 ) then Q <= Q+1; end if; end if; end process; process (Q) if (Q = TERMINAL_OUNT) then T <= 1 ; else T <= 0 ; end if; end process; EO<=T and E; end Behavioral; Verilog Inference ode (posedge or posedge ) if () Q <= 0; else if (E) Q <= Q + 1; end (Q) if (Q == TERMINAL_OUNT) T <= 1; else T <= 0; end (E or T) E0 <= T && E; end Libraries Guide ISE 6.li

Digital Fundamentals

Digital Fundamentals Tenth Edition Floyd hapter 8 Modified by Yuttapong Jiraraksopakun Floyd, Digital Fundamentals, 10 th 2008 Pearson Education ENE, KMUTT ed 2009 ounting in Binary As you know, the binary