CSE 320: Spartan3 I/O Peripheral Testing

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1 CSE 320: Spartan3 I/O Peripheral Testing Ujjwal Gupta, Kyle Gilsdorf Arizona State University Version 1.1 October 2, 2012 Contents 1 Introduction 2 2 Test code description and procedure Modes Mode Mode Mode Mode Test Procedure Step Step Step Step Step A Appendix-1: Top level module 4 B Appendix-2: Clock divider module 7 C Appendix-3: UCF File 9 D References 10 E Modification history 10 1

2 1 Introduction This document serves as a guide to understand and use the code for testing the input and output peripherals of Spartan 3 FPGA starter board in the CSE-320 Lab. The code has been written using Verilog HDL. 2 Test code description and procedure Following Peripherals are to be tested: 4 Push buttons 8 Slide switches 8 LEDs 4 Seven segment displays 2.1 Modes Each Push button is associated with a mode. In total we are using 4 modes in this design out of which 3 are of primary importance. Although there can be number of modes due to 4 push buttons, one of the push buttons is reset (active high), so effectively we have number of modes to choose from. Presently our code uses only 3 test modes and one reset mode (which is implied) Mode1 On a reset mode, all LEDs are ON and Seven segment will be OFF Mode2 The 8 LEDs will display one to one mapped value on the 8 DIP switches Mode3 A shift register from left to right on the 8 LEDs and the seven segment will blink ON and OFF (all 4 together). The previous value of LEDs and seven segment will be retained and used for first few clock cycles depending on the previous state and value. 2

3 2.1.4 Mode4 A piecewise blink chain of scan return on the seven segments from left to right will be seen. 2.2 Test Procedure Follow the procedure to test the board s IO peripheral functionality Step 1 Write the spartan3 board test.bit file to the FPGA using appropriate tool (refer to lab0 on how to do this) Step 2 Press BTN2 (L13) on the board, you will come into mode1. In this mode, the value on the DIP switches will be displayed. Play around by changing the DIP switch values Step 3 Press BTN1 (M14), you will see that seven segment displays start blinking all at once. The LEDs will also appear to blink in a line fashion Step 4 Press BTN0 (M13), you will see that seven segment displays go in a scan chain fashion. The LED will retain the previous state value Step 5 Press BTN1 again, what do you observe? Is this a good design? Also see what is the counter value used in clk divider.v file, is such a large comparison good in practice? The answer to this is that practically this is not a very good design, since the LEDs or seven segments may be in any random state when we switch between mode 3 and mode 4. We should be deterministic in our designing approach. Such a code can be used to test a primitive board like this one, but certainly not in a real application. The counter value in clock divider is 24 bits, this is a lot of combinational logic (with comparators) and will constraint the clock speed. Also all the logic might not be in same region in FPGA, which may reduce reliability. To solve this we can divide the counters into smaller counters. 3

4 A Appendix-1: Top level module spartan3 board test.v 1 // 2 // Copyright ( c ) 2012, ARIZONA STATE UNIVERSITY 3 // 4 // P r o j e c t : Spartan 3 Board t e s t 5 // 6 // Course : CSE 320 by Kyle G i l s d o r f, F a l l // F i l e : s p a r t a n 3 b o a r d t e s t. v 8 // Author : Ujjwal Gupta ( u j j w a l. gupta@asu. edu ) 9 // Last modified : Oct, // 11 // D e s c r i p t i o n : Top l e v e l RTL module f o r checking the f u n c t i o n a l i t y 12 // o f FPGA boards p e r i p h e r a l s 13 // 14 // M o d i f i c a t i o n h i s t o r y : 15 // 16 // Date Version Modified By D e s c r i p t i o n 17 // 18 // Aug, Ujjwal Created 19 // module s p a r t a n 3 b o a r d t e s t ( / AUTOARG / 22 // Outputs 23 o l e d, o s e v s e g s e l, o s e v s e g d r v, 24 // Inputs 25 i r s t, i s y s c l k, i p u s h b t n, i s l i d e s w i t c h 26 //, o t e s t c l k 27 ) ; // BTN3, u s e r r e s e t 30 input wire i r s t ; 31 // 50MHz c l o c k 32 input wire i s y s c l k ; 33 // 3 Push Buttons 34 input wire [ 2 : 0 ] i p u s h b t n ; 35 // 8 DIP s w i t c h e s 36 input wire [ 7 : 0 ] i s l i d e s w i t c h ; 37 // 8 output LEDs 38 output reg [ 7 : 0 ] o l e d ; 39 // Chosing one or more o f 4 seven seg LEDs 40 output reg [ 3 : 0 ] o s e v s e g s e l ; 41 // 7 seg l e d d r i v e r value 42 output reg [ 7 : 0 ] o s e v s e g d r v ; // Slow c l o c k 46 wire b l i n k c l k i ; // Double r e g i s t e r i n g the e x t e r n a l i n p u t s 49 reg [ 2 : 0 ] p u s h b t n s t a t e i ; 50 reg [ 2 : 0 ] p u s h b t n r e g 1 i ; 51 reg [ 2 : 0 ] p u s h b t n r e g 2 i ; 52 reg [ 7 : 0 ] s l i d e s w i t c h r e g 1 i ; 53 reg [ 7 : 0 ] s l i d e s w i t c h r e g 2 i ; // Parameterized modes 56 parameter [ 2 : 0 ] MODE2 = 3 b100, MODE3 = 3 b010, MODE4 = 3 b001 ; 57 4

5 58 // I n s t a n t i a t i n g the c l o c k d i v i d e r module 59 c l k d i v i d e r c l k d i v i d e r u 1 ( 60 // Outputs 61. o b l i n k c l k ( b l i n k c l k i ), 62 // Inputs 63. i r s t n (! i r s t ), 64. i s y s c l k ( i s y s c l k ) ) ; // Double R e g i s t e r i n g the push button input and s l i d e switch 67 ( posedge b l i n k c l k i or posedge i r s t ) begin 68 i f ( i r s t == 1 b1 ) begin 69 p u s h b t n r e g 1 i <= 3 d0 ; 70 p u s h b t n r e g 2 i <= 3 d0 ; 71 end 72 e l s e begin 73 p u s h b t n r e g 1 i <= i p u s h b t n ; 74 p u s h b t n r e g 2 i <= p u s h b t n r e g 1 i ; 75 end 76 end 77 ( posedge b l i n k c l k i or posedge i r s t ) begin 78 i f ( i r s t == 1 b1 ) begin 79 s l i d e s w i t c h r e g 1 i <= 8 d0 ; 80 s l i d e s w i t c h r e g 2 i <= 8 d0 ; 81 end 82 e l s e begin 83 s l i d e s w i t c h r e g 1 i <= i s l i d e s w i t c h ; 84 s l i d e s w i t c h r e g 2 i <= s l i d e s w i t c h r e g 1 i ; 85 end 86 end // Making Push buttons l a t c h f o r use as s t a t e modes 89 ( posedge b l i n k c l k i or posedge i r s t ) begin 90 i f ( i r s t == 1 b1 ) begin 91 p u s h b t n s t a t e i <= 3 b000 ; 92 end 93 e l s e i f ( p u s h b t n r e g 2 i == 3 d0 ) 94 p u s h b t n s t a t e i <= p u s h b t n s t a t e i ; 95 e l s e 96 p u s h b t n s t a t e i <= p u s h b t n r e g 2 i ; 97 end // Main p r o c e s s f o r d r i v i n g LEDs and Seven Segment LEDs 100 ( posedge b l i n k c l k i or posedge i r s t ) begin 101 i f ( i r s t == 1 b1 ) begin 102 o l e d <= 8 hff ; // A l l LEDs ON 103 o s e v s e g d r v <= 8 hff ; // A l l seven segment d i s p l a y s OFF 104 o s e v s e g s e l <= 4 hf ; // A l l seven segment d i s p l a y s s e l e c t e d 105 end 106 e l s e begin 107 c a s e ( p u s h b t n s t a t e i ) 108 MODE2 : begin 109 // LED d i s p l a y s s l i d e switch value 110 o l e d <= s l i d e s w i t c h r e g 2 i ; 111 o s e v s e g s e l <= 4 hf ; 112 o s e v s e g d r v <= 8 h00 ; 113 end 114 MODE3 : begin 115 i f ( o l e d <= 8 d0 ) begin 116 o l e d <= 8 hff ; 117 o s e v s e g s e l <= 4 hf ; 118 o s e v s e g d r v <= 8 h00 ; 119 end 5

6 120 e l s e begin 121 // Right s h i f t 122 o l e d <= {1 b0, o l e d [ 7 : 1 ] } ; 123 // A l l 7 seg are ON and OFF at each c l o c k c y c l e 124 o s e v s e g s e l [ 3 : 0 ] <= o s e v s e g s e l [ 3 : 0 ] ; 125 end 126 end 127 MODE4: begin 128 // Scan chain the seven seg LEDs b i t by b i t 129 i f ( o s e v s e g s e l == 4 hf) 130 o s e v s e g s e l <= 4 h0 ; 131 e l s e i f ( o s e v s e g d r v == 8 d0 ) begin 132 o s e v s e g d r v <= 8 hff ; 133 o s e v s e g s e l <= {1 b1, o s e v s e g s e l [ 3 : 1 ] } ; 134 end 135 e l s e 136 o s e v s e g d r v <= {1 b0, o s e v s e g d r v [ 7 : 1 ] } ; 137 end 138 d e f a u l t : begin 139 o l e d <= 8 hff ; 140 o s e v s e g d r v <= 8 h00 ; 141 o s e v s e g s e l <= 4 hf ; 142 end 143 endcase 144 end 145 end 146 // Test p o i n t s 147 // output wire o t e s t c l k ; 148 // a s s i g n o t e s t c l k = b l i n k c l k i ; endmodule // s p a r t a n 3 b o a r d t e s t 6

7 B Appendix-2: Clock divider module clk divider.v 1 // 2 // Copyright ( c ) 2012, ARIZONA STATE UNIVERSITY 3 // 4 // P r o j e c t : Spartan 3 Board t e s t 5 // 6 // Course : CSE 320 by Kyle G i l s d o r f, F a l l // F i l e : c l k d i v i d e r. v 8 // Author : Ujjwal Gupta ( u j j w a l. gupta@asu. edu ) 9 // Last modified : Oct, // 11 // D e s c r i p t i o n : Slow c l o c k g e n e r a t i o n to view the b l i n k i n g o f LEDs 12 // + Blink Freq r e q u i r e d i s around 50Hz, more than 13 // 100Hz i s not d i f f e r e n t i a b l e by human eye! 14 // + Current d e s i g n i s not a good way to compare 15 // counter value What do you think w i l l be a b e t t e r 16 // approach? 17 // ( Hint : Can we d i v i d e a big counter i n t o s m a l l 18 // ones?) 19 // 20 // M o d i f i c a t i o n h i s t o r y : 21 // 22 // Date Version Modified By D e s c r i p t i o n 23 // 24 // Aug, Ujjwal Created 25 // module c l k d i v i d e r ( / AUTOARG / 28 // Outputs 29 o b l i n k c l k, 30 // Inputs 31 i r s t n, i s y s c l k 32 ) ; input i r s t n ; // Active low r e s e t 35 input i s y s c l k ; // System c l o c k 36 output reg o b l i n k c l k ; // output b l i n k c l o c k // Parameterized Counter : Change t h e s e 3 l i n e s 39 // o f code to make changes to c l k d i v i s i o n. 40 parameter [ 2 3 : 0 ] CLK DIV VALUE = 24 h9fffe0 ; 41 parameter [ 2 3 : 0 ] COUNTER RST = 24 d0 ; 42 reg [ 2 3 : 0 ] c o u n t e r d i v i ; ( posedge i s y s c l k or negedge i r s t n ) begin 46 i f ( i r s t n == 1 b0 ) begin 47 o b l i n k c l k <= 1 b0 ; 48 end 49 e l s e begin 50 i f ( c o u n t e r d i v i <= (CLK DIV VALUE/2) 1) 51 begin 52 o b l i n k c l k <= 1 b1 ; 53 end 54 e l s e i f ( c o u n t e r d i v i < CLK DIV VALUE 1) 55 begin 56 o b l i n k c l k <= 1 b0 ; 57 end 7

8 58 end 59 end // Making counter zero, a f t e r i t has counted to the 62 // r e q u i r e d value. 63 ( posedge i s y s c l k or negedge i r s t n ) begin 64 i f ( i r s t n == 1 b0 ) begin 65 c o u n t e r d i v i <= COUNTER RST; 66 end 67 e l s e begin 68 i f ( c o u n t e r d i v i >= CLK DIV VALUE 1) begin 69 c o u n t e r d i v i <= COUNTER RST; 70 end 71 e l s e 72 c o u n t e r d i v i <= c o u n t e r d i v i + 1 ; 73 end 74 end endmodule // c l k d i v i d e r 8

9 C Appendix-3: UCF File spartan3 board test.ucf 1 NET i s y s c l k TNM NET = CLK; 2 TIMESPEC TS CLK = PERIOD CLK 20 ns HIGH 50%; 3 4 # PlanAhead Generated p h y s i c a l c o n s t r a i n t s 5 NET i s y s c l k LOC = T9 ; 6 NET i r s t LOC = L14 ; 7 # 8 NET i p u s h b t n [ 2 ] LOC = L13 ; 9 NET i p u s h b t n [ 1 ] LOC = M14 ; 10 NET i p u s h b t n [ 0 ] LOC = M13 ; 11 # 12 NET i s l i d e s w i t c h [ 0 ] LOC = F12 ; 13 NET i s l i d e s w i t c h [ 1 ] LOC = G12 ; 14 NET i s l i d e s w i t c h [ 2 ] LOC = H14 ; 15 NET i s l i d e s w i t c h [ 3 ] LOC = H13 ; 16 NET i s l i d e s w i t c h [ 4 ] LOC = J14 ; 17 NET i s l i d e s w i t c h [ 5 ] LOC = J13 ; 18 NET i s l i d e s w i t c h [ 7 ] LOC = K14 ; 19 NET i s l i d e s w i t c h [ 6 ] LOC = K13 ; 20 # 21 NET o l e d [ 0 ] LOC = K12 ; 22 NET o l e d [ 1 ] LOC = P14 ; 23 NET o l e d [ 2 ] LOC = L12 ; 24 NET o l e d [ 3 ] LOC = N14 ; 25 NET o l e d [ 4 ] LOC = P13 ; 26 NET o l e d [ 5 ] LOC = N12 ; 27 NET o l e d [ 6 ] LOC = P12 ; 28 NET o l e d [ 7 ] LOC = P11 ; 29 # 30 NET o s e v s e g d r v [ 0 ] LOC = P16 ; 31 NET o s e v s e g d r v [ 1 ] LOC = N15 ; 32 NET o s e v s e g d r v [ 2 ] LOC = G13 ; 33 NET o s e v s e g d r v [ 3 ] LOC = E14 ; 34 NET o s e v s e g d r v [ 4 ] LOC = F13 ; 35 NET o s e v s e g d r v [ 5 ] LOC = R16 ; 36 NET o s e v s e g d r v [ 6 ] LOC = P15 ; 37 NET o s e v s e g d r v [ 7 ] LOC = N16 ; 38 # 39 NET o s e v s e g s e l [ 3 ] LOC = E13 ; 40 NET o s e v s e g s e l [ 2 ] LOC = F14 ; 41 NET o s e v s e g s e l [ 1 ] LOC = G14 ; 42 NET o s e v s e g s e l [ 0 ] LOC = D14 ; 9

10 D References Spartan 3 Starter Kit Board User Guide, UG130 (v1.1) May 13, 2005 E Modification history Date Version Description Oct, v1.0 Created, posted on CSE320 website Oct,02,2012 v1.1 Made 1.2 heading name change, removal of redundant counter process from top level module,minor typo. 10

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