Module half adder module half_adder(output S,C,input x,y); xor(s,x,y); and(c,x,y); endmodule

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1 Eric Blasko Dr. Tong Yu CSE-310 digital logic Spring 2018 Homework 4, due 5/28/2018 ( Mon ) 12 pm 1. (15 points) Textbook Problems 4.37: Write the HDL gate-level hierarchical description of a four-bit adder-subtractor for unsigned binary numbers. The circuit is similar to Fig.4.13 but without output V. You can instantiate the four-bit full adder described in HDL Example 4.2. (HDLâ see Problems 4.13 and 4.40.) Write a test bench to test your module. Module half adder module half_adder(output S,C,input x,y); xor(s,x,y); and(c,x,y); module full_adder(output S, C, input x,y,z); wire S1,C1,C2; half_adder HA1(S1,C1,x,y); half_adder HA2(S,C2,S1,z); or G1(C,C2,C1); Module 4-bit add sub module four_bit_add_sub(output[3:0] S,output C, input[3:0] A,B, input M); wire [3:0] B_xor_M; wire C1, C2, C3, C4; assign C = C4; xor (B_xor_M[0],B[0],M), (B_xor_M[1],B[1],M), (B_xor_M[2],B[2],M), (B_xor_M[3],B[3],M); full_adder FA0 (S[0],C1,A[0],B_xor_M[0],M), FA1 (S[1],C2,A[1],B_xor_M[1],C1), FA2 (S[2],C3,A[2],B_xor_M[2],C2), FA3 (S[3],C4,A[3],B_xor_M[3],C3); Test Bench module four_bit_add_sub_tb(); wire[3:0] S; wire C; reg[3:0] A,B;

2 reg M; A = 4'h0; B = 4'h0; M = 1; $display("time\t A[3-0] b[3-0] M C S[3-0]"); $monitor("%g\t %4b %4b %b %b %4b",$time,A,B,M,C,S); four_bit_add_sub uut(s,c,a,b,m); A=4'b0000; B=4'b0000; M=1'b1; #10 A=4'b0100; B=4'b0000; M=1'b1; #10 A=4'b0100; B=4'b0011; M=1'b1; #10 A=4'b0100; B=4'b0011; M=1'b1; #10 A=4'b1100; B=4'b0011; M=1'b1; #10 A=4'b1100; B=4'b0011; M=1'b1; #10 A=4'b0100; B=4'b0000; M=1'b0; #10 A=4'b0100; B=4'b0011; M=1'b0; #10 A=4'b0100; B=4'b0011; M=1'b0; #10 A=4'b1100; B=4'b0011; M=1'b0; #10 A=4'b1100; B=4'b0011; M=1'b0; #10 A=4'b0111; B=4'b0110; M=1'b0; #10 A=4'b1000; B=4'b1001; M=1'b0; #10 A=4'b1100; B=4'b1000; M=1'b1; #10 A=4'b0101; B=4'b1010; M=1'b1; #10 A=4'b0000; B=4'b0001; M=1'b1; #10 $finish; Output time A[3-0] b[3-0] M C S[3-0]

3 hw4]$ 2. (10 points) Textbook Problems 4.13 (p.184):the adder-subtractor circuit of Fig has the following values for mode input M and data inputs A and B. M A B A B C D E In each case, determine the values of the four SUM outputs, the carry C, and overflow V. Use the Verilog program you developed above to verify your results. (You may refer to the video 4-bit Adder-Subtractor.) The circuit acts as an adder (A+B) in input M = 0. Acts as a subtractor (A-B) when M = 1. a) M = 0 input C0 = 0 A=0111 B=0110 C3 C2 C1 C C C4 = 0 and C3 = 1 V = (C4 Xor C3) = (0 Xor 1) = 1 Thus, the sum is V is 1 and C4 = C is 0. b) M = 0, input C0 = 0 A=1000 B=1001 C3 C2 C1 C C C4 = 1 and C3 = 0 V = (C4 Xor C3) = (1 Xor 0) = 1 Thus, the sum is V is 1 and C4 = C is 1. c) M = 1, input C0 = 1 A=1100 B=1000

4 C3 C2 C1 C C C4 = 1 and C3 = 1 V = (C4 Xor C3) = (1 Xor 1) = 0 Thus, the sum is V is 0 and C4 = C is 1. d) M = 1, input C0 = 1 A=0101 B=1010 C3 C2 C1 C C C4 = 0 and C3 = 1 V = (C4 Xor C3) = (0 Xor 1) = 1 Thus, the sum is V is 1 and C4 = C is 0. e) M = 1, input C0 = 1 A=0000 B=0001 C3 C2 C1 C C C4 = 0 and C3 = 0 V = (C4 Xor C3) = (0 Xor 0) = 0 Thus, the sum is V is 0 and C4 = C is 0. To verify my results, the last five inputs and outputs are these equations. As you can see my program verifies that a-e are correct. 3. (10 points) Textbook Problems 4.44: Using a case statement, write an HDL behavioral description of a eight-bit arithmetic logic unit (ALU). The circuit has a three-bit select bus (Sel), sixteen-bit input datapaths (A[15:0] and b[15:0], and eight-bit output datapath (y[15:0]), and performs the arithmetic and logic operations listed below.

5 Sel Operation Description 000 y = 8 b0 001 y = A & B Bitwise AND 010 y = A B Bitwise OR 011 y = A ^ B Bitwise exclusive OR 100 y = ~A Bitwise complement 101 y = A B Subtract 110 y = A + B Add (Assume A and B are unsigned) 111 y = 8 hff Module ALU module ALU(y,A,B,sel); output[15:0] y; input [15:0] A,B; input [2:0] sel; reg [15:0] y; case(sel) 3'b000 : y = 8'b ; 3'b001 : y = A & B; 3'b010 : y = A B; 3'b011 : y = A ^ B; 3'b100 : y = ~A; 3'b101 : y = A - B; 3'b110 : y = A + B; 3'b111 : y = 8'hFF; case Test Bench module ALU_tb; reg[15:0]a; reg[15:0]b; reg[2:0]sel; wire[15:0]y; ALU uut(y,a,b,sel); $display("time\t A[0-15]\t B[0-15]\t sel[0-2] y[0-15]"); $monitor("%g\t %16b %16b %3b %16b",$time,A,B,sel,y); A = 16'b ; B = 16'b ; sel = 3'b000;

6 #200 sel = 3'b001; #200 sel = 3'b010; #200 sel = 3'b011; #200 sel = 3'b100; #200 sel = 3'b101; #200 sel = 3'b110; #200 sel = 3'b111; initial #1600 $finish; Output time A[0-15] B[0-15] sel[0-2] y[0-15] [ @csusb.edu@jb358-0 hw4]$ 4. (20 points) Design a binary sequence detector that detects the sequence 000. Overlap is allowed. You may use either D flip-flops or JK flip-flops. Write a Verilog program to verify your design. State Diagram

7 *Diagram made using DIA software State Table Input Present State Next State Output I Q0 Q1 Q0 Q1 F Simplified State Table Present State Next State Present Output X = 0 X = 1 X = 0 X = 1

8 S0 S1 S0 0 0 S1 S2 S1 0 0 S2 S0 S2 1 0 S0 = 00 S1 = 01 S2 = 10 K-map and Equations D X X 1 D0 = IQ1 + IQ0 D X X 0 D1 = I Q0 Q1 + IQ1 F X X 0 F = I Q0 Module Dff module Dff(output reg Q, Qn, input ck, rst, D); always@(posedge ck, posedge rst) if (rst!= 0) begin Q <= 1'b0; Qn <= 1'b1;

9 else begin Q <= D; Qn <= ~D; Module seqdetect module seqdetect(output F, input ck, input rst, input I); wire [1:0] D; wire [1:0] Q, Qn; assign D[0] = (~I && Q[1]) (I && Q[0]); assign D[1] = ((~I && ~Q[0]) && ~Q[1]) (I && Q[1]); assign F = (~I && Q[0]); Dff D0( Q[0], Qn[0], ck, rst, D[0]); Dff D1( Q[1], Qn[1], ck, rst, D[1]); Test Bench `timescale 1ns/ 1ps module seqdetect_tb; reg ck; reg rst; reg I; wire FO; seqdetect uut(.f(fo),.ck(ck),.rst(rst),.i(i)); $display ("time\t Clk I FO"); $monitor ("%g\t %b %b %b",$time,ck,i,fo); ck = 1'b0; rst = 1'b1; I = 1; #1 rst = 1'b0; #14 I = 0; #21 I = 0; #31 I = 0; #60 I = 1; initial #150 $finish; always #5 ck = ~ck;

10 Output time Clk I FO [ @csusb.edu@jb358-1 hw4]$ ^C Score (55/55) I believe for this homework assignment, I have demonstrated a very good understanding of Verilog and the circuits that needed to be programmed. The adder-subtractor was simple as we have done it many times throughout the class. Question 2 was verified in the last five input/outputs of question 1. Question 3 was also easy as the module simply deped on a case section that would return an output based on what sel was. Each output was verified by hand to ensure that I got the right outputs. The fourth question was a bit trickier, but I was able to work through it. I was able to come up with the state diagram and state table fairly easily, but the Verilog section took some time. However, upon completion you can see from the output, that when 0 is the input it advances to the next state. On the third input of 0, the program detects the state 000 and returns an output of 1. After going over each question many times, I am sure that each answer is fully correct.

CprE 281: Digital Logic

CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Multiplication CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev HW