Chapter 4 (Lect 4) Encoders Multiplexers Three-State Gates More Verilog

Size: px

Start display at page:

Download "Chapter 4 (Lect 4) Encoders Multiplexers Three-State Gates More Verilog"

Jemimah Emma Merritt
6 years ago
Views:

1 Chapter 4 (Lect 4) Encoders Multiplexers Three-State Gates More Verilog

2 Encoder: an encoder is the inverse of a decoder, it has 2 n or fewer input lines and n output lines Recall: 2 4 line decoder Inputs Outputs x y D 0 D 1 D 2 D encoder: Inputs Outputs D 0 D 1 D 2 D 3 x y

3 Encoder: Inputs Outputs D 0 D 1 D 2 D 3 x y D0 D1 D2 D3 x = D 2 + D 3 y = D 1 + D 3 x y Issues: 1. Both outputs are 0, when D 0 is 1 or when all inputs are Only one input can be high at any given time or ambiguity occurs Solution: priority encoder and one additional output

4 Priority Encoder: a priority encoder includes a priority function which acts to ensure if two or more inputs are high at the same time, the input with highest priority will take precedence Inputs Outputs D 0 D 1 D 2 D 3 x y Inputs Outputs D 0 D 1 D 2 D 3 x y V X X

5 Inputs Outputs D 0 D 1 D 2 D 3 x y V X X D 2 D 3 D 0 D x = D 2 D 3 D 0 D y =

6 Priority Encoder: x = D 2 + D 3 y = D 3 + D 1 D 2 V = D 0 + D 1 + D 2 + D 3 D0 V D1 D2 x D3 y Priority Event Alarm 1 Heavy Rain 00 2 Thunderstorm 01 3 Severe Thunderstorm 10 4 Tornado 11

7 Multiplexers: multiplexers (aka MUX, data selector) are combinational circuits that select information from one of multiple inputs, based on the inputs at a set of selection lines, and directs the information to a single output line For 2 n inputs you must have n-selection lines 2 - to - 1 MUX: Selection Line (S) Output (Y) 0 Input line 1 1 Input line 2 I0 I1 Y S I0 I1 MUX Y S Think of the Inputs as two digital signals alternating between high and low

8 Multiplexers: Design 4 - to - 1 MUX with enable E S 0 S 1 Y 0 X X I I I I 3

9 Multiplexers: 4 - to - 1 MUX with enable Input selector for Sound System E S 0 S 1 Output 0 X X Video Video DVD AUX Sel Video 1 Sel Video 2 Sel DVD Sel AUX MUX F S0 S1 E MUX Data Sheet

10 Multiplexers: Combining multiplexers for the purpose of multiple bit selection. Use four A0 B0 MUX Y0 2 - to - 1 multiplexers to select one of two possible 4-bit inputs A1 B1 MUX Y1 A2 B2 MUX Y2 A3 B3 MUX Y3 E S

11 Demultiplexers: Takes information from a single input and directs it to one of multiple outputs. Can be configured from a decoder with the enable acting as the data input line Line in DEMUX D 0 S E Enable as input D 1 S 0 D 2 S 1 D 3

12 Multiplexers: using to implement a Boolean function Consider a XOR function if x and y = 0, or x and y = 1, then F = 0 if x = 0 and y = 1, or x = 1 and y = 0, then F = 1 MUX F

13 Three-State Gate: Is a digital circuit that exhibits three states 1. Normal logic high 2. Normal logic low 3. High impedance state a) Appears as an open circuit, no logic value b) Isolated from other devices connected to its output c) Most commonly used as a buffer X Y Control line 1 Y = X Control 0 Open Circuit Typically used to connect multiple sources to a single line, loading and fan out Issues can be minimized using the high impedance state

14 More on Verilog Gate-Level Modeling: describes a circuit by specifying its logic gates and how they are connected, a textual description of a schematic diagram Dataflow Modeling: is accomplished, for the most part, by using Boolean expressions to describe the combinational logic Behavioral Modeling: most powerful approach used to describe combinational and sequential circuits at a higher level

15 Gate-Level Modeling: Verilog and 4-to-1 Multiplexer module MUX_4_1_Gate (m_out,i,s,e); output m_out; input [0:3] I; input [0:1] S; input E; wire [0:1] S_not; wire [0:3] and_out; not G1 (S_not[0], S[0]), G2 (S_not[1], S[1]); I[0] I[1] I[2] I[3] m_out and G3 (and_out[0], I[0], S_not[0], S_not[1], E), G4 (and_out[1], I[1], S_not[0], S[1], E), G5 (and_out[2], I[2], S[0], S_not[1], E), G6 (and_out[3], I[3], S[0], S[1], E); S[0] S[1] E or G7(m_out, and_out[0], and_out[1], and_out[2], and_out[3]); endmodule

16 Dataflow Modeling: Verilog and 4-to-1 Multiplexer S[0] S[1] E m_out I[0] I[1] I[2] I[3] x x 0 0 module MUX_4_1_DataF (m_out,i,s,e); output m_out; input [0:3] I; input [0:1] S; input E; /*Assign statement (condition)? true expression: (condition)?: true expression: false expression */ assign m_out = endmodule (E&~S[0]&~S[1])? I[0]: (E&~S[0]&S[1])? I[1]: (E&S[0]&~S[1])? I[2]: (E&S[0]&S[1])? I[3]: 0;

17 Behavioral Modeling: Verilog and 4-to-1 Multiplexer module MUX_4_1_Bhav (m_out,i,s); output m_out; // reg type retains its value until a change occurs reg m_out; input [0:3] I; // changed the enable to selection line input [0:2] S; /* procedures inside always block, execute whenever a change occurs in the variables listed after sign */ or S) case(s) 1 : m_out = I[0]; 3 : m_out = I[1]; 5 : m_out = I[2]; 7 : m_out = I[3]; default : m_out = 0; // S = 0,2,4, or 6 endmodule

18 // timing test bench for MUX4_1_Gate module t_mux4_1_gate; wire m_out; reg [0:3] I; reg [0:1] S; reg E; MUX4_1_Gate M1(m_out, I, S, E); initial begin E=1; S=2'b00;I=4'b0000; #10 I=4'b0000; #10 I=4'b1000; #10 E=1; S=2'b01;I=4'b0000; #10 I=4'b0100; #10 I=4'b0000; #10 E=1; S=2'b10;I=4'b0000; #10 I=4'b0010; #10 I=4'b0010; #10 E=1; S=2'b11;I=4'b0001; #10 I=4'b0001; #10 I=4'b0001; #10 E=0; S=2'b00;I=4'b1111; end initial #150 $finish; endmodule Example Test Benches // timing test bench for MUX4_1_DataF module t_mux4_1_dataf; wire m_out; reg [0:3] I; reg [0:1] S; reg E; MUX4_1_DataF M1(m_out, I, S, E); initial begin E=1; S=2'b00;I=4'b0000; #10 I=4'b0000; #10 I=4'b1000; #10 E=1; S=2'b01;I=4'b0000; #10 I=4'b0100; #10 I=4'b0000; #10 E=1; S=2'b10;I=4'b0000; #10 I=4'b0010; #10 I=4'b0010; #10 E=1; S=2'b11;I=4'b0001; #10 I=4'b0001; #10 I=4'b0001; #10 E=0; S=2'b00;I=4'b1111; end initial #150 $finish; endmodule // timing test bench for MUX4_1_Bhav module t_mux4_1_behav; wire m_out; reg [0:3] I; reg [0:2] S; MUX4_1_Behav M1(m_out, I, S); initial begin S=3'b001;I=4'b0000; #10 I=4'b0000; #10 I=4'b1000; #10 S=3'b011;I=4'b0000; #10 I=4'b0100; #10 I=4'b0000; #10 S=3'b101;I=4'b0000; #10 I=4'b0010; #10 I=4'b0010; #10 S=3'b111;I=4'b0001; #10 I=4'b0001; #10 I=4'b0001; #10 S=3'b000;I=4'b1111; end initial #150 $finish; endmodule

19 What you should know 1. The function of an encoder and how to implement 2. The function of an multiplexer and how to implement 3. Why tri-state buffers exist 4. Difference between, gate-level, dataflow, and behavioral models

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan

Combinational Logic. Mantıksal Tasarım BBM231. section instructor: Ufuk Çelikcan Combinational Logic Mantıksal Tasarım BBM23 section instructor: Ufuk Çelikcan Classification. Combinational no memory outputs depends on only the present inputs expressed by Boolean functions 2. Sequential