CITS2016, July6-8,Kunming,China

Size: px

Start display at page:

Download "CITS2016, July6-8,Kunming,China"

Abel Barker
5 years ago
Views:

1 CITS2016, July6-8,Kunming,China yamin/ HoseiUniversity CITS2016 1/28

2 Cube Root AlgorithmsandImplementations Algorithms Digit-by-digit integer restoring Digit-by-digit integer non-restoring Improved implementations Basic implementations Eliminating multiplications Calculating 12q 2 in advance Using carry save adders(csas) Cost/ performance evaluation HoseiUniversity CITS2016 2/28

3 Cube Root Given a radicand d,calculate the cuberoot q sothat d = q 3 + r Ex. 26 = (Weconsideronly d 0) Assumethat dhas 33bits. Then q has 11bits (33/3 bits) r has 24bits atmost d = q 3 + r < (q + 1) 3 = q 3 + 3q 2 + 3q + 1 r 3q 2 + 3q bits Inorderto check the signofthe partial remainder, we use 25 bits during the calculation HoseiUniversity CITS2016 3/28

4 Definitionof PartialCube Root q i b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 q 1 q 2 q 10 q 11 = q Register reg_q stores cube root HoseiUniversity CITS2016 4/28

5 InitialValuesof Registersreg_rand reg_d Shift 3bits d(33-bit) d 1 d 2 d 3 d 4 d 5 d 6... d 32 d 33 Register reg_r (25-bit) Register reg_d (30-bit) Register reg_r stores remainder Register reg_d stores radicand HoseiUniversity CITS2016 5/28

6 BasicRestoringCube Root Algorithm Radicand d = {d 1, d 2, d 3,..., d 33 } = q 3 + r Supposethat wehave gotapartialcuberoot q i andapartial remainder r i suchthat the partialradicand {d 1, d 2,..., d 3i } = q 3 i + r i To calculate b i+1 and r i+1, wehave {d 1, d 2,..., d 3i, d 3i+1, d 3i+2, d 3i+3 } = q 3 i+1 + r i+1 where q i+1 = {q i, b i+1 }or q i+1 = 2q i + b i+1 HoseiUniversity CITS2016 6/28

7 BasicRestoringCube Root Algorithm Let p i = {d 3i+1, d 3i+2, d 3i+3 },then r i+1 = {d 1, d 2,..., d 3i, p i } q 3 i+1 = 8({d 1, d 2,..., d 3i }) + p i q 3 i+1 = 8(q 3 i + r i ) + p i (2q i + b i+1 ) 3 = 8r i + p i (12q 2 i b i+1 + 6q i b 2 i+1 + b 3 i+1) = {r i, p i } (12q 2 i b i+1 + 6q i b 2 i+1 + b 3 i+1) Assume b i+1 = 1 r i+1 = {r i, p i } (12q 2 i + 6q i + 1) HoseiUniversity CITS2016 7/28

8 BasicRestoringCube Root Algorithm r i+1 = {r i, p i } (12q 2 i + 6q i + 1) If r i+1 0, then b i+1 = 1, Otherwise, b i+1 = 0, q i+1 = {q i, 1} q i+1 = {q i, 0} andwe restore r i+1 byadding (12q 2 i + 6q i + 1)tothe negative remainder HoseiUniversity CITS2016 8/28

9 Circuitof RestoringCube Root (Usingmul) clk r i+1 = {r i, p i } (12q 2 i + 6q i + 1) d load 12 6 q 2 q + msb mux mux mux Restoring 3 reg_q reg_r reg_d q r HoseiUniversity CITS2016 9/28

10 Waveformof RestoringCube Root Algorithm Implemented on Altera Cyclone IV E EP4CE115F29C7 160 LEs (logic elements) 72 DFFs(D flip-plops) Two embedded multiplier 9-bit elements Maximum clock frequency: MHz HoseiUniversity CITS /28

11 EliminatingMultiplications Let s i = qi 2 For the case of b i+1 = 0 s i+1 = qi+1 2 = (2q i + 0) 2 = 4qi 2 = 4s i For the case of b i+1 = 1 s i+1 = qi+1 2 = (2q i + 1) 2 = 4qi 2 + 4q i + 1 = 4s i + 4q i + 1 Then r i+1 = {r i, p i } (12qi 2 + 6q i + 1)became r i+1 = ({r i, p i } (8s i + 4s i )) (4q i + 2q i + 1) HoseiUniversity CITS /28

12 Circuitof RestoringCube Root (Nomul) r i+1 = ({r i, p i } (8s i + 4s i )) (4q i + 2q i + 1) clk d load + s12 + q6 + msb mux mux mux mux 3 reg_s reg_q reg_r reg_d s = q 2 q r HoseiUniversity CITS /28

13 Waveformof RestoringCube Root Algorithm Implemented on Altera Cyclone IV E EP4CE115F29C7 220 LEs (logic elements) (160) 92 DFFs(D flip-plops) (72) No embedded multiplier is required (2) Maximum clock frequency: MHz (73.87 MHz) HoseiUniversity CITS /28

14 Calculating 12q 2 inadvance Let w i+1 = 12s i+1 For the case of b i+1 = 0 w i+1 = 12qi+1 2 = 12(2q i + 0) 2 = 48s i For the case of b i+1 = 1 w i+1 = 12qi+1 2 = 12(2q i + 1) 2 = 48s i + 48q i + 12 Thenthe calculation of r i+1 became r i+1 = ({r i, p i } w i ) (4q i + 2q i + 1) HoseiUniversity CITS /28

15 Algorithm1: cube_root_restoring(d, q, r) Input: 33-bitradicand d = {d 1, d 2,..., d 33 } Output: 11-bitcuberoot q = {b 1, b 2,..., b 11 } Output: 24-bit remainder r begin r {0,..., 0, d 1, d 2, d 3 }; /*25bits*/ d {d 4,..., d 33 }; /*30bits*/ q {0,..., 0}; /*11bits*/ s {0,..., 0}; /* s = q 2,22bits*/ w {0,..., 0}; /* w = 12q 2,25bits*/ for i 1 to 11 do /*forbits1to11*/ p = d[29 : 27]; /*3leftmostbitsof d*/ t = (r w) ({q, 0, 1} + {q, 0}); /*rem */ if (t 0) /* rem is non-negative*/ w ({s, 0, 0, 0, 0, 0} + {q, 0, 1, 0, 0, 0}) + ({ s, 0, 0, 0, 0} + { q, 0, 1, 0, 0}); s {s, 0, 0} + {q, 0, 1}; /* {q, 1} 2 */ q {q, 1}; /* b i =1*/ if (i < 11) r {t, p}; /*newr*/ else r t[23 : 0]; /*finalr*/ endif else /*remisnegative*/ w {s, 0, 0, 0, 0, 0} + {s, 0, 0, 0, 0}; s {s, 0, 0}; /* {q, 0} 2 */ q {q, 0}; /* b i =0*/ end endfor if (i < 11) r {r, p}; /*restoringr*/ else r r[23 : 0]; /*finalr*/ endif endif d {d, 0, 0, 0}; /*shift3-bitleft*/ HoseiUniversity CITS /28

16 Circuitof RestoringCube Root (Balanced) r i+1 = ({r i, p i } w i ) (4q i + 2q i + 1) clk d load w0 w1 msb t mux mux mux mux mux 3 reg_w reg_s reg_q reg_r reg_d w = 12q 2 s = q 2 q r HoseiUniversity CITS /28

17 cube_root_restoring.v // Copyright by Yamin Li and Wanming Chu, 2016 module cube_root_restoring ( input [32:0] d, // 33-bit radicand input load, // start input clk, // clock input clrn, // reset output [10:0] q, // 11-bit cube root output [23:0] r, // 24-bit remainder output reg busy, // circuit busy output reg ready); // results ready reg [29:0] reg_d; // register for d reg [10:0] reg_q; // register for q reg [24:0] reg_r; // register for r reg [23:0] reg_w; // register for 12q^2 reg [21:0] reg_s; // register for q^2 reg [3:0] count; // counter for control wire [24:0] rem; // signed remainder HoseiUniversity CITS /28

18 cube_root_restoring.v wire [23:0] w0,w1,w; // for reg_w wire [21:0] rs; // for reg_s wire [24:0] rr; // for reg_r assign w0 = {reg_s[18:0],5 d0} + // 32q^2 {reg_s[19:0],4 d0}; // 16q^2 assign w1 = ({reg_s[18:0],5 d0} + // 32q^2 { 8 d0,reg_q,5 d8})+ // 32q+8 ({reg_s[19:0],4 d0} + // 16q^2 { 9 d0,reg_q,4 d4}); // 16q+4 assign rem = (reg_r - {1 d0,reg_w}) - // r-w ({12 d0,reg_q,2 d0} + // 4q {13 d0,reg_q,1 d1}); // 2q+1 wire b = ~rem[24]; // root bit assign rs = b? {reg_s[19:0],2 d0} + // 4q^2 { 9 d0,reg_q,2 d1} : // 4q+1 {reg_s[19:0],2 d0}; // 4q^2 assign rr = b? { rem[21:0],reg_d[29:27]} : {reg_r[21:0],reg_d[29:27]}; HoseiUniversity CITS /28

19 cube_root_restoring.v assign w = b? w1 : w0; // 12q^2 wire [3:0] count_plus = count + 4 d1; wire counter10 = (count == 4 d10); ( posedge clk or negedge clrn ) begin if (!clrn) begin // on reset, active low busy <= 0; // circuit is not busy ready <= 0; // results are not ready end else begin // not on reset if (load) begin // load radicand d reg_d <= d[29:0]; // 30 bits reg_q <= 0; // q_0=0 reg_r <= {22 d0,d[32:30]}; // r_0 reg_s <= 0; // q^2 reg_w <= 0; // 12q^2 busy <= 1; // circuit is busy ready <= 0; // results are not ready count <= 0; // clear counter end else if (busy) begin // calculating HoseiUniversity CITS /28

20 cube_root_restoring.v reg_d <= {reg_d[26:0],3 d0}; // shift reg_q <= {reg_q[9:0],b}; // shift reg_s <= rs; // q^2 reg_w <= w; // 12q^2 if (counter10) begin // finish busy <= 0; // circuit is idle ready <= 1; // results are ready if (b) reg_r <= rem; // remainder end else begin // not finish reg_r <= rr; end count <= count_plus; // counter++ end end end assign q = reg_q; // final cube root assign r = reg_r[23:0]; // final remainder endmodule HoseiUniversity CITS /28

21 Waveformof RestoringCube Root Algorithm Implemented on Altera Cyclone IV E EP4CE115F29C7 271 LEs (logic elements) (220) 109 DFFs(D flip-plops) (92) No embedded multiplier is required (0) Maximum clock frequency: MHz ( MHz) HoseiUniversity CITS /28

22 UsingCarrySave Adders Two-level carry propagate adders(cpas) to calculate t We canuse the carrysave adders(csas)to speedupit t = {r, p} w 4q 2q 1 = {r, p} + (w + 1) + (4q + 1) + (2q + 1) 1 = {r, p} + w + 4q + 2q We usetwo-levelcsas to performthe additionsandget twonumbers: carry candsum s Thenwe useacpa to getthe temporaryremainder t = 2c + s HoseiUniversity CITS /28

23 UsingCarrySave Adders t = r w 4q 2q 1 r w q = r + w + 4q + 2q CSA CSA CSA CSA CSA CSA CSA 1 CSA CSA CSA CSA CSA CSA CSA 1 CPA t [24] t[13] t[12] t[11] t[2] t[1] t[0] HoseiUniversity CITS /28

24 Waveformof RestoringCube Root Algorithm Implemented on Altera Cyclone IV E EP4CE115F29C7 298 LEs (logic elements) (271) 109 DFFs(D flip-plops) (109) No embedded multiplier is required (0) Maximum clock frequency: MHz ( MHz) HoseiUniversity CITS /28

25 Non-RestoringCube Root Algorithms Inrestoringalgorithm,if r i < 0, r i is restoredbyadding (12q 2 i 1 + 6q i 1 + 1)to r i Thenwe perform r i+1 = {r i, p i } (12q 2 i + 6q i + 1) Because q i = {q i 1, 0}or q i 1 = q i /2, wehave r i+1 = (8(r i + 12q 2 i 1 + 6q i 1 + 1) + p i ) (12q 2 i + 6q i + 1) = (8r i + 24q 2 i + 24q i p i ) (12q 2 i + 6q i + 1) = {r i, p i } + 12q 2 i + 18q i + 7 Non-restoring cube root algorithm r i+1 = {r i, p i } (12q 2 i + 6q i + 1) if r i 0 r i+1 = {r i, p i } + (12q 2 i + 18q i + 7) if r i < 0 HoseiUniversity CITS /28

26 Cost/Performance Evaluation Implementation Frequency Cycle time Latency Logic Reg Mul 1. Restoring (Mul) MHz ns ns Restoring (NoMul) MHz 7.93 ns ns Restoring (Advance) MHz 7.44 ns ns Restoring (CSAs) MHz 6.78 ns ns Non-rest. (Mul) MHz ns ns Non-rest. (NoMul) MHz 8.68 ns ns Non-rest. (Advance) MHz 8.19 ns ns Non-rest. (CSAs) MHz 7.26 ns ns HoseiUniversity CITS /28

27 Cost/Performance Evaluation Clock frequency (MHz) Restoring Non-restoring Mul NoMul Advance CSAs Implementation method Restoring cube root: Speedup CSA = /73.87 = % Non-restoring cube root: Speedup CSA = /77.77 = % Both are lowat cost HoseiUniversity CITS /28

28 FYI: Square Root Algorithms Square Root Algorithms Restoring and non-restoring algorithms Goldschmidt algorithm Newton-Raphson algorithm Refer to Yamin Li, Computer Principles and Design in Verilog HDL, John Wiley& Sons, ISBN , 2015, 550 pages Thank you very much! HoseiUniversity CITS /28

Chapter 6. Synchronous Sequential Circuits

Chapter 6. Synchronous Sequential Circuits Chapter 6 Synchronous Sequential Circuits In a combinational circuit, the values of the outputs are determined solely by the present values of its inputs. In a sequential circuit, the values of the outputs