MSL RAD EVIL L2 trigger FPGA code review

Transcription

1 Title MSL RAD EVIL L2 trigger FPGA code review Institut für Experimentelle und Angewandte Physik Christian Albrechts Universität zu Kiel November, 2007

2 Table of Contents Intro Title Table of Contents Design Code Style Memories Revision Control Simulation Interface Module Reset Algorithms Event Processing L2 trigger Calibration

3 Code Style 100 % synchronous. Single clock ( MHz). Semi-structural coding style. Every sequential cell is explicit in the code. Runs without reset, i.e., all non-nominal state flushes out while processing an event. wire a =... ; reg b ; posedge c l k ) i f (... ) b <=... ; e l s e i f (... ) b <=... ; e l s e b <=... ;

4 Memories The L2 trigger configuration is stored in cells. Calibration and Si-hit configuration is stored in SRAM. Event and trigger counters are stored in SRAM. Two instances of module sram128x32(); 128 words of 32 bits. clk in, ina ine outa oute out

5 Revision Control Revision controlled since December CVS, Concurrent Versions System. // $ I d : l 2 t r i g. v, v /07/ : 2 9 : 2 6 b o t t c h e r Exp $ // // $ Log : l 2 t r i g. v, v $ // R e v i s i o n /07/ : 2 9 : 2 6 b o t t c h e r // minor documentation typo f i x // // R e v i s i o n /07/ : 2 1 : 4 5 b o t t c h e r // r o u n d i n g implemented i n f l o a t 8 // // R e v i s i o n /07/ : 3 6 : 0 9 b o t t c h e r // f i x bug i n esuma : s i g n e d d i f f // // R e v i s i o n /07/ : 4 3 : 5 9 b o t t c h e r // p h a o f f s e t f e a t u r e added

6 Simulation Simulator: Icarus Verilog Waveform viewer: GTKWave v Verilog testjig with: Driver logic and tasks for all input interfaces. Driver logic and monitors for all output interfaces. All I/O is logged to a (text) logfile. The logfile is compared to a (revision controlled) gold file after each run. After changes to the l2trig module, the diff between logfile and goldfile highlights the changed behavior, aiding verification of the change.

7 Module module l 2 t r i g ( c l k, // MHz c l o c k r e s e t, // s y n c h r o n o u s r e s e t Tclk, // Token c l o c k phase Tin, TinE, // L1 token s e r i a l i n p u t and e n a b l e Tout, ToutE, // ADC token s e r i a l output and e n a b l e p r i o r i t y, // p r i o r i t y t r i g g e r d e t e c t e d n c h a n n e l s, // number o f c h a n n l e s to d i g i t i z e data, // ADC data comes i n h e r e datae, // when s t r o b e d h e r e. Fout, FoutE, // FIFO output and e n a b l e FoutBusy, // U n f i n i s h e d p a c k e t C i n i, // C o n f i g u r a t i o n i n p u t CinAi, C i n E i // C o n f i g u r a t i o n a d d r e s s, e n a b l e ) ;

8 Reset wire Reset = r e s e t CinE & ( CinA == 0 ) ; The reset is affecting registers that do not come out clean from unknown state during simulation, or that may cause spurious output before they settle down in a quiescent state. No reset is required to recover the l2trig module from arbitrarily corrupted states. The reset puts the l2trig module immediately into nominal idle state.

9 Event Processing Tin phase Serially receive VIRENA slow tokens. Count each slow token. Evaluate trigger conditions, priority. Count event (priority). Count matched triggers. Tout phase Serially send VIRENA readout tokens. Send event packet header to FIFO. Count event (priority). Count matched triggers. Fetch first set of calibration constants. Digitization phase Receive -bit ADC result. Calculate the energy. Convert ADC value to floating point. Perform gain selection. Send channel data to FIFO. Fetch next set of calibration constants.

10 L2 trigger 16x Tsel00 Tsel00 clk Tsel01 Tsel02 Tsel03 Tsel04 Tsel01 Tsel02 Tsel03 Tsel04 Tclk TinE ToutE token_schedule sel_out sel_in Tsel05 Tsel06 Tsel07 Tsel08 Tsel09 Tsel10 Tsel11 Tsel12 Tsel13 Tsel Tsel15 Tsel16 Tsel17 Tsel18 Tsel19 Tsel20 Tsel21 Tsel22 Tsel23 Tsel Tsel25 Tsel26 Tsel27 Tsel28 Tsel29 Tsel30 Tsel31 Tsel05 Tsel06 Tsel07 Tsel08 Tsel09 Tsel10 Tsel11 Tsel12 Tsel13 Tsel Tsel15 Tsel16 Tsel17 Tsel18 Tsel19 Tsel20 Tsel21 Tsel22 Tsel23 Tsel Tsel25 Tsel26 Tsel27 Tsel28 Tsel29 Tsel30 Tsel31 mask value trigger_configuration_register readout pri[.] priority Tin start_in Tout J Q K Q too[.] l2_token

11 L2 trigger clk TinE Tin Tclk start stop VIRENA channels are numbered 0 to 35. Channels 0 and 35 are unused edge-channels. Channels 1 to 34 are connected to 17 RSH outputs. Every RSH output is connected to two adjacent VIRENA channels. Multiple RSH channels belonging to the same detector are connected with the higher gains at higher numbered channels. The VIRENA tokens are serially shifted highest number first, i.e., 35 downto 0. The L2 trigger relies on getting high-gain first, to selectively read out channels from triggered detectors. For digitization, the VIRENA multiplexer delivers the output voltage of the lowest numbered channel first. The gain selection relies on seeing the low-gain channels of each detector first.

12 2 Calibration Calibration Constants (128 bits) phaoffset offset scale scale exp overflow underflow eshift usithr lsithr first 8 CMP CMP 8 8 ADC CMP CMP exp mant 12 EN FP 8 bit 8 + 2,4,8 MUX REG PHA kev overflow nndiff D_keV Si_Hit underflow Verilog modules calibrate () and gainselect ().

13 Calibration Sync (0x35) Packet Type (0x00) Sync (0xED) Packet Length (12+8*n bytes) VIRENA Readout Tokens unused, zero VIRENA Slow Tokens nchannels L2 Triggers O U S PHA ndiff Channel Energy Detector Energy Five byte EVIL packet header, type 0. Twelve byte event header. Eight bytes per readout channel. The number of read channels appears three times: 1. Packet length. 2. Explicit number in the event header. 3. Number of bits set in the VIRENA readout tokens.