CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3 Solutions

Transcription

1 CSEE W3827 Fundamentals of Computer Systems Homework Assignment 3 Solutions Prof. Martha A. Kim Columbia University Due October 10, 2013 at 10:10 AM Write your name and UNI on your solutions Show your work for each problem; we are more interested in how you get the answer than whether you get the right answer.

2 1. (10 pts.) Draw the bubble and arc diagram for the clock divider shown below. CLK n PRE D CLR CLK o t RST CLK o t = 0 CLK o t = 1

3 2. (10 pts.) Draw a schematic for an 32-bit up/down counter, using any combinational blocks you wish (except for a counter). Given two inputs NC and DEC, and the current value Q 31:0, your counter should behave as specified in the table below. The superscript + denotes the next value. For this problem, you may ignore any reset signal. NC DEC Q + 31:0 0 0 Q 31:0 1 0 Q 31: Q 31: Q 31: D 31:0 Q 31:0 Q DEC INC CLK

4 3. (20 pts.) Examine the state transition diagram below. It specifies the behavior of a four-input round robin arbiter. Each input gets a turn, and if there is a request on input (R = 1) during s turn, the arbiter grants access to that input (GRANT = 1; SEL = ). R 0 /GRANT = 0; SEL = XX TURN 0 TURN 1 R 0 /GRANT = 1; SEL = 00 R3/GRANT = 0; SEL = XX R3/GRANT = 1; SEL = 11 R 2 /GRANT = 1; SEL = 10 R1/GRANT = 1; SEL = 01 R1/GRANT = 0; SEL = XX TURN 3 TURN 2 R 2 /GRANT = 0; SEL = XX

5 (a) (10 pts.) Give expressions for the next state logic (D 1 and D 0 ) and output logic (GRANT and SEL 1:0 ) using the state encoding below. State Q 1 Q 0 TURN TURN TURN TURN Q 1 Q 0 D 1 D D 1 = Q 1 Q 0 D 0 = Q 0 GRANT = Q 1 Q 0 R 0 + Q 1 Q 0 R 1 + Q 1 Q 0 R 2 + Q 1 Q 0 R 3 SEL 1 = Q 1 SEL 0 = Q 0

6 (b) (10 pts.) Give expressions for the next state logic (D 3, D 2, D 1 and D 0 ) and output logic (GRANT and SEL 1:0 ) using the state encoding below. State Q 3 Q 2 Q 1 Q 0 TURN TURN TURN TURN D 0 = Q 3 D 1 = Q 0 D 2 = Q 1 D 3 = Q 2 GRANT = Q 0 R 0 + Q 1 R 1 + Q 2 R 2 + Q 3 R 3 Q 3 Q 2 Q 1 Q 0 SEL 1 SEL SEL 1 = Q 2 + Q 3 SEL 0 = Q 1 + Q 3

7 4. (30 pts.) In this problem you will implement a two-entry queue controller. The queue can hold up to two entries, and supports both enqueue and dequeue operations. The controller FSM, which you will implement, has the following interface and behavior: Input E is 1 bit indicating an enqueue operation. Input D is 1 bit indicating a dequeue operation. Input CLK, has the usual behavior. Input RST resets the controller to the initial state where the queue is empty. Output ERR, is 1 bit indicating whether or not there has been an error in the operation of the queue. Any attempt to enqueue to a full queue, dequeue from an empty queue, or enqueue and dequeue simultaneously cause ERR = 1. After an error the only way to resume normal operation is via a reset. Output CE, for can enqueue, is a 1 bit signal indicating that it is safe to enqueue. Output CD, for can dequeue, is a 1 bit signal indicating that it is safe to dequeue. When ERR = 1, both CD and CE are don t cares.

8 (a) (10 pts.) Draw a bubble and arc diagram for a Moore machine implementation of the queue controller, using the following four states HAS 0,HAS 1,HAS 2 indicating the number of entries in the queue, i.e., in HAS 0 state the queue is empty. ERR is the error state E D E D E D ED ED HAS 0 HAS 1 HAS 2 CE = 1 CD = 0 ERR = 0 ED CE = 1 CD = 1 ERR = 0 ED CE = 0 CD = 1 ERR = 0 D ED E ERR CE = X CD = X ERR = 1

9 (b) (10 pts.) Using the state encoding shown below, give minimal expressions for the output logic, CE, CD, ERR State Q 1 Q 0 HAS HAS HAS ERR 1 1 Q 1 Q 0 CE CD ERR X X 1 CE = Q 1 CD = Q 1 + Q 0 ERR = Q 1 Q 0

10 (c) (10 pts.) Using the same state encoding, give minimal expressions for the next state logic. Curr. State Q 1 Q 0 E D Next State D 1 D 0 HAS HAS HAS ERR 1 1 HAS HAS HAS ERR 1 1 HAS HAS HAS HAS HAS HAS HAS ERR 1 1 HAS HAS HAS HAS HAS ERR 1 1 HAS ERR 1 1 ERR ERR 1 1 ERR ERR 1 1 ERR ERR 1 1 ERR ERR 1 1

11 E D Q 1 Q D 1 = Q 1 Q 0 + Q 0 E + Q 1 D + ED + Q 0 Q 1 D E D Q 1 Q D 0 = Q 1 Q 0 + ED + Q 0 D + Q 0 E + E DQ 0

12 5. (30 pts.) Consider a subway turnstile that is either locked or unlocked. When locked, nobody can pass through the turnstile, except by inserting a coin, to unlock it. When unlocked, one person can push on the crossbar and pass through, at which point the turnstile becomes locked again. Three attempts to push on a locked turnstile will trigger an alarm. Inserting a coin when the turnstile is already unlocked will cause the turnstile to stay unlocked until one person has passed. In other words, inserting two coins will allow only one person to pass through, not two. Once an alarm has sounded, only a reset will stop it. The controller for this turnstile accepts two inputs push (P) and coin (C) as well as clock (CLK) and reset (RST). The outputs indicate whether the turnstile is locked (L) and whether or not the alarm should be sounding (A).

13 (a) (10 pts.) Draw the state transition diagram for a Moore implementation of this turnstile. LOCKED 0 L = 1 A = 0 P P C LOCKED 1 L = 1 A = 0 C UNLOCKED L = 0 A = 0 C P C LOCKED 2 L = 1 A = 0 P ALARM L = 1 A = 1

14 (b) (0 pts.) Pick a state encoding for the turnstile FSM. State Q L0 Q L1 Q L2 Q U Q A LOCKED LOCKED LOCKED UNLOCKED ALARM

15 (c) (10 pts.) Give expressions for the next state logic of the turnstile FSM. D L0 = Q U P D L1 = Q L0 P D L2 = Q L1 P D A = Q A D U = (Q L0 + Q L1 + Q L2 + Q U )C Also, RST must be wired to preset Q L0 and clear Q L1, Q L2, Q A, and Q U.

16 (d) (10 pts.) Give expressions for the output logic of the turnstile FSM. L = Q U A = Q A