ECEN 468 Advanced Logic Design

Transcription

1 ECEN 468 Advanced Logic Design Lecture 27: Verilog Delay Models

2 Inertial Delay v Delay is caused by charging and discharging node capacitors in circuit B v Gate delay and wire delay v Pulse rejection o If pulse with is less than delay, the pulse is ignored A C D 2

3 Simulation with Delay A X B C X X A C 3 2 D 13 D X B t sim A = x B = x C = x D = x A = 1 B = 0 C = 0 B = 1 C = 1 A = 0 C = 0 B = 0 D = 1 D = 0 D = 1 3

4 Example of De-scheduling A B C A C 3 2 D D B T_sim A=x B=x C=x D=x A=1 B=0 15 B=1 C=1 D= C=0 D=1 A=0 C=1 4

5 Options for Delay Specifications Logic value before transition Logic value after transition 0 1 x z 0 dr d* dz 1 df d* dz x df dr d** z df dr d* v dr = rising delay, df = falling delay, dz = turnoff delay v If 2 delays are specified o d* = d** = min ( dr, df ) v If 3 delays are specified o d* = min( dr, df, dz ), d** = dz 5

6 Net Delay wire #2 y_tran; and #3 (y_tran, x1, x2); buf #1 (buf_out, y_tran); and #3 (y_inertial, x1, x2); x1 x2 y_inertial x1 x2 y_tran y_inertial buf_out y_tran buf_out

7 Examples of Net Delay module xor1( y, a, b ); input a, b; output y; parameter delay = 5; assign #delay y = a ^ b; endmodule module xor2( y, a, b ); input a, b; output y; wire #5 y; module xor3( y, a, b ); input a, b; output y; parameter wire_delay = 5; parameter gate_delay =3; wire #wire_delay y; assign #gate_delay y = a ^ b; endmodule assign y = a ^ b; endmodule 7

8 Module Delays and Paths v In structural description, module delays can be obtained by tracing gate and net delays v In behavioral description, module paths can be described separately to allow delay descriptions 8

9 Module Paths v Simple module paths o Unconditional direct input to output path v State-dependent paths o Exists when certain condition is satisfied o Describe transparent latch v Edge-dependent paths o Exists for a synchronizing signal o Describe edge-triggered flip-flop 9

10 Simple Module Path Parallel paths, => Full connection paths, *> v Source of path must be a net declared as input or output v Destination of path must be a net or reg declared as output or inout 10

11 Example of Simple Module Path Delay module nand1( out, A, B ); output out; input A, B; nand ( out, A, B ); A B out specify ( A,B *> out ) = ( 15, 14, 11, 10, 16,15 ); // 0->1, 1->0, 0->z, z->1, 1->z, z->0 endspecify endmodule Specify blocks declare paths Its path can override structural delays 11

12 Edge-Sensitive Paths module edge_ff ( clock, data, clear, preset, q ); input clock, data, clear, preset; output q; specify specparam t_rise_clk_q = 100; t_fall_clk_q = 120; t_rise_ctl_q = 50; t_fall_ctl_q = 60; ( posedge clock *> (q:data) ) = ( t_rise_clk_q, t_fall_clk_q ); ( clear, preset *> q ) = ( t_rise_ctl_q, t_fall_ctl_q ); endspecify endmodule 12

13 State-Dependent Paths specify if ( enable ) ( data *> q ) = ( t_rise_clk_q, t_fall_clk_q ); endspecify specify if (!set &&!clear ) ( posedge clock *> ( q:data )) = ( t_rise_clk_q, t_fall_clk_q ); endspecify 13

14 Path Polarity Specify whether a transition at output of a path has the same direction (rising or falling) as the input ( siga +*> q1 ) = delay_to_q1; // positive path polarity ( sigb -*> q2 ) = delay_to_q2; // negative path polarity ( sigc *> q3 ) = delay_to_q3; // unknown polarity 14

15 Specify Block Parameters module nand1 ( O, A, B ); input A, B; output O; nand ( O, A, B ); specify specparam T01 = 1.13:3.09:7.75; T10 = 0.93:2.50:7.34; ( A=>O ) = ( T01, T10 ); ( B=>O ) = ( T01, T10 ); endspecify endmodule Local to specify block 15

16 Specify Pulse Width module nand1 ( O, A, B ); input A, B; output O; nand ( O, A, B ); specify specparam T01 = 1.13:3.09:7.75; T10 = 0.93:2.50:7.34; ( A=>O ) = ( T01, T10 ); ( B=>O ) = ( T01, T10 ); pathpulse$ ( : : ); endspecify endmodule Specify inertial delays 16

17 Pulse Reject Limit and Error Limit specify ( clk => q ) = 10; ( data => q ) = 7; ( clr, preset *> q ) = 3; specparam pathpulse$ clk$q = ( 3, 8 ); pathpulse$ clr$q = ( 0, 5 ); pathpulse$ = 4; endspecify Reject limit Error limit Single value for both reject and error For any other paths not specified If pulse_width < reject_limit, pulse is rejected If reject_limit < pulse_width < error_limit, x is at output If error_limit < pulse_width, signal is transported to output 17

18 SYSTEM TASKS FOR TIMING CHECKS 18

19 Setup Time Constraint v $setup(data, posedge clock, 5); v It specifies an interval before the active edge of clock v Data must arrive before the interval clock 5 5 data 19

20 Hold Time Constraint v $hold(data, posedge clock, 2); v It specifies an interval after the active edge of clock v Data must be stable in the interval clock 2 2 data 20

21 Setup and Hold Time v $setuphold(data, posedge clock, 5, 2); clock data 21

22 Signal Period v $period(posedge clock, t_limit); v Signal period must be sufficiently long clock cycle time clock t_limit 22

23 Pulse Width v $width(posedge clock, t_mpw); v The width of the clock pulse must not be too small clock pulse width clock t_mpw 23

24 Clock Skew v $skew(negedge clk1, negedge clk2, t_skew); v Signal skew is the arriving time difference of two clock signals v Clock skew should be limited clk1 clk2 skew 24

25 Recovery Time v $recovery(negedge bus_control, bus_driver, t_rec); v Time to go from Z to 0 or 1 Bus_control Bus_driver Z t_rec 25

26 No Signal Change v $nochange(posedge clk, data, -5, 2); v Equivalent to o $setuphold(data, posedge clk, 5, 2); 26

27 Finer-grain and Conditional Events Timing Check $setup ( data, edge 01 clk, 5 ); $hold ( data, edge 10 clk, 2 ); $setup ( data, posedge clk &&& (!reset), 4 ); 27