Menu. Part 2 of 3701: Sequential Digital Machines Latches and Flip-Flops: >S-R latches >D latches >T latches. Comb. n. Logic. m Q.

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1 Menu Part 2 of 3701: equential Digital Machines Latches and Flip-Flops: >- latches >D latches >T latches Look into my... 1 Topic 2 : equential Digital Machines or equential Logic LID from Lecture #2 X Comb. n Logic m Network + Y k Memory k ach is called a state a summary of the past or historical behavior. Y = F(,X) There are m equations or m scalar functions. + = G(,X) There are k equations or k scalar functions. 2 1

2 equential Logic and Memory General Model + = F(,X) Y = G(,X) Observation: All circuits so far have had no feedback. What happens if we add feedback? >f 20MHz >We call this a un-gated oscillator or clock >Z turns on & off >Go to LogicWorks (stick/unstick) X Combinational Y Logic + Memory Z = H L H L Z = L H L H Z 3_Nots.cct t Z 3 Consider what happens if we replace the first Level-hifter with a NAND gate We call this a gated- oscillator or clock X turns it on & off >Go to LogicWorks Note that the circuit is stable! What if we connect the following circuit Gated-Oscillators X Y When X=1 t Z Y Gated_Osc.cct 4 2

3 Latch: The Beginning Consider the following circuit: K-Map for z 1 (everything active-high) /x 1 z 1 = /x 1 + x 0 z 1 x 0 z 1.cct Tracing through the circuit: z 1 x 0 x 1 z 0 z 1 z 0 z 1 L L L H H H H L L H H L L H L H H L H L H H H L H L L H H H L H H L H L H H L L H H H H L H This device is called a latch or Flip- Flop. It flip flops between 2 states. 5 Latch Interpretations If we change the names of this device, we can better relate it to our model. Below makes sense except when x 0 and x 1 are both false (L). x 0 z 0 x 0 + z 1+ = /x 1 + x 0 z 1 x 1 z 1 x 1 + A better interpretation: Noticing that x 1 (H)=L sets the device (z 1 =H, =1) and x 0 (H)=L resets the device (z 1 =L, =0 when x 1 (H)=1=H), we can call: >x 0 (H) /x 0 (L)=(L) x 1 (H) /x 1 (L)=(L) z 1 (H) (H) Demonstrate latch in LogicWorks _circuit.cct + = + / 6 3

4 - Latch edrawing the latch circuit (and choosing z 0 to as the active-low output and z 1 as the active-high output); and are the active-low inputs:.cct 7 - Latch Using a truth table >When ( = 1) ( = 1), (H)=1 & (L)=0 These are a contradictions. No Boolean variable can be like this! What if & switch states (from 0 1 to 1 0, or from 1 0 to 0 1) but not simultaneously (so 1 1 for some time)? (eal life) Answer: The next state is uncertain! Convention: The case where =1 & = 1 simultaneously is forbidden!! Thus, when =1 is forbidden we still get : + = + / (L) (H) (L) (H) / 8 4

5 - Latch + = + / edrawing this circuit using mixed-logic we have the traditional form:.cct (L) (H) (L) (L) 9 NO ealization of - Previous page has the NAND realization of the - latch: + = + /.cct Move feedback bubbles to outputs (& reverse output active levels): emove input bubbles; change activation levels of & : 10 5

6 Feedback and Latches Observation: The feedback latches the signal. ince 1, if = 1 then becomes 1 & it reinforces the input to the gate so that even if becomes 0 the output remains = 1. The same is true when = 1 ( must be 0) & reinforces the state. We note that the changes occur only when and change. This is called an asynchronous or unclocked FF model, but more appropriated this is called a latch. Latch Latch 11 Gated-latches Often in digital circuits (e.g., computers) signals change are synchronized to a clock pulse (not necessarily a continuous or oscillator clock). is active-high enable (almost a clock) >This is a third type of enable X X Do it in LogicWorks! _FFa.cct Latch Gated (nabled) Latch 12 6

7 Gated- ince the signal gates the inputs, &, we call this a gated-clock -latch a gated-clock -FF (since it is almost synchronous), or my favorite: a enabled -Latch When we refer to synchronous logic, the ANDing (gating) of the inputs (and therefore outputs) is UNDTOOD >ven though + =f(, ) the is assumed and generally not written in the equation, e.g., + = ( + / ) Adding more functionality to the basic -latch yields other latches and FFs in commercially available configurations Observation: In most synchronous circuits, the clock is a pulse and an edge activates the outputs. The synchronizing clock pulse is often derived from other logic in a circuit. X X 13 with Pre-et/Clear Pre-set/pre-clear inputs: Add these to force the latch to asynchronously et or eset the outputs Pre-et Pre-et X X (L) (H) and can not simultaneously true and can not simultaneously true and Pre-et can not simultaneously true Pre-et and can not simultaneously true Demo in LogicWorks! P PC P PC _FFb.cct 14 7

8 Delay Latch Delay-, Data-, or D-Latch D-Latch + = D + = ( + / )=(D + D ) Pre-et D P PC D D-Latch using -Latch = D(1+)= D Pre-et P PC 15 Toggle-latch or T-latch Toggle Latch - Useful in counters A Toggle or T-FF changes state (no matter what the value of ) when the toggle input is true When T=1, changes 0 1 or from 1 0. When T= 0, holds. Pre-et T T T_latch.cct Gated-Toggle Latch Pre-et (L) (H) 16 8

9 Problem with Gated- or Unclocked- Toggle Latch Problem with this circuit is that if stays on too long (longer than the gate delays), as long as T=1, the circuit will 1/t PD t PD gate propagation delay T_FF.cct T Pre-et (L) (H) eal T-FFs do not have this problem, i.e., they are not designed as above (i.e., no T-latches!) T 17 olution to Gated- or Unclocked-Latch Problem To solve this, we can add a capacitor to differentiate the CLK, and a diode to get rid of the negative blip nable To CLK nable Blip To CLK Blip is the output of the cap (used as a differentiator) The Zener diode chops off the negative part of blip Logic designers want to help you avoid this, (1) They add the capacitor/diode for you O (2) They design edge-only trigger devices O (3) They solve it some other way (digitally) These solutions are built-in by the IC manufacturer 18 9

10 The nd! 19 10