Using the NOT realization from the NAND, we can NOT the output of the NAND gate making it a NOT NOT AND or simply an AND gate.

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Angel Ross
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1 CSC 216 NAND/NOR Equivalents and Flip/Flops Dr. Anthony S. Pyzdrowski 10/28/2016 The NAND gate is a NOT AND gate. It is false when all inputs are true and true otherwise. The NOR gate is a NOT OR gate. It is true when all inputs are false and true otherwise. A B A NAND B A B A NOR B F F T F F T F T T F T F T F T T F F T T F T T F Both the NAND and NOR gates can be used to realize all of the logic operations. If both inputs of the NAND gate, A and B, are the same, i.e. connected together, then there are just two entries of the truth table used, the false, false and the true, true. When both inputs of the NAND gate are false the function is true and when both inputs are true the function is false, this realizes the NOT gate. AB A NAND B F T T F Likewise if both inputs of the NOR gate, A and B, are the same, i.e. connected together, then there are just two entries of the truth table used, the false, false and the true, true. When both inputs of the NOR gate are false the function is true and when both inputs are true the function is false, this realizes the NOT gate. AB A NOR B F T T F Using the NOT realization from the NAND, we can NOT the output of the NAND gate making it a NOT NOT AND or simply an AND gate. A B A NAND B NOT(A NAND B) = A AND B F F T F F T T F T F T F T T F T

2 Using the NOT realization from of the NOR, we can NOT the output of the NOR gate making it a NOT NOT OR or simply an OR gate. A B A NOR B NOT(A NOR B) = A OR B F F T F F T F T T F F T T T F T Using DeMorgan's theorm on the AND gate we have a NOR gate with the inputs NOTted: AB A B By NOTting the inputs of a NOR gate we can realize an AND gate. A B A& B& (NOT A) NOR (NOT B) = A B F F T T F F T T F F T F F T F T T F F T Using DeMorgan's theorem on the OR gate we have a NAND gate with the inputs NOTted: A B AB By NOTting the inputs of a NAND gate we can realize an OR gate. A B A& B& A& NAND B& = A + B F F T T F F T T F T T F F T T T T F F T By NOTting the inputs and the output of a NOR gate we can realize a NAND gate. A B A& B& A& NOR B& NOT(A& NOR B&) = A NAND B F F T T F T F T T F F T T F F T F T T T F F T F

3 By NOTting the inputs and output of a NAND gate we can realize a NOR gate. A B A& B& A& NAND B& NOT(A& NAND B&) = A NOR B F F T T F T F T T F T F T F F T T F T T F F T F NAND NOR AND OR NOT NAND NOR

4 Any circuit can be realized with either all NAND's or all NOR's by substituting the equivalent module for each component in the circuit. Circuit Circuit realized with all NAND's Circuit with all NAND's and NOT-NOT removed Try to realize the same circuit using all NOR's. The S-R Flip/Flop Using two NOR gates and feedback, outputs feed the inputs, we can make a logic device which can store data. In this circuit the output X is A NOR Y, X A Y and the output Y is B NOR X, Y B X Substituting the expression for Y into the first equation we get X A B X and applying DeMorgan's theorem we get X A B X A B X AB A X In order to analyze this equation we must break the feedback line and step time from the old value to the new value. A B old X new X X becomes and remains 0 because both B and X are 0 and &A is X remains 1 since &A X remain X becomes 1 and stays 1 because of &A B is a X becomes and remains 1 because of &A B is a X becomes and remains 0 because of &A is a X becomes and remains 0 because of &A is a X becomes and remains 0 because of &A is a X becomes and remains 0 because of &A is a 0

5 Rename the inputs A and B to R for Reset and S for Set and the output X to Q, q is old Q and Q is new Q. R S q Q' No change in X No change in X X becomes and remains 1, Set X remains 1, Set X remains 0, Reset X becomes and remains 0, Reset 1 1 0? Undefined, can't Reset and Set at the same time 1 1 1? Undefined, can't Reset and Set at the same time This is a SR or Set Reset Flip/Flop R S Q 0 0 q No Change Set Reset 1 1 X Undefined This device can be set, made true, by making the input S true and the input R false. The state can remain set, true, by making both the S and R inputs false. The state can be changed to false by setting the input R true and the input S false. The state can remain reset, false, by making both the S and R inputs false. This device, RS F/F, is a simple storage device. A &S &R F/F can be made using NAND gates in the same configuration as the SR F/F made from NOR Gates. The truth table for the &S &R F/F is: &S &R Q 0 0 X Undefined Set Reset 1 1 q No Change Adding AND gates to the inputs of a SR F/F alows for "clocking" of the device, i.e. the inputs of the F/F are not changed until the inputs of the AND gates become true. Only when the Clock is true will the R and S inputs pass through to the RS F/F. Anytime the Clock is false both the inputs to the RS F/F will be false and the state of the RS F/F will remain unchanged. This is a level Clock. If the Clock input is NOTted, it will become a negative level Clock and the inputs will pass through to the F/F whenever the Clock is false, otherwise the F/F inputs will be false and the state will remain unchanged. By making R = &S of a clocked RS F/F through the use of an inverter, NOT, we create a Data

6 storage unit. Clock S=D R=&S Q q No Change q No Change Reset Set D Q (When clock is true) Adding feedback to the AND gates can resolve the undefined state of the SR F/F. The true-true input results in the state of the Flip/Flop toggling from it's previous state. J K Q (When clock is true) 0 0 q No Change Reset Set 1 1 q' Toggle The last Flip/Flop that we will use is the T F/F. T stands for toggle. Making both J and K inputs equal to each other results in only two input sequences, false-false and true-true, T Q (When clock is true) 0 q No Change 1 q' Toggle There are two additional types of clocks, edge triggered. Unlike the level triggered Clocks which allow the inputs to pass through to the F/F over a period of time which allows the inputs to change while the Clock is true, the edge triggered Clocks only allow the inputs to pass through during the brief instant of time that the level of the Clock changes. There is the positive edge triggered Clock and the negative edge triggered Clock. The inputs will pass through to the F/F on the rising edge of the Clock signal for the positive edge Clock and the inputs will pass through to the F/F on the falling edge of the Clock signal for the negative edge Clock. The period of time the Clock is true is very short compared to the time it takes the other signals in a system to change, think of it as the shutter on your high speed camera.

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