M. Morris Mano Charles R. Kime Pearson Prentice Hall Pearson Education, Inc. Upper Saddle River, New Jersey

Transcription

1 Instructor s Manual for Logic and omputer esign Fundamentals - 3rd Edition - Partial Preliminary Release M. Morris Mano harles R. Kime Pearson Prentice Hall Pearson Education, Inc. Upper Saddle River, New Jersey

2 Inclusion of the name of any product or vendor does not constitute an endorsement by either the authors or Pearson Prentice Hall. ltera and Flex K are trademarks of ltera orporation. GL and PL are trademarks of Lattice Semiconductor orporation. Mentor Graphics, Model Technology, and ModelSim are trademarks of Mentor Graphics orporation. RMUS and RRM are registered trademarks of RMUS, Inc. ilinx and Spartan are registered trademarks of ilinx, Inc. Verilog is a registered trademark of adence esign Systems, Inc. PowerPoint is registered trademark of the Microsoft orporation. 24, 2, 997 Pearson Education, Inc. Pearson Prentice Hall Pearson Education, Inc. Upper Saddle River, NJ 7458 ll rights reserved. No part of this book may be reproduced, in any form or by any means, without permission in writing from the publisher. ISN......

3 P RT 2 PROLEM SOLUTIONS NOTES ON SOLUTIONS:. Legal Notice: This publication is protected by United States copyright laws, and is designed exclusively to assist instructors in teaching their courses. It should not be made available to students, or to anyone except the authorized instructor to whom it was provided by the publisher, and should not be sold by anyone under any circumstances. Publication or widespread dissemination (i.e. dissemination of more than extremely limited extracts within the classroom setting) of any part of this material (such as by posting on the World Wide Web) is not authorized, and any such dissemination will violate the United States copyright laws. In consideration of the authors, your colleagues who do not want their students to have access to these materials, and the publisher, please respect these restrictions. 2. ompanion Website Problem Solutions: The solutions to all problems marked with a * are available to students as well as instructors on the ompanion Website. 3. Problem hallenge: The problems marked with a + are designated as more challenging than the typical problems. 4. Text Errata Notations: Text errata are noted at the ning of a problem if those errata affect either the problem or its solution. These notes indicate only errors identified in the first printing of the 3rd Edition and are expected be removed after the first printing. 5. Solutions Errata: Errata for these solutions will be provided on the ompanion Website in the Errata section. 3

4 HPTER -.* * ecimal, inary, Octal and Hexadecimal Numbers from (6) to (3) ec in Oct Hex E F 48K = 48 2 = 49, 52 its 384M = = 42, 653, 84 its 8G = = 8, 589, 934, 592 its 2 its 2 2 = 495 = 6, 777, its 2 24 ( ) 2 = = 77 (.) 2 = = (.) 2 = = = = ( ) 2 6 = = ( ) 2 23 = = ( ) = = ( ) 2 ( ) 2 = = 23 ( 222) 3 = = 23 ( 33) 4 = = 25 ( 4) 5 = = 53 ( 343) 8 = = 227 4

5 Problem Solutions hapter -7. * ecimal inary Octal Hexadecimal F * a) 7562/8 = /8 => 2 945/8 = 8 +/8 => 8/8 = 4 + 6/8 => 6 4/8 = + 6/8 => 6 /8 = /8 =>.45 8 = 3.6 => = 4.8 => = 6.4 => 6.2x8 = 3.2 => 3 ( ) = ( ) 8 b) ( ) = (792.4) 6 c) (75.75) = (.) 2-9.* a) (673.6) 8 = (.) 2 = (.) 6 b) (E7.) 6 = (.) 2 = (774.54) 8 c) (3.2) 4 = (.) 2 = (64.4) 8 -. a) b) c) x x x 5

6 Problem Solutions hapter -. ) () 2 () 2 = () 2 Partial Quotient = () 2 () 2 () 2 = () 2 Partial Remainder = () 2 () 2 () 2 2) () 2 () 2 = () 2 Partial Quotient = () 2 () 2 () 2 < () 2 Partial Remainder = () 2 () 2 3) () 2 () 2 = () 2 Partial Quotient = () 2 () 2 () 2 < () 2 Partial Remainder = () 2 () 2 4) () 2 () 2 = () 2 Partial Quotient = () 2 () 2 () 2 = () 2 () 2 Partial Remainder = () 2 < () 2 lgorithm stops. (Partial Remainder < ivisor) Quotient = Partial Quotients = () 2 Remainder = Final Partial Remainder = () 2-2. a) E F G H I J b) 23/2 = + 3/2 => 3 /2 = 5 + /2 => 5/2 = 5/2 => 5 (23) = (53) 2 c) ( H.G) = = * a) (EE) r = (2699) r r + 4 r = 2699 r r 2685 = y the quadratic equation: r = 5 or 6.27 NSWER: r = 5 b) (365) r = (94) 3 r r + 5 r = 94 3 r r 89 = y the quadratic equation: r = 9 or 7 NSWER: r = 7 6

7 Problem Solutions hapter -4. Noting the order of operations, first add (35) r and (24) r ( 35) r = 3 r + 5 r ( 24) r = 2 r + 4 r ( 35) r + ( 24) r = 5 r + 9 r Now, multiply the result by (2) r ( 2 r + r ) ( 5 r + 9 r ) = r r + 9 Next, set the result equal to (5) r and reorganize. r r + 9 = r r 2 + r r 3 5 r 2 23 r 8 r = Finally, find the roots of this cubic polynomial. Solutions are: r = 8, , NSWER: The chicken has 4 toes on each foot (half of 8). -5.* (694) = ( ) (835) = ( ) * a) ( ) = (4867) = () 2 b) (. ) = (378.75) = (.) inary Numbers from (6) to (3) with Odd and Even Parity ecimal Odd Even Gray ode for Hexadecimal igits Hex E F Gray 7

8 Problem Solutions hapter -9. The percentage of power consumed by the Gray code counter compared to a binary code counter equals: Number of bit changes using Gray code Number of bit changes using binary code s shown in table -4, and by definition, the number of bit changes per cycle of an n-bit Gray code counter is per count = 2 n. Number of bit changes using Gray code = 2 n For a binary counter, notice that the least significant bit changes on every increment. The second least significant bit changes on every other increment. The third digit changes on every fourth increment of the counter, and so on. s shown in Table -4, the most significant digit changes twice per cycle of the binary counter. Number of bit changes using binary code = 2 n + 2 n n = 2 i 2 i i = n = = ( 2( n + ) ) = 2 n i = % Power = n 2 ( n + ) 2 From Table -4, complementing the 6th bit will switch an uppercase letter to a lower case letter and vice versa. -2. a) The name used is rent M. Ledvina. n alternative answer: use both upper and lower case letters. R E N T (SP) M. (SP) L E V I N b) -22. NSWER: John oe 8

9 Problem Solutions hapter -23.* a) () 2 b) ( ) c) SII -24. a) b) c) 2 32 = 4,294,967,296 Integers 32 its ( igit) ( 4its) = 8igits = 8 =,, Integers 32 its ( igit) ( 8 its) = 4 igits = 4 =, Integers 9

10 Problem Solutions hapter

11 HPTER 2 2-.* a) YZ = + Y + Z Verification of emorgan s Theorem Y Z YZ YZ +Y+Z b) + YZ = ( + Y) ( + Z) The Second istributive Law Y Z YZ +YZ +Y +Z (+Y)(+Z) c) Y + YZ + Z = Y + YZ + Z Y Z Y YZ Z Y+YZ+Z Y YZ Z Y+YZ+Z 2-2.* a) Y + Y + Y = + Y = ( Y + Y) + ( Y + Y) = Y ( + Y) + Y ( + ) = + Y

12 Problem Solutions hapter 2 b) = = ( + ) + ( + ) = ( + ) + ( + ) = + = c) Y + Z + Y = + Y + Z = Y + Y + Z = ( Y + ) ( Y + Y) + Z = Y + + Z = Y + ( + ) ( + Z) = + Y + Z d) Y + YZ + Z + Y + YZ = Y + Z + YZ = Y + YZ( + ) + Z + Y + YZ = Y + YZ + YZ + Z + Y + YZ = Y( + Z) + YZ + Z + Y + YZ = Y + Z( + Y) + Y + YZ = Y + Z + Y( Z + Z) + YZ = Y + Z + YZ + YZ( + ) = Y + Z( + Y) + YZ = Y + Z + YZ a) = + = ( + ) + + +( + ) = + ( + ) + ( + ) + = = = + b) WY + WYZ + WZ + WY = WY + WZ + YZ + YZ = ( WY + WYZ) + ( WYZ + WYZ) + ( WYZ + WYZ) + ( WYZ + WYZ) = ( WY + WYZ) + ( WYZ + WYZ) + ( WYZ + WYZ) + ( WYZ + WYZ) = WY + WZ( Y + Y) + YZ( W + W) + YZ( W + W) = WY + WZ + YZ + YZ c) = ( ) ( ) = = ( + ) ( + ) ( + ) = ( + + ) ( + ) = + = ( ) ( ) 2

13 Problem Solutions hapter Given: =, + = Prove: ( + ) ( + ) ( + ) = = = ( + + ) ( + ) + + = + ( + ) = ( + ) ( ) = ( + ) ( + ) = = ( + + ) Step : efine all elements of the algebra as four bit vectors such as, and : = ( 3, 2,, ) = ( 3, 2,, ) = ( 3, 2,, ) Step 2: efine OR, N and NOT so that they conform to the definitions of N, OR and NOT presented in Table 2-. a) + = is defined such that for all i, i =,...,3, i equals the OR of i and i. b) = is defined such that for all i, i =,...,3, i equals the N of i and i. c) The element is defined such that for =, for all i, i =,...,3, i equals logical. d) The element is defined such that for =, for all i, i =,...,3, i equals logical. e) For any element, is defined such that for all i, i =,...,3, i equals the NOT of i a) b) c) d) e) + + = ( + ) + + = + ( + ) + = + + ( + ) = + + ( + ) ( + ) = ( + ) = + = ( + ) + = + ( + ) = + = ( + ) + ( + ) = + + = ( + ) + + = + ( + ) + = + + = + = ( + ) ( + + ) ( + + ) = ( + ) ( + + ) = + + = * a) b) c) d) Y + YZ + Y = + YZ = ( + Y) ( + Z) = ( + ) ( + Y) ( + Z) = ( + Y) ( + Z) = + YZ + Y( Z + + Z) = + Y( Z + Z) = + Y( Z + ) ( Z + Z) = + YZ + Y = ( + ) ( + Y) + YZ = + Y + YZ = + Y W( Z + YZ) + W ( + WYZ) = WZ + WYZ + W + WYZ = WZ + WZ + W = W + W = ( + ) ( + ) + = = + + = + + ( ) = + + ( ) = + + 3

14 Problem Solutions hapter a) F = + + b) F = + + = ( + + ) + ( + ) +( + ) = ( + + ) ( + ) ( + ) = ( ) ( ) ( ) 2-9.* 2-.* a) b) c) d) F = ( + ) ( + ) F = (( V + W) + Y)Z F = [ W + + ( Y + Z) ( Y + Z) ][ W+ + YZ + YZ] F = + ( + ) + ( + ) Truth Tables a, b, c Y Z a b W Y Z c a) Sum of Minterms: Product of Maxterms: b) Sum of Minterms: Product of Maxterms: c) Sum of Minterms: Product of Maxterms: YZ + YZ + YZ + YZ ( + Y + Z) ( + Y + Z) ( + Y+ Z) ( + Y + Z) ( + + ) ( + + ) ( + + ) ( + + ) WYZ + WYZ + WYZ + WYZ + WYZ + WYZ + WYZ ( W+ + Y+ Z) ( W + + Y + Z) ( W + + Y + Z) ( W+ + Y+ Z) ( W + + Y + Z) ( W + + Y + Z) ( W+ + Y+ Z) ( W + + Y + Z) ( W + + Y + Z) 2-. a) E = Σm( 256,,, ) = ΠM(, 3, 4, 7), F = Σm( 2467,,, ) = ΠM(,, 3, 5) b) E = Σm( 347,,, ), F = Σm( 35,,, ) c) E + F = Σm( 24567,,,,, ), E F = Σm( 2, 6) d) E = YZ + YZ + YZ + YZ, F = YZ + YZ + YZ + YZ 4

15 Problem Solutions hapter 2 e) E = Z( + Y) + YZ, F = Y( Z + ) + Z 2-2.* a) ( + ) ( + ) = + + = + s.o.p. b) c) = ( + ) p.o.s. + ( + Y) ( Y + Z) = ( + ) ( + ( + Y) ( Y + Z) ) = ( + + Y) ( + Y + Z) p.o.s. = ( + Y) ( + Y + Z) = + Y + Z s.o.p. ( + + ) ( + EF) = ( + + ) ( + + ) ( + + ) ( + EF) = ( + + ) ( + + ) ( + + ) ( + E) ( + F) s.o.p. p.o.s. ( + + ) ( + EF) = ( + EF) + ( + EF) + ( + EF) = + EF + EF + + EF 2-3. a) b) c) W Y W Z Y Z Z Y W Y Y Z W Z W * a) Y b) Y c) d) Z Z Z + Y YZ + Z + Y + + +( or ) a) Y b) c) Z Z + Y + + 5

16 Problem Solutions hapter a) b) c) Y W Z + + YZ + Z + YZ + ( WZ or WY) a) Y b) W Z F = WY + WZ + YZ + WZ F = ( or ) 2-8. * a) b) c) Y Y W Z Z Σm( 3567,,, ) Σm( ,,,,,,, ) Σm(, 2, 6, 7, 8,, 3, 5) 2-9.* a) Prime= ZWZWZ,,, b) Prime =,,,, c) Prime =,,,,, 2-2. Essential = Z, Z Essential =,, Essential =,, a) Prime= YWYYZWZWYYZWZ,,,,,, b) Prime =,,,, Essential = Y Essential =,,, F = Y + ( W Y + YZ + WZ or YZ + WY + WZ) F = c) Prime= ZYYZYZZY,,,,, Essential = none F = ( Z + Y + YZ) or YZ + Z + Y 6

17 Problem Solutions hapter a) F Y b) F W Z 2-22.* a) s.o.p. + + b) s.o.p. + + c) s.o.p. + + ( or ) F = Σm( ,,,,,,, ) F = Σm(, 2, 4, 5, 8,,, 2, 3, 4) F = YZ + WZ + WY F = F = ( Y + Z) ( W + + Z) ( W + + Y) F = ( + ) ( + ) ( + ) ( + + ) p.o.s. ( + ) ( + ) ( + + ) p.o.s. ( + ) ( + ) ( + + ) p.o.s. ( + ) ( + ) ( + + ) a) s.o.p b) s.o.p. Y + WZ + YZ + Z There are several others. or p.o.s. or p.o.s. ( W+ + Y+ Z) ( W+ + Y + Z) ( W + + Y + Z) ( + + ) ( + + ) ( + + ) ( + + ) ( + + ) ( + + ) ( + + ) ( + + ) a) b) Y c) F = + + W Z F = WY + ( YZ + YZ) or (Z + Z) F = 2-25.* a) b) Y c) W Z Primes =,,, Primes = Z, Z, WY, WY, WYZ, WYZ Primes =,,, Essential =,, Essential = Z Essential =, F = + + F = Z + WY + WY F = + + ( or ) 7

18 Problem Solutions hapter a)() F = + ( or ) a)(2) F = + ( or ) F = ( + ) (( + ) or ( + ) b)() Y b)(2) Y W W Z Z F = W Y + W Y Z + W Y F = W Y + W Y + W Z + (W Y or W Y Z or Y Z) + W Y + (W Y or W Y Z) F = (W + + Y)(W + + Y)(W + Z)(W + + Y) ((W + + Y) or (W + Y + Z)) a) F = = 2 = F = = ( + 2 )( + ) 3 = + F = ( + 2 ) F b) F = WY + Y + WZ + WZ Y = ( W + )Y + ( W + W)Z = ( W + )Y + ( W+ ) ( W+ )Z = W+ F = Y + ( W+ )Z W Z F a) F b) G F = + + G = + + = + ( + ) = + ( + ) + = 2 = + = + ( + ) F = + 2 G = + 2 8

19 Problem Solutions hapter 2 G F a) F = ( + ) + ( + ) + ( + ) b) T = YZ( W+ ) + YZ( WY + ) = ( + ) ( + ) + ( + ) + ( ( + ) ) = WYZ + YZ + YZ = * Y = Y + Y ual ( Y ) = ual ( Y + Y) = = = ( + Y) ( + Y) Y Y + Y + Y = Y = + ( ) Note that + Y = ( Y) + Y Letting = and Y =, We can observe from the map below or determine algebraically that Y is equal to. For this situation, + Y = ( Y) + Y = ( Y) + = Y So, we can write F (,,, ) = Y = ( ) 9

20 Problem Solutions hapter 2 F a) Y Z H = Y + Z b) Y F = Y + Y a) F = + + b) There are no three-state output conflicts. Necessary to make F = for = = ; otherwise F would be Hi-Z for this combination. 2

21 Problem Solutions hapter (Errata: problem 2-32 should be problem 2-33 ) TG TG TG TG TG F = + + TG TG TG TG 2-35.(Errata: problem 2-33 should be problem 2-34 ) a) For the solution given in Problem 2-34, the output of F is in the Hi-Z state when = and =. b) TG TG TG TG TG F = + + TG TG TG TG TG TG TG 2

22 P RT 2 PROLEM SOLUTIONS NOTES ON SOLUTIONS:. Legal Notice: This publication is protected by United States copyright laws, and is designed exclusively to assist instructors in teaching their courses. It should not be made available to students, or to anyone except the authorized instructor to whom it was provided by the publisher, and should not be sold by anyone under any circumstances. Publication or widespread dissemination (i.e. dissemination of more than extremely limited extracts within the classroom setting) of any part of this material (such as by posting on the World Wide Web) is not authorized, and any such dissemination will violate the United States copyright laws. In consideration of the authors, your colleagues who do not want their students to have access to these materials, and the publisher, please respect these restrictions. 2. ompanion Website Problem Solutions: The solutions to all problems marked with a * are available to students as well as instructors on the ompanion Website. 3. Problem hallenge: The problems marked with a + are designated as more challenging than the typical problems. 4. Text Errata Notations: Text errata are noted at the ning of a problem if those errata affect either the problem or its solution. These notes indicate only errors identified in the first printing of the 3rd Edition and are expected be removed after the first printing. 5. Solutions Errata: Errata for these solutions will be provided on the ompanion Website in the Errata section.

23 HPTER Pearson Education, Inc. Y Z W=Z + YZ Hierarchy Y W Z Hierarchy Y W Z F = (E + E) + E Hierarchy Y W Z Hierarchy Y W Z G = (E + E) Hierarchy Y H Z + Hierarchy Y H Z G = ( + ) + ( + ) = Hierarchy + Y H Z inputs 6 inputs 6 inputs 3-4.* The longest path is from input or..78 ns +.78 ns +.52 ns +.78 ns =.286 ns 2

24 Problem Solutions hapter a) b) c) a) b) Input elay elay.6ns.6ns.6ns.6ns.2ns.2ns.8ns.8ns.8ns.8ns.8ns.8ns c) The values are identical in all cases If the rejection time for inertial delays is greater than the propagation delay, then an output change can occur before it can be predicted whether or not it is to occur due to the rejection time. For example, with a delay of 2 ns and a rejection time of 3 ns, For a 2.5 ns pulse, the initial edge will have already appeared at the output before the 3 ns has elapsed at which whether to reject or not is to be determined. 3

25 Problem Solutions hapter a) The propagation delay is t pd = ( t PHL + t PLH )/2 = (.5 +.)/2 =.75 ns For a positive output pulse, the following actually occurs:.5 ns. ns If the input pulse is narrower than.5 ns, no output pulse occurs so the rejection time is.5 ns. The model projects:.75 ns b) For a negative output pulse, the following actually occurs if the input pulse is narrower than the rejection time: The model projects:. ns.5 ns For the negative pulse, the rejection time should be.75ns (it can t be larger than the propagation delay) to represent that fact that the pulse is not narrower in the output than in the input. The parameters provide a poor model in this situation. 3-9.* P-Logic N-Logic Y NN NOR Y NN NOR Y NN NOR L L H H L H H L H L H L H H L L 3-. Y F = Z + Y + YZ This is the same function as the carry for the full adder. Z 4

26 Problem Solutions hapter 3 3-.* F = W= + = + + Y = ( + ) + ( + ) Z = a) 2 3 Z Z = 2 3 b) There are 2 different functions of Z: Z = 2 3 and Z = GNS YNS RNS GEW YEW REW GNS = + YNS = YNS RNS = + GNS RNS GEW = + YEW = YEW REW = + GEW REW 5

27 Problem Solutions hapter S5 S4 S3 S2 S S S = S = S2 = + S3 = + S4 = + S5 = S2 S S S = S = S2 = W Y Z to W = + + = + Y = Z = 6

28 Problem Solutions hapter a) PS LS RS RR PL LL RL PL = PS LL = PS LS RS + PS LS RR RL = PS LS RS + PS RS RR b) PS PL LS LL RS RR RL 7

29 3-9. a) Problem Solutions hapter 3 a b c d a e f g b) a = b = c = + + d = e = + f = g = c) The following gate input counts include input inverters and share N gates. Total gate inputs for this solutions = 67. Total gate inputs for book solution is 7. This solution is better by 3 gate inputs a) b) c) Part b requires 6 fewer gates. E F G H E F G H 8

30 Problem Solutions hapter E F This design requires an inverter, 2NN, 4NOR, and 2NOR for a total normalized area of = This design requires two inverters, a 2NN, and four 2NOR for a total normalized area of 2 * *.25 = Y T T2 T3 F T = Y T2 = Y T3 = Y F = Y + Y 3-24.*(Errata: Replace equations with F = W and G = W Y + WZ. See Fig. 4- for decoder diagram/table.) F = U U 2U 3U = U + U + 2U + 3U = WY ( + Y+ Y+ Y) = W G = U 2U L 2L = U + 2U + L + 3L = WY ( + Y) + WZ ( + Z) = WY + WZ (Errata: See Fig. 4- for decoder diagram/table.) Upper Lower W Y Z F G 9

31 Problem Solutions hapter G G2 G2 E = G G2 G2 E Y = E Y = E Y2 = E Y3 = E Y4 = E Y5 = E Y6 = E Except for G = and G2 and G2 =, the outputs Y through Y7 are all s. Otherwise, one of Y through Y7 is equal to with all others equal to. The output that is equal to has index i = decimal value of the values of (,,) in binary. E.g., if (,,) = (,,), then Y6 =. Y7 = E G G2_n G2_n Y [] [] [2] [3] [4] [5] [6] [7] W Y Z

32 Problem Solutions hapter 3

33 HPTER 4 24 Pearson Education, Inc. 4-.* a) b) V F 7 F 6 F 5 F 4 F 3 F 2 F F F 7 F 6 F 5 F 4 F 3 F 2 F F 4-2. a) b) V V F 7 F 6 F 5 F 4 F G 7 G 6 G 5 G 4 F 3 F 2 G 3 G 2 F G F G 4-3. a) b) F 2 :8 3: 4 4 7:4 8 3: G F(3:) G(3:) 4 4 7:4 8 3: H 4-4. = ( S S S 2 S 3 S 4 S 5 ) + M S 4 S 3 L = S 2 S V = = ( S S S 2 S 3 S 4 S 5 ) + M S = V M S 5 L V 2

34 Problem Solutions hapter EOER EOER EN EOER 2 EN 3 EOER 2 En 3 EOER 2 En EOER 2 En EOER 2 En

35 Problem Solutions hapter *(Errata: four should be two and 48 should be 32 ) EOER EOER EOER EOER

36 Problem Solutions hapter EN 7 4-.* 3 2 V V = = ( + 2 ) = ( should be decimal ) 9 is the highest priority. ecimal Inputs inary Outputs V 5

37 4-2. I I I 2 I 3 I 4 I 5 I 6 I 7 Problem Solutions hapter 4 a) b) S S S 2 EOER Y S S I I I 2 2 2x MU I 3 3 S 2 S Y 4x MU S S S S I 4 Y 2 3 I 5 I 6 I 7 4x MU S S Y Y 4-3. EOER Y

38 Problem Solutions hapter S S S 2 EOER I I I 2 I 3 Y I 4 I 5 I 6 I 7 I I I 2 I 3 Y I 4 I 5 I 6 I S S EOER 2 3 I I I 2 Y I 3 I I I 2 Y I 3 7

39 Problem Solutions hapter S 2 S S I I I 2 I 3 I 4 Y I 5 I 6 I S 3 EOER I S S S 2 EOER I I 2 I 3 I 4 I 5 Y I 6 I 7 I 8 I (2:) (7:) 8x MU (7:) Y S (2:) (7:) 8x MU (7:) Y S (2:) 2(7:) 8x MU (7:) Y 3 3(7:) (8) (8) 2(8) 3(8) S (2:) 8x MU (7:) Y S (2:) 2xx4 MU S,,,2,3,,,2,3 Y Y Y 2 Y 3 8

40 Problem Solutions hapter * (7:) (2:) 8x MU (7:) Y S (2:) (4:8) (3) 8x MU (6:) Y (7) S (2:) 3 OR gates 4-2. E 2 3 onsider E as the data input and, as the select lines. For a given combination on (, ), the value of E is distributed to the corresponding output. For example for (, ) = (), the value of E appears on 2, while all other outputs have value Y Z EOER F F 2 F EOER F F 2 7 F Y in S S = in = S = in = in S = in = in S = in = in V Y 4 x 2 MU S S () () Y (2) (3) () () Y (2) (3) S 9

41 Problem Solutions hapter F F = F = F = F = F = F = F = F = V 8 x MU S S S Y F 4-25.* F F= F= F= F= V 4 x MU S S Y 2 3 F EOER EN 7 EOER EN 7 F 2

42 Problem Solutions hapter (7:) x 8 ROM ddress 8 (5:8) x 8 ROM ddress 8 EOER EN 256 x 8 ROM ddress 8 8 EN 256 x 8 ROM ddress 8 EN EN x 8 ROM ddress x 8 ROM ddress 8 EN EN x 8 ROM ddress 256 x 8 ROM ddress EN EN (7:) (5:8) 4-28.* IN OUT IN OUT IN OUT IN OUT a) = 8 address bits and 8 + = 9 output bits, 256K 9 b) 64K 6 c) To represent maximum input 9999, 4 output bits are needed, 64K Input Output Y Z 2

43 Problem Solutions hapter PTERMS INPUTS OUTPUTS Y Z Y Y 2 Y Z 3 Y Z 4 Y Z * PTERMS INPUTS OUTPUTS Y Z E F Y 2 Y Z 3 Y 4 Z PTERM INPUTS OUTPUTS W Y Z * ssume 3-input OR gates. PTERM INPUTS

44 4-35. ssume 3-input OR gates. Problem Solutions hapter 4 PTERM INPUTS Y Z YZ YZ 2 Z 3 - Y 4 YZ 5 Y 6 7 Y 8 9 Z Y entity decoder_2_to_4 is port(en: in std_logic; : in std_logic_vector( to ); : out std_logic_vector( to 3)); end decoder_2_to_4;... signal not_: std_logic_vector( to ); g: NOT port map ((), not_()); g: NOT port map ((), not_()); g2: NN3 port map (not_(), not_(), EN, ()); g3: NN3 port map ((), not_(), EN, ()); g4: NN3 port map (not_(), (), EN, (2)); g5: NN3 port map ((), (), E, (3)); 23

45 Problem Solutions hapter * N N N3 N5 N4 N6 f Figure 4-4: Structural VHL escription library ieee; use ieee.std_logic_64.all; entity nand2 is port(in, in2: in std_logic; out : out std_logic); end nand2; architecture concurrent of nand2 is out <= not (in and in2); end architecture; library ieee; use ieee.std_logic_64.all; entity nand3 is port(in, in2, in3 : in std_logic; out : out std_logic); end nand3; architecture concurrent of nand3 is out <= not (in and in2 and in3); end concurrent; library ieee; use ieee.std_logic_64.all; entity nand4 is port(in, in2, in3, in4: in std_logic; out : out std_logic); end nand4; -- The code above this point could be eliminated by using the library, func_prims. library ieee; use ieee.std_logic_64.all; entity fig44 is port(: in std_logic_vector( to 2); f: out std_logic); end fig44; architecture structural_2 of fig44 is component NN2 port(in, in2: in std_logic; out: out std_logic); end component; 24

46 Problem Solutions hapter 4 component NN3 port(in, in2, in3: in std_logic; out: out std_logic); end component; signal T: std_logic_vector( to 4); g: NN2 port map ((),(),T()); g: NN2 port map ((),T(),T()); g2: NN2 port map ((),T(),T(2)); g3: NN3 port map ((2),T(),T(2),T(3)); g4: NN2 port map ((2),T(2),T(4)); g5: NN2 port map (T(3),T(4),f); end structural_2; F = g: NOT_ port map (, x); g: N_2 port map (,, x2); g2: NOR_2 port map (, x, x3); g3: NN_2 port map (x, x3, x4); g4: OR_2 port map (x, x2, x5); g5: N_2 port map (x4, x5, ); g6: N_2 port map (x3, x5, Y); end structural_; = + Y = F G 25

47 Problem Solutions hapter * F <= ( and Z) or ((not Y) and Z); end; library IEEE; use IEEE.std_logic_64.all; entity priority_4 is port ( : in ST_LOGI_VETOR (3 downto ); : out ST_ULOGI_VETOR ( downto ); V: out ST_LOGI ); end priority_4; architecture priority_4_arch of priority_4 is V <= '' when ="" else ''; <= "" when (3) = '' else "" when (2) = '' else "" when () = '' else "" when () = '' else ""; end priority_4_arch; _ g _ ; ntity multiplexer_8_to_ is port(s: in std_logic_vector(2 downto ); : in std_logic_vector(7 downto ); Y: out std_logic); nd multiplexer_8_to_; chitecture function_table of multiplexer_8_to_ is gnal not_s: std_logic_vector( to ); gnal N: std_logic_vector( to 3); egin with S select Y <= () when "" () when "" (2) when "" (3) when "" (4) when "" (5) when "" (6) when "" (7) when "" ''; nd function_table; 26

48 4-46.* Problem Solutions hapter module decoder_2_to_4_st(, EN, ); input [:] ; input EN; output [3:] ; wire [:] not_; not go(not_[], []), g(not_[], []); nand g2([], not_[], not_[], EN), g3([],[], not_[], EN), g4([2], not_[], [], EN), g5([3], [],[], EN); endmodule end structural_; * N N N3 N5 N4 N6 f 27

49 Problem Solutions hapter module circuit_4_5(,,,,, Y); input,,, ; output, Y; wire n, n2, n3, n4, n5; not go(n, ); nand g(n4, n, n3); and g2(n2,, ), g3(, n4, n5), g4(y, n3, n5); or nor g5(n5, n, n2); g6(n3, n, ); endmodule 4-5. module circuit_4_5(, F); input [2:] ; output F; wire [:4] T; nand g(t[],[],[]), g(t[],[],t[]), g2(t[2],[],t[]), g3(t[3],[2],t[],t[2]), g4(t[4],[2],t[2]), g5(f,t[3],t[4]); endmodule 28

50 Problem Solutions hapter F G 4-53.* module circuit_4_53(, Y, Z, F); input, Y, Z; output F; assign F = ( & Z) (Z & ~Y); endmodule module multiplexer_8_to cf_v(s,, Y); input [2:] S; input [7:] ; output Y; assign Y = (S == 3'b)? [] : (S == 3'b)? [] : (S == 3'b)? [2] : (S == 3'b)? [3] : (S == 3'b)? [4] : (S == 3'b)? [5] : (S == 3'b)? [6] : (S == 3'b)? [7] : 'bx ; endmodule 29

51 Problem Solutions hapter module prioencoder_4_to (,, V); input [3:] ; output [:] ; output V; assign V = [] [] [2] [3]; assign [] = [3]? 'b:([2]? 'b:([]? 'b:([]? 'b:'bx))); assign [] = [3]? 'b:([2]? 'b:([]? 'b:([]? 'b:'bx))); endmodule 3

52 P RT 2 PROLEM SOLUTIONS NOTES ON SOLUTIONS:. Legal Notice: This publication is protected by United States copyright laws, and is designed exclusively to assist instructors in teaching their courses. It should not be made available to students, or to anyone except the authorized instructor to whom it was provided by the publisher, and should not be sold by anyone under any circumstances. Publication or widespread dissemination (i.e. dissemination of more than extremely limited extracts within the classroom setting) of any part of this material (such as by posting on the World Wide Web) is not authorized, and any such dissemination will violate the United States copyright laws. In consideration of the authors, your colleagues who do not want their students to have access to these materials, and the publisher, please respect these restrictions. 2. ompanion Website Problem Solutions: The solutions to all problems marked with a * are available to students as well as instructors on the ompanion Website. 3. Problem hallenge: The problems marked with a + are designated as more challenging than the typical problems. 4. Text Errata Notations: Text errata are noted at the ning of a problem if those errata affect either the problem or its solution. These notes indicate only errors identified in the first printing of the 3rd Edition and are expected be removed after the first printing. 5. Solutions Errata: Errata for these solutions will be provided on the ompanion Website in the Errata section.

53 2

54 HPTER *S = = + + S = = + + * 2 = + + *S = * These are the three equations for the outputs. The logic diagram consists of a sum-of-products implementation of these equations. 5-2.* = T 3 + T 2 = T + T 2 = + + = ( + ) + = ( + )( + ) = + + S = T 4 = T T 2 = ( + ) = ( + )( + ) = + S = T 3 T T 4 T * Unsigned s omplement 2 s omplement 5-4. a) b) c) d) = 3

55 Problem Solutions hapter a) b) c) d) Overflow on omplement Overflow on Subtract 5-6.* +36 = - 24 = - 35 = 36 +( 24) + = 2 = 35 - ( 24) + = = 5-7. a) b) c) d) Overflow a) H = b) G = F = + + E = c) H = it in S out it in out S G = F = ( + ) E = ( + + ) S = it in out = it + in it in H out S it in G out S it in F out S E E F G H 4

56 Problem Solutions hapter S 3 S 2 S S 5-. = = S = S S = = ( S) + ( S) + = S + S S + S S = S = S = S S = 2 = S + S + S S = 2 7 = S its 2-6 use regular full adder/subtractor logic. For bit 7, the carry logic is omitted. S F in S out F in S out F in out F in out F in out F in S S S S S 7 S 6 S 5 S 4 S 3 S 2 S S 5-.+ a) = 2 = 3 = S = = P = = G = = = G + P = = S = = P = = G = = 2 = G + P ( G + P ) = + = + S 2 = 2 2 P 2 = 2 G 2 = 3 = G 2 + P 2 ( G + P ( G + P )) = =

57 Problem Solutions hapter 5 a) S 3 = 3 3 P 3 = 3 G 3 = P 3 = P 3 P 2 P P = 3 2 G 3 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G = P -3 G S 3 S 2 S S b) = = 2 = 3 = S = = P = = G = = = G + P = S = P = G = 2 = G + P ( G + P ) = S 2 = 2 2 P 2 = 2 G 2 = 3 = G 2 + P 2 ( G + P ( G + P )) = 2 S 3 = 3 3 P 3 = 3 G 3 = P 3 = P 3 P 2 P P = 3 2 G 3 = G 3 + P 3 G 2 + P 3 P 2 G + P 3 P 2 P G = 3 2 P -3 G S 3 S 2 S S 6

58 Problem Solutions hapter 5 c) 4 = G 3 + P 3 8 = G P = P 4 7 G 3 + P 4 7 P 3 2 = G 8 + P 8 8 = P 8 P 4 7 G 3 + P 8 P 4 7 P 3 6 = G P = P 2 5 P 8 P 4 7 G 3 + P 2 5 P 8 P 4 7 P 3 P 5 = P 3 P 4 7 P 8 P 2 5 G 5 = G P 2 5 G 8 + P 2 5 P 8 G P 2 5 P 8 P 4 7 G 3 = P 2 5 P 8 P 4 7 G in P S in P S in P S in G P S S 2-5 S 8- S 4-7 S -3 6 G -5 P Proceeding from MS to LS: ased on the above, < if i < i ( i i = ) and for all j > i, j = j ( j j + j j = ) = ( ) ( )( ) + ( )( )( + ) 7

59 Problem Solutions hapter in out in out Logic 5-4. In a subtractor, the sum is replaced by the difference and the carry is replaced by the borrow. The borrow at any given point is a only if in the LS direction from that point, <. Only borrow logic is needed to produce, so the difference logic is discarded in contraction.the remaining equation for borrow into the i + position is: r i+ = i i + i r i + i r i for i =,,2,3. r = giving r = When the borrow r 4 =, then <. Thus, = r 4. The resulting circuit using the borrow logic is: i i i i i i r i+ r i r i+ r i r i+ r i = for <, = otherwise. E= for =, E = otherwise. Use the carry logic from problem 5-4 to produce, with the addition of difference logic to find E: i = i i r i = = its -3 use regular subtractor logic. E = 3 2 =

60 Problem Solutions hapter i i i i i i r i+ i r i r i+ i r i r i+ i r i E ircuit iagram: 4 4 S/ ontrol Logic dd/subtract Sign Sub Sign Sub/dd s omplementer dder/subtractor out 4-bit dder S 3 S 2 S S in ontrol Logic Resultorrection Sign Sub orr out Sign 2 s omplementer ontrol Logic Truth Tables S 4 S 3 S 2 S S Inputs Inputs S/ Sign Sign Sub Sub Sign out orr Sign Overflow Sub = S/ Sign Sign orr = Sub out Sign = Sign orr Overflow = Sub out 5-7.* S 4 S 3 S 2 S S a) b) c) d) e) 9

61 Problem Solutions hapter * ddend 4-bit dder out Sum ugend ddend 4-bit dder out Sum ugend 3 2 ddend 4-bit dder out Sum ugend S 7 S 6 S 5 S 4 S 3 S 2 S S ddend 4-bit dder out Sum ugend S 7 S 6 S 5 S 4 S 3 S 2 S S a) b) Q 7 Q 6 Q 5 Q 4 Q 3 Q 2 Q Q R 7 R 6 R 5 R 4 R 3 R 2 R R

62 Problem Solutions hapter * library IEEE; use IEEE.std_logic_64.all; use IEEE.std_logic_unsigned.all; entity ad_sub_4_bit is port (, : in ST_LOGI_VETOR (3 downto ); Sel: in ST_LOGI; S: out ST_LOGI_VETOR (3 downto ); 4: out ST_LOGI ); end ad_sub_4_bit; architecture ad_sub_4_bit_arch of ad_sub_4_bit is signal temp: std_logic_vector(4 downto ); temp <= ('' & ) + ('' & ) when Sel = '' else ('' & ) + not('' & ) + "" when Sel = '' else ""; S <= temp(3 downto ); 4 <= temp(4); end ad_sub_4_bit_arch;

63 Problem Solutions hapter library IEEE; use IEEE.std_logic_64.all; entity PF is port (,, : in ST_LOGI; P, G, S: out ST_LOGI); end PF; architecture PF_arch of PF is P <= xor ; G <= and ; S <= xor xor ; end PF_arch; library IEEE; use IEEE.std_logic_64.all; entity cla_logic is port ( P, G: in ST_LOGI_VETOR(3 downto ); : in ST_LOGI; GG, GP,, 2, 3: out ST_LOGI); end cla_logic; architecture cla_logic_arch of cla_logic is <= G() or (P() and ); 2 <= G() or (P() and G()) or (P() and P() and ); 3 <= G(2) or (P(2) and G()) or (P(2) and P() and G()) or (P(2) and P() and P() and ); GP <= P(3) and P(2) and P() and P(); GG <= G(3) or (P(3) and G(2)) or (P(3) and P(2) and G()) or (P(3) and P(2) and P() and G()); end cla_logic_arch; library IEEE; use IEEE.std_logic_64.all; entity cla_4_bit is port (, : in ST_LOGI_VETOR(3 downto ); : in ST_LOGI; S: out ST_LOGI_VETOR(3 downto ); 4, GG, GP: out ST_LOGI); end cla_4_bit; architecture cla_4_bit_arch of cla_4_bit is component PF port (,, : in ST_LOGI; P, G, S: out ST_LOGI); end component; component cla_logic port ( P, G: in ST_LOGI_VETOR(3 downto ); : in ST_LOGI; GG, GP,, 2, 3: out ST_LOGI); end component; 2

64 Problem Solutions hapter 5 signal P, G: ST_LOGI_VETOR(3 downto ); signal : ST_LOGI_VETOR(3 downto ); bit: PF port map((),(),,p(),g(),s()); bit: PF port map((),(),(),p(),g(),s()); bit2: PF port map((2),(2),(2),p(2),g(2),s(2)); bit3: PF port map((3),(3),(3),p(3),g(3),s(3)); carry_logic: cla_logic port map(p, G,, GG, GP,(), (2), (3)); end cla_4_bit_arch; * 3

65 Problem Solutions hapter / 4-bit dder: ehavioral Verilog escription module adder_4_b_v(,, Sel, S, 4); input[3:], ; input Sel; output[3:] S; output 4; assign {4, S} = Sel? ( - ):( + ); endmodule module PF(,,, P, G, S); input,, ; output P, G, S; assign P= ^ ; assign G= & ; assign S= ( ^ ) ^ ; endmodule module cla_logic (P, G, GG, GP,,, 2, 3) ; input [3:] P, G ; output GG, GP ; input ; output, 2, 3; assign = G[] (P[] & ); assign 2= G[] P[] & G[] P[] & P[] & ; assign 3= G[2] P[2] & G[] P[2] & P[] & G[] P[2] & P[] & P[] & ; assign GP= P[3] & P[2] & P[] & P[]; assign GG= G[3] P[3] & G[2] P[3] & P[2] & G[] P[3] & P[2] & P[] & G[]; endmodule endmodule 4

66 Problem Solutions hapter 5 module cla_4_bit (,,, S, 4, GG,GP); input [3:], ; input ; output [3:] S; output GG, GP; wire[3:] P, G; wire[3:] ; PF bit([],[],,p[],g[],s[]), bit([],[],[],p[],g[],s[]), bit2([2],[2],[2],p[2],g[2],s[2]), bit3([3],[3],[3],p[3],g[3],s[3]); cla_logic logic(p, G, GG, GP,, [], [2], [3]); endmodule 5

67 HPTER S_n R_n Q Q_n ps 2 ns 4 ns 6 ns 8 ns 6-2. S R Q Q_n ps 5 ns ns 5 ns 2 ns 6-3. Q Q_n ps 5 ns ns 5 ns 6-4. (Errata: Flip-flop is master-slave.) a)there are no setup time violations. There is a hold time violation at 28 ns. There is an input combination violation just before 24 ns. b) There are no setup time violations. There is a hold time violation just before 24 ns. There is an input combination violation just before 24 ns. c) There is a setup time violation at 28ns. d) There is a hold time violation at 6ns and a setup time violation at 24ns. 6

68 7 Problem Solutions hapter * 6-7. Y Z 2 3 x/, x/ x/ / / / x/, x/ x/ / / / lock lock Format: Y/Z (x = unspecified) Present state Inputs Next state Output Y Z = = Present state Input Next state State diagram is the combination of the above two diagrams. Present state Inputs Next state Output Q Y Q S /, / /, / /, / /, / Format: Y/S

69 Problem Solutions hapter Present State Input Output Next State 6-9.* / / / x/, / / / / / 3 2 x/, / Format: Y/Z /, / / 6-.* S = R = S = R = Present state Input Next state Output / / Y / / / 2 3 / Format: /Y / / 6-. a) The longest direct path delay is from input through the two OR gates to the output Y. t delay = t pdor + t pdor = 2.ns + 2.ns = 4.ns b) The longest path from an external input to a positive clock edge is from input through the OR gate and the inverter to the FlipFlop. t delay = t pdor + t pd INV + t sff = 2.ns +.5ns +.ns = 3.5ns c) The longest path delay from the positive clock edge is from FlipFlop through the two OR gates to the output Y. t delay = t pdff + t pdor + t pdor = 2.ns + 2.ns + 2.ns = 6.ns d) The longest path delay from positive clock edge to positive clock edge is from FlipFlop through the OR gate and inverter to FlipFlop. 8

70 Problem Solutions hapter 6 t delay = t pdff + t pdor + t pdinv + t sff = 2.ns + 2.ns +.5ns +.ns = 5.5ns e) The maximum frequency is /t delaymax. For this circuit, the longest delay is 6. ns, so the maximum frequency is /5.5 ns = 8.82 MHz a) The longest direct path delay is from input through the four OR gates to the output Y. t delay = t pdor + t pdor + t pdor + t pdor = 2.ns + 2.ns + 2.ns + 2.ns = 8.ns b) The longest path from an external input to a positive clock edge is from input through three OR gates and the inverter to the second FlipFlop. t delay = t pdor + t pdor + t pdor + t pd INV + t sff = 2.ns + 2.ns +2.ns +.5ns +.ns = 7.5ns c) The longest path delay from the positive clock edge is from the first FlipFlop through the four OR gates to the output Y. t delay = t pdff + t pdor + t pdor + t pdor + t pdor = 2.ns + 2.ns + 2.ns + 2.ns + 2.ns =.ns d) The longest path delay from positive clock edge to positive clock edge is from the first FlipFlop through three OR gates and one inverter to the second FlipFlop. t delay = t pdff + t pdor + t pdor + t pdor + t pdinv + t sff = 2.ns + 2.ns + 2.ns + 2.ns +.5ns +.ns = 9.5ns e) The maximum frequency is /t delay-clockedge to clockedge. For this circuit, the longest delay is. ns, so the maximum frequency is /9.5 ns = 5.26 MHz a) S R Reset lock S R Y 9

71 Problem Solutions hapter 6 b) Reset lock Y 6-4.* Present state Input Next state = + + = + Logic diagram not given. 6-5.* Format: Y/Z (x = unspecified) Present state Inputs Next state Output Q(t) Y Q(t+) Z / x/x x/x / / / 6-6. E= / / 2/ 3/ 4/ 5/ 6/ 7/ E= 2

72 Problem Solutions hapter 6 Present state Next State For Input Output 2 E= E= Z The state assignment could be different. E. g., state 7 could be with state. This would permit use of R inputs on the flip-flops for RESET. RESET E S S Z S 2 LK 6-7. E= / / 2/ 3/ 4/ 5/ 6/ 7/ Present state Next State For Input E= Output 2 E= E= Z ssumes for E =, the output remains at. 2

73 22 Problem Solutions hapter LK Z E S S S RESET =/Z=,S= =/ =/Z=,S= Z=,S= =x/ Z=,S= =/ Z=,S= =/ Z=,S= =/Z=,S= =/ Z=,S= =/ =/ Z=,S= Z=, S= =/Z=,S= LK Z S Present state Input Next state Output Z S

74 Problem Solutions hapter (Errata: Last two bits of NRSI Message: change "" to "") = / Z= = / Z= = / Z= Present Next state Input state Output = / Z= Z LK R RESET Z = / Z= = / Z= = / Z= Present state Input Next state Output = / Z= Z Z LK R RESET 6-2. Format: R/E (x = unspecified) xx/ / x/ / x/ x/ x/ / / Reset / / / / 23

75 24 Problem Solutions hapter * 6-24.* Present state Inputs Next state Output R E Present state Inputs Next state Output R E x/ / / x/ x/ Present state Input Next state Output Y Z Format: Y/Z (x = unspecified) Y lock S R Q Q No hange Reset Set Set a),,,, Format: SR b)

76 Problem Solutions hapter 6 c) Present state Input Next state Q S R Q(t+) x x x x x = S = SR S R S R lock Q 6-25.(Errata: hange state table in Table 6-5 to state diagram in Figure 6-25(d). ) R R R Reset lock Z Present State Next State a) = = = b) lear = Reset lear = Reset lear = Reset c, d, e, f) The circuit is suitable for child s toy, but not for life critical applications. In the case of the child s toy, it is the cheapest implementation. If an error occurs the child just needs to reset it. In life critical applications, the immediate detection of errors is critical. The circuit above enters invalid states for some errors. For a life critical application, additional circuitry is needed for immediate detection of the error (Error = + ). This circuit using the design in a), does return from the invalid states to a valid state automatically after one or two clock periods. 25

77 Problem Solutions hapter Specification Verification Present state Input Next state Next state Q S R Q(t+) Q(t+) x x x x x 6-28.(Errata: hange 6-25 to hange Table 6-6 to Figure 6-4. hange Z to Y. ) lock Reset Y ps 2 ns 4 ns 6 ns 8 ns 6-29.* RESET 7 x/, / / / 2 / / / / 3 2 x/, / Format: Y/Z 5 / 4 /, / / 9 Reset,,,,,, x, x,,,,,,,,. 26

78 Problem Solutions hapter Y Z lock lock Reset Y ps 2 ns 4 ns 6 ns 8 ns 6-3.* lock J K Y Q ps 5 ns ns 5 ns This simulation was performed without initializing the state of the latches of the flip-flop beforehand. Each gate in the flip-flop implementation has a delay of ns. The interaction of these delays with the input change times produced a narrow pulse in Y at about 55 ns. In this case, the pulse is not harmful since it dies out well before the positive clock edge occurs. Nevertheless, a thorough examination of such a pulse to be sure that it does not represent a design error or important timing problem is critical. 27

79 Problem Solutions hapter * library IEEE; use IEEE.std_logic_64.all; entity mux_4to is port ( S: in ST_LOGI_VETOR ( downto ); : in ST_LOGI_VETOR (3 downto ); Y: out ST_LOGI ); end mux_4to; -- (continued in the next column) architecture mux_4to_arch of mux_4to is process (S, ) case S is when "" => Y <= (); when "" => Y <= (); when "" => Y <= (2); when "" => Y <= (3); when others => null; end case; end process; end mux_4to_arch; library IEEE; use IEEE.std_logic_64.all; entity mux_4to is port ( S: in ST_LOGI_VETOR ( downto ); : in ST_LOGI_VETOR (3 downto ); Y: out ST_LOGI ); end mux_4to; -- (continued in the next column) architecture mux_4to_arch of mux_4to is process (S, ) if S = "" then Y <= (); elsif S = "" then Y <= (); elsif S = "" then Y <= (2); elsif S = "" then Y <= (3); else null; end if; end process; end mux_4to_arch; library IEEE; use IEEE.std_logic_64.all; entity serial Ex3 is port (clk, reset, : in ST_LOGI; Z : out ST_LOGI); end serial Ex3; architecture process_3 of serial Ex3 is type state_type is (Init,,, 2, 2, 2, 3, 3); signal state, next_state: state_type; -- Process - state register state_register: process (clk, reset) if (reset = '') then state <= Init; else if (LK'event and LK='') then state <= next_state; end if; end if; end process; -- (continued in the next column) -- Process 2 - next state function next_state_func: process (, state) case state is when Init => if ( = '') then next_state <= ; else next_state <= ; end if; when => if ( = '') then next_state <= 2; else next_state <= 2; end if; when => next_state <= 2; when 2 => next_state <= 3; when 2 => if ( = '') then next_state <= 3; else next_state <= 3; end if; 28

80 Problem Solutions hapter 6 when 2 => if ( = '') then next_state <= 3; else next_state <= 3; end if; when 3 => next_state <= Init; when 3 => next_state <= Init; end case; end process; -- Process 3 -output function output_func: process (, state) case state is when Init => if ( = '') then Z <= ''; else Z <= ''; end if; when => if ( = '') then Z <= ''; -- (continued in the next column) else Z<= ''; end if; when => Z <= ; when 2 => Z <= ; when 2 => if ( = '') then Z <= ''; else Z <= ''; end if; when 2 => if ( = '') then Z <= ''; else Z <= ''; end if; when 3 => Z <= ; when 3 => Z <= ''; end case; end process; end process_3; clk reset x z state init b b2 b3x init b b2 b3x init b b2 b3x init clk reset x z state init b b2 b3 init b b2x b3x init b b2x b3 init

81 Problem Solutions hapter library IEEE; use IEEE.std_logic_64.all; entity Zseq_circuit is port (, Y, LK, RESET: in ST_LOGI; Z: out ST_LOGI ); end seq_circuit; architecture seq_circuit_arch of seq_circuit is type state_type is (,); signal state, next_state: state_type; state_register: process (LK, RESET) if RESET='' then--asynchronous RESET active High state <= ; elsif (LK'event and LK='') then --LK rising edge state <= next_state; end if; end process; -- (continued in the next column) library IEEE; use IEEE.std_logic_64.all; entity NRZI is port (, LK, RESET: in ST_LOGI; Z: out ST_LOGI ); end seq_circuit; architecture process_3 of NRZI is type state_type is (S,S); signal state, next_state: state_type; state_register: process (LK, RESET) if RESET='' then--asynchronous RESET active High state <= S; elsif (LK'event and LK='') then --LK rising edge state <= next_state; end if; end process; -- (continued in the next column) next_state_process: process (, Y, state) case state is when => if ( = '' and Y = '') then next_state <= ; else next_state <= ; end if; when => if Y = '' then next_state <= ; else next_state <= ; end if; end case; end process; output_func: process (, state) case state is when => Z <= ; when => Z <= not ; end case; end process; end seq_circuit_arch; next_state_process: process (, state) case state is when S => if ( = '') then next_state <= S; else next_state <= S; end if; when S => if ( = '') then next_state <= S; else next_state <= S; end if; end case; end process; output_func: process (, state) case state is when S => Z <= ; when S => Z <= not ; end case; end process; end process_3; clk reset x state s s s s s s s z 2 3

82 Problem Solutions hapter * library IEEE; use IEEE.std_logic_64.all; entity jkff is port ( J,K,LK: in ST_LOGI; Q: out ST_LOGI ); end jkff; architecture jkff_arch of jkff is signal q_out: std_logic; state_register: process (LK) if LK'event and LK='' then --LK falling edge -- (continued in the next column) case J is when '' => if K = '' then q_out <= ''; end if; when '' => if K = '' then q_out <= ''; else q_out <= not q_out; end if; when others => null; end case; end if; end process; Q <= q_out; end jkff_arch; * module problem_6_38 (S,, Y) ; input [:] S ; input [3:] ; output Y; reg Y ; // (continued in the next column) module problem_6_39 (S,, Y) ; input [:] S ; input [3:] ; output Y; reg Y ; // (continued in the next column) or ) case (S) 2'b : Y <= [] ; 2'b : Y <= [] ; 2'b : Y <= [2] ; 2'b : Y <= [3] ; endcase; end endmodule or ) if (S == 2'b) Y <= []; else if (S == 2'b) Y <= []; else if (S == 2'b) Y <= [2]; else Y <= [3]; end endmodule 3

83 Problem Solutions hapter //Serial to Excess 3 onverter module serial Ex3(clk, reset,, Z); input clk, reset, ; output Z; reg[2:] state, next_state; parameter Init = 3'b, = 3'b, =3'b, 2= 3'b, 2 = 3'b, 2 = 3'b, 3 = 3'b, 3 = 3'b; reg Z; 2: if ( ==) next_state <= 3; else next_state <= 3; 3: next_state <= Init; 3: next_state <= Init; endcase end // State Register always@(posedge clk or posedge reset) if (reset == ) state <= Init; else state <= next_state; end // Next StateFunction always@( or state) case (state) Init: if ( == ) next_state <= ; else next_state <= ; : if ( == ) next_state <= 2; else next_state <= 2; : next_state <= 2; 2: next_state <= 3; 2: if ( == ) next_state <= 3; else next_state <= 3; // (continued in the next column) State ssignment State ode State Name Init // Output Function always@( or state) case (state) Init: if ( == ) Z <= ; else Z <= ; : if ( == ) Z <= ; else Z <= ; : Z <= ; 2: Z <= ; 2: if ( == ) Z <= ; else Z <= ; 2: if ( == ) Z <= ; else Z <= ; 3: Z <= ; 3: Z <= ; endcase end endmodule clk reset Z state clk reset Z state module seq_circuit (, Y, LK, RESET, Z) ; input, Y, LK, RESET ; output Z ; reg [2:] state, next_state, Z; // (continued in the next column) parameter S = 3'b, S = 3'b; //State register process LK or posedge RESET) if (RESET) 32

84 Problem Solutions hapter 6 state <= S; else state <= next_state; end //Next state function or Y or state) case (state) S: next_state <=? (Y? S : S) : S; S: next_state <= Y? S : S; endcase end // (continued in the next column) //Output function or Y or state) case (state) S: Z <=? (Y? 'b : 'b) : 'b; S: Z <=? 'b : (Y? 'b : 'b); endcase end endmodule //NRZI ode Generator module NRZI (, LK, RESET, Z); input, LK, RESET; output Z; reg state, next_state, Z; parameter S =, S = ; //State Register always@(posedge LK or posedge RESET) if (RESET == ) // asynchronous RESET active High state <= S; else state <= next_state; end //Next State Function always@( or state) case (state) S: if ( == ) next_state <= S; else next_state <= S; S: if ( == ) next_state <= S; else next_state <= S; endcase end always@(, state) case (state) S: Z <= ; S: Z <= ~; endcase end endmodule LK RESET state Z ps ns 2 ns 6-43.* module JK_FF (J, K, LK, Q) ; input J, K, LK ; output Q; reg Q; LK) case (J) 'b: Q <= K? : Q; 'b: Q <= K? ~Q: ; endcase endmodule 33

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