Solutions to Problems Marked with a * in Logic and Computer Design Fundamentals, 4th Edition Chapter Pearson Education, Inc.

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2 -3* Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 28 Pearson Education, Inc. -7* Decimal, Binary, Octal and Hexadecimal Numbers from (6) to (3) Dec Bin Oct Hex A B D E F -9* ( ) 2 = = 77 (.) 2 = = (.) 2 = = Decimal Binary Octal Hexadecimal BD.A D6.A F37.A -* a) = 3.6 => = 4.8 => = 6.4 => =3.2 => ( ) = ( ) 8 b) ( ) = (792.4B) 6 -* c) (75.75) = (.) 2 a) (673.6) 8 = (.) 2 = (BB.) 6 b) (E7.B) 6 = (.) 2 = (774.54) 8 c) (3.2) 4 = (.) 2-6* = (64.4) 8 a) (BEE) r = (2699) r r + 4 r = 2699 r r 2685 = By the quadratic equation: r = 5 or 6.27 ANSWER: r = 5

3 Problem Solutions hapter -8* b) (365) r = (94) 3 r r + 5 r = 94 3 r r 89 = By the quadratic equation: r = 9 or 7 ANSWER: r = 7 a) ( ) BD = (4867) = () 2-9* b) (. ) BD = (378.75) = (.) 2 (694) = ( ) BD (835) = ( ) BD * (a) Move R column > Subtract 3 - Subtract 3 - Move R column > Subtract 3 - Move R Move R Move R Move R Leftmost in BD number shifted out: Finished (b) 2 Move R and columns > Subtract Move R and columns > Subtract Move R column > Subtract 3 - Move R Move R Move R column > Subtract 3 - Move R Move R Move R Leftmost in BD number shifted out: Finished 2

4 Problem Solutions hapter -25* a) () 2 b) ( ) BD c) ASII d) ASII with Odd Parity 3

5 2-.* a) Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 2 28 Pearson Education, Inc. YZ = + Y + Z Verification of DeMorgan s Theorem Y Z YZ YZ +Y+Z b) + YZ = ( + Y) ( + Z) The Second Distributive Law Y Z YZ +YZ +Y +Z (+Y)(+Z) c) Y + YZ + Z = Y + YZ + Z Y Z Y YZ Z Y+YZ+Z Y YZ Z Y+YZ+Z 2-2.* a) Y Y Y = Y = ( Y + Y) + ( Y + Y) = Y ( + Y) + Y ( + ) = + Y b) AB + B + AB + B = = ( AB + AB) + ( B + B) = B( A + A) + B ( + )

6 Problem Solutions hapter 2 B + B = c) Y + Z + Y = + Y + Z = Y + Y + Z = ( Y + ) ( Y + Y) + Z = Y + + Z = Y + ( + ) ( + Z) = + Y + Z d) Y + YZ + Z + Y + YZ = Y + Z + YZ = Y + YZ( + ) + Z + Y + YZ = Y + YZ + YZ + Z + Y + YZ = Y( + Z) + YZ + Z + Y + YZ = Y + Z( + Y) + Y + YZ = Y + Z + Y( Z + Z) + YZ = Y + Z + YZ + YZ( + ) = Y + Z( + Y) + YZ = Y + Z + YZ 2-7.* a) b) c) d) Y + YZ + Y = + YZ = ( + Y) ( + Z) = ( + ) ( + Y) ( + Z) = ( + Y) ( + Z) = + YZ + Y( Z + + Z) = + Y( Z + Z) = + Y( Z + ) ( Z + Z) = + YZ + Y = ( + ) ( + Y) + YZ = + Y + YZ = + Y W( Z + YZ) + W ( + WYZ) = WZ + WYZ + W + WYZ = WZ + WZ + W = W + W = ( AB + AB) ( D + D) + A = ABD + ABD + ABD + ABD + A + = ABD + A + = A + + A( BD) = A + + ( BD) = A + + BD 2-9.* a) b) c) d) F = ( A + B) ( A + B) F = (( V + W) + Y)Z F = [ W + + ( Y + Z) ( Y + Z) ][ W+ + YZ + YZ] F = AB + ( A + B) + A( B + ) 2-.* Truth Tables a, b, c Y Z a A B b W Y Z c 2

7 Problem Solutions hapter 2 Truth Tables a, b, c a) Sum of Minterms: Product of Maxterms: b) Sum of Minterms: Product of Maxterms: c) Sum of Minterms: Product of Maxterms: YZ + YZ + YZ + YZ ( + Y + Z) ( + Y + Z) ( + Y+ Z) ( + Y + Z) AB + AB + AB + AB ( A + B + ) ( A + B + ) ( A + B + ) ( A + B + ) WYZ + WYZ + WYZ + WYZ + WYZ + WYZ + WYZ ( W+ + Y+ Z) ( W + + Y + Z) ( W + + Y + Z) ( W+ + Y+ Z) ( W + + Y + Z) ( W + + Y + Z) ( W+ + Y+ Z) ( W + + Y + Z) ( W + + Y + Z) 2-2.* a) ( AB + ) ( B + D) = AB + ABD + B = AB + B s.o.p. = BA ( + ) p.o.s. b) + ( + Y) ( Y + Z) = ( + ) ( + ( + Y) ( Y + Z) ) = ( + + Y) ( + Y + Z) p.o.s. = ( + Y) ( + Y + Z) = + Y + Z s.o.p. c) ( A + B + D) ( B + EF) = ( A + B + ) ( A + B + D) ( A + + D) ( B + EF) = ( A + B + ) ( A + B + D) ( A + + D) ( B + E) ( B + F) p.o.s. ( A + B + D) ( B + EF) = AB ( + EF) + B( B + EF) + D( B + EF) = AB + AEF + BEF + BD + DEF s.o.p. 2-5.* 2-8.* a) Y b) B c) A A Z Z + Y A + B B + a) b) c) Y Y B W A Z Z D Σm( 3567,,, ) Σm( ,,,,,,, ) Σm(, 2, 6, 7, 8,, 3, 5) B 3

8 Problem Solutions hapter * a) Prime= ZWZWZ,,, b) Prime = D, A, BD, ABD, B c) Prime = AB, A, AD, B, BD, D 2-22.* a) s.o.p. D + A + BD b) s.o.p. A + BD + AD c) s.o.p. BD + ABD + ( AB or AD) p.o.s. ( + D) ( A + D) ( A + B + ) p.o.s. ( + D) ( A + D) ( A + B + ) p.o.s. ( A + B) ( B + D) ( B + + D) 2-25.* 2-32.* Essential = Z, Z Essential = A, BD, ABD Essential = A, B, BD a) b) Y c) B A B W A Z D Primes = AB, A, B, AB Primes = Z, Z, WY, WY, WYZ, WYZ Primes = AB,, AD, BD Essential = AB, A, B Essential = Z Essential =, AD F = AB + A + B F = Z + WY + WY F = + AD +( BD or AB) Y = Y + Y Dual ( Y ) = Dual ( Y + Y) = ( + Y) ( + Y) = Y + Y = Y + Y = Y 4

9 3-2.* Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 3 28 Pearson Education, Inc. A B F = AB + A D 3-24.* a) b) VDD F 7 F 6 F 5 F 4 F 3 F 2 F F A A A A G 7 G 6 G 5 G 4 G 3 G 2 G G

10 Problem Solutions hapter * D D D 2 D 3 D 4 D 5 D 6 D 7 A A A 2 DEODER A A A D 8 D 9 D D D 2 D 3 A 3 A 4 DEODER A A 2 3 D 4 D 5 D 6 D 7 D 8 D 9 D 2 D 2 D 22 D 23 D 24 D 25 D 26 D 27 D 28 D 29 D 3 D * D 3 D 2 D D A A V V = D + D + D 2 + D 3 A = D ( D + D 2 ) A = D D A D D 2 D 3 D D D D 2 A D D 3 D 2 D 3 D A A V 2

11 Problem Solutions hapter * D(7:) A(2:) 8x MU D (7:) Y S (2:) D(4:8) A(3) 8x MU D (6:) Y D (7) S (2:) 3 OR gates 3-43.* A A E D D D 2 D 3 onsider E as the data input and A, A as the select lines. For a given combination on (A, A), the value of E is distributed to the corresponding D output. For example for (A, A) = (), the value of E appears on D2, while all other outputs have value * A B D F F=D F= D F= D F= D VDD B A 4 x MU S S D Y D D 2 D 3 F 3

12 4-2.* Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 4 28 Pearson Education, Inc. = T 3 + T 2 = T + T 2 = A B + A + B = ( A + B ) + A B = ( A B + )( A + B ) = A B + A + B S = T 4 = T T 2 = A B ( A + B ) = ( A + B )( A + B ) = A B + A B S = A B T 3 T T 4 T * Unsigned s omplement 2 s omplement 4-6.* +36 = - 24 = - 35 = 36 +( 24) + = 2 = 35 - ( 24) + = = 4-6.* S A B 4 S 3 S 2 S S a) b) c) d) e)

13 Problem Solutions hapter * N N N3 N5 N4 N6 f 4-24.* begin F <= ( and Z) or ((not Y) and Z); end; 4-29.* The solution given is very thorough since it checks each of the carry connections between adjacent cells transferring and. In contrast a test applying = and A = 5 with B = would allow a whole variety of incorrect connections between cells that would not be detected. 4-3.*(Errata: Replace E with EN.) 2

14 Problem Solutions hapter * N N N3 N5 N4 N6 f 4-38.* module circuit_4_53(, Y, Z, F); input, Y, Z; output F; assign F = ( & Z) (Z & ~Y); endmodule 4-43.* The solution given is very thorough since it checks each of the carry connections between adjacent cells transferring and. In contrast a test applying = and A = 5 with B = would allow a whole variety of incorrect connections between cells that would not be detected. 3

15 Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 5 28 Pearson Education, Inc. 5-7.* 5-.* 5-3.* = = Present state Input Next state A B A B State diagram is the combination of the above two diagrams. S A = B R A = B Present state Input Next state Output A B A B Y S B A = R B A = 2 3 / / / / / / / / Format: /Y Present state Input Next state A B A B A B A B D A D B D A = A + B D B = A + B Logic diagram not given.

16 Problem Solutions hapter * / x/x Format: Y/Z (x = unspecified) x/x / / / Present state Inputs Next state Output Q(t) Y Q(t+) Z 5-26.* To use a one-hot assignment, the two flip-flops A and B need to be replaced with four flip-flops Y4, Y3, Y2. Y. Present State Input Next State Output A B Y4 Y3 Y2 Y A B" Y4 Y3 Y2 Y Z No Reset State Specified. D = Y = Y + Y4 D2 = Y2 = Y + Y2 D3 = Y3 = Y2 + Y3 D4 = Y4 = Y3 + Y4 D D D D Y Y2 Y3 Y4 Y lock 2

17 5-27.* a) c) S R Q Q No hange Reset Set Set Problem Solutions hapter 5 b) Format: SR Present state Input Next state,,,, Q S R Q(t+) A B x x x x x A = S B = SR S R A S B R lock Q *5-3. RESET 7 x/, / / / 2 / / / / 3 2 x/, / Format: Y/Z 5 / 4 /, / / 9 Reset,,,,,, x, x,,,,,,,,. 3

18 Problem Solutions hapter * lock J K Y Q ps 5 ns ns 5 ns This simulation was performed without initializing the state of the latches of the flip-flop beforehand. Each gate in the flip-flop implementation has a delay of ns. The interaction of these delays with the input change times produced a narrow pulse in Y at about 55 ns. In this case, the pulse is not harmful since it dies out well before the positive clock edge occurs. Nevertheless, a thorough examination of such a pulse to be sure that it does not represent a design error or important timing problem is critical * ( ) 4

19 Problem Solutions hapter * library IEEE; use IEEE.std_logic_64.all; entity mux_4to is port ( S: in STD_LOGI_VETOR ( downto ); D: in STD_LOGI_VETOR (3 downto ); Y: out STD_LOGI ); end mux_4to; -- (continued in the next column) architecture mux_4to_arch of mux_4to is begin process (S, D) begin case S is when "" => Y <= D(); when "" => Y <= D(); when "" => Y <= D(2); when "" => Y <= D(3); when others => null; end case; end process; end mux_4to_arch; 5-45.* 5-49.* library IEEE; use IEEE.std_logic_64.all; entity jkff is port ( J,K,LK: in STD_LOGI; Q: out STD_LOGI ); end jkff; architecture jkff_arch of jkff is signal q_out: std_logic; begin state_register: process (LK) begin if LK'event and LK='' then --LK falling edge -- (continued in the next column) module problem_6_39 (S, D, Y) ; input [:] S ; input [3:] D ; output Y; reg Y ; // (continued in the next column) case J is when '' => if K = '' then q_out <= ''; end if; when '' => if K = '' then q_out <= ''; else q_out <= not q_out; end if; when others => null; end case; end if; end process; Q <= q_out; end jkff_arch; or D) begin if (S == 2'b) Y <= D[]; else if (S == 2'b) Y <= D[]; else if (S == 2'b) Y <= D[2]; else Y <= D[3]; end endmodule 5-53.* module JK_FF (J, K, LK, Q) ; input J, K, LK ; output Q; reg Q; LK) case (J) 'b: Q <= K? : Q; 'b: Q <= K? ~Q: ; endcase endmodule 5

20 6-.* a) F = (A + B) D Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 6 28 Pearson Education, Inc. b) G = (A + B) ( + D) 6-4* The longest path is from input or D..73 ns +.73 ns +.48 ns +.73 ns =.267 ns 6-.* a) The longest direct path delay is from input through the two OR gates to the output Y. t delay = t pdor + t pdor = =.4 ns b) The longest path from an external input to a positive clock edge is from input through the OR gate and the inverter to the B Flip-flop. t delay = t pdor + t pd INV + t sff = =.35 ns c) The longest path delay from the positive clock edge is from Flip-flop A through the two OR gates to the output Y. t delay = t pdff + 2 t pdor =.4 + 2(.2) =.8 ns d) The longest path delay from positive clock edge to positive clock edge is from clock on Flip-flop A through the OR gate and inverter to clock on Flip-flop B. t delay-clock edge to clock edge = t pdff + t pdor + t pdinv + t sff = =.75 ns e) The maximum frequency is /t delay- clock edge to clock edge. For this circuit, t delay-clock edge to clock edge is.75 ns, so the maximum frequency is /.75 ns =.33 GHz. omment: The clock frequency may need to be lower due to other delay paths that pass outside of the circuit into its environment. alculation of this frequency cannot be performed in this case since data for paths through the environment is not provided.

21 6-3.* (Errata: hange "32 8" to "64 8" ROM) Problem Solutions hapter 6 IN OUT IN OUT IN OUT IN OUT 6-9.* Assume 3-input OR gates. W B B B d d d d d d d d d d d d d d d d A A A A d d d d d d d d D D D D W = A + B + BD = B D + B + BD Y = D + D Z = D Each of the equations above is implemented using one 3-input OR gate. Four gates are used. B 2

22 Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 7 28 Pearson Education, Inc * AND OR OR 7-4.* sl sr 7-5.* Q i remains connected to MU data input. onnect D i to MU data input instead of Mux data input 3. onnect Q i- to MU data input 2 instead of MU data input. Finally, is connected to MU data input * a),,,,.... b) # States = n

23 Problem Solutions hapter * The equations given on page can be manipulated into SOP form as follows: D = Q, D 2 = Q 2 Q Q 8 = Q Q 2 Q 8 + Q Q 2 + Q 2 Q 8, D 4 = Q 4 Q Q 2 = Q Q 2 Q 4 + Q Q 4 + Q 2 Q 4, D 8 = Q 8 (Q Q 8 + Q Q 2 Q 4 ) = Q 8 (Q Q 8 +Q Q 2 Q 4 ) + Q 8 (Q + Q 8 )(Q + Q 2 + Q 4 ) = Q Q 2 Q 4 Q 8 + Q Q 8. These equations are mapped onto the K-maps for Table 7-9 below and meet the specifications given by the maps and the table. D Q 2 D 2 Q 2 Q 4 Q 4 Q 8 Q 8 Q Q To add the enable, D Q 2 D Q change D to: D = Q EN. For the other three functions, AND EN with the Q 4 Q 4 Q 8 Q 8 expression ORed with the state variable. The Q Q circuit below results. D Q Y EN D Q 2 D Q 4 D Q 8 lock 7-4.* Present state Next state A B A B a) D B = b) D = B D A = B + A D B = A B + B D = 2

24 Problem Solutions hapter * 3 lock R Load R2 Load 7-9.* 2 R LOAD D D D 2 D 3 Q Q Q 2 Q 3 R2 LOAD D D D 2 D 3 Q Q Q 2 Q 3 lock 7-24.* a) LK R2 REG 4 D (-3) Q (-3) ADD 4 I A (-3) B (-3) (-3) O 2 TR 4 Load ount R D (-3) Q (-3) O b) 2 R REG 4 D (-3) Q L (-3) ADD 4 I A (-3) B (-3) (-3) O R2 REG 4 D (-3) Q L (-3) lock 3

25 Problem Solutions hapter * a) Destination <- Source Registers R <- R, R2 R <- R4 R2 <- R3, R4 R3 <- R R4 <- R, R2 b) Source Registers -> Destination R -> R4 R -> R, R3 R2 -> R, R4 R3 -> R2 R4 -> R, R2 c) The minimum number of buses needed for operation of the transfers is three since transfer b requires three different sources. d) R R R2 R3 R4 MU MU MU 7-3.*,,,,,,,, 7-3.* Shifts: A B 7-32.* Default: Z =, Z2 = S S + 2 S2 Z2 Z Reset * State: STA, STA, STB, ST, STA, STB, ST, STA, STB Z:,,,,,,,, - 4

26 Problem Solutions hapter * Default: Z = Reset STA STB STD Z ST STE Z 7-39.* STA STB Present state Input Next state Output A B A B W W Y Y Z ST Z D A = AW + BY + D B = AW D = B ( + Y) Z = B Y + The implementation consists of the logic represented by the above equations and three D flip-flops with Reset connected to S on the first flip-flop and to R on the other two flip-flops * LA IN LK L AR LB Bit 5 A(5:) Zero LK L BR B(5:) A(4:) S MU LK L L R R B(4:) R is a synchronous reset that overides any simultaneous synchronous transfer. Default: LA =, LB =, L = Reset A G LA G B LB L 5

27 Problem Solutions hapter 7 G D R LA D R LB D R L Reset 7-48.* library IEEE; use IEEE.std_logic_64.all; entity reg_4_bit is port ( LEAR, LK: in STD_LOGI; D: in STD_LOGI_VETOR (3 downto ); Q: out STD_LOGI_VETOR (3 downto ) ); end reg_4_bit; architecture reg_4_bit_arch of reg_4_bit is begin process (LK, LEAR) begin if LEAR ='' then Q <= ""; elsif (LK'event and LK='') then Q <= D; end if; end process; --asynchronous RESET active Low --LK rising edge end reg_4_bit_arch; clk clear d q 4 6

28 7-5.* module register_4_bit (D, LK, LR, Q) ; input [3:] D ; input LK, LR ; output [3:] Q ; reg [3:] Q ; LK or negedge LR) begin if (~LR) //asynchronous RESET active low Q = 4'b; else //use LK rising edge Q = D; end endmodule Problem Solutions hapter 7 LK LR D Q * library IEEE; use IEEE.std_logic_64.all; entity prob_7_53 is port (clk, RESET, W,, Y : in STD_LOGI; Z : out STD_LOGI); end prob_7_53; architecture process_3 of prob_7_53 is type state_type is (STA, STB, ST); signal state, next_state: state_type; begin -- Process - state register state_register: process (clk, RESET) begin if (RESET = '') then state <= STA; else if (LK'event and LK='') then state <= next_state; end if; end if; end process; -- Process 2 - next state function next_state_func: process (W,, Y, state) begin case state is when STA => -- ontinued in next column if W = '' then next_state <= STB; else next_state <= STA; end if; when STB => if = '' and Y = '' then next_state <= STA; else next_state <= ST; end if; when ST => next_state <= STA; end case; end process; -- Process 3 - output function output_func: process (, Y, state) begin case state is when STA => Z <= ''; when STB => if = '' and Y = '' then Z <= ''; else Z <= ''; end if; when ST => Z <= ''; end case; end process; end process_3; 7

29 Problem Solutions hapter * // State Diagram in Figure 5-4 using Verilog module prob_7_54 (clk, RESET, W,, Y, Z); input clk, RESET, W,, Y; output Z; reg[:] state, next_state; parameter STA = 2'b, STB = 2'b, ST = 2'b; reg Z; // State Register always@(posedge clk or posedge RESET) begin if (RESET == ) state <= STA; else state <= next_state; end // Next StateFunction always@(w or or Y or state) begin case (state) STA: if (W == ) next_state <= STB; else // (continued in the next column) next_state <= STA; STB: if ( == & Y == ) next_state <= STA; else next_state <= ST; ST: next_state <= STA; endcase end // Output Function always@( or Y or state) begin Z <= ; case (state) STB: if ( == & Y == ) Z <= ; else Z <= ; ST: Z <= ; endcase end endmodule 8

30 Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 8 28 Pearson Education, Inc. 8-.* a) A = 6, D = 8 b) A = 9, D = 32 c) A = 26, D = 64 d) A = 3, D = 8-3.* Number of bits in array = 2 6 x 2 4 = 2 2 = 2 * 2 Row Decoder size = 2 a) Row Decoder = to 24, AND gates = 2 = 24 (assumes level of gates with inputs/gate) olumn Decoder = 6 to 64, AND gates = 2 6 = 64 (assumes level of gates with 6 inputs/gate) Total AND gates required = =88 b) (32) = ( ) 2, Row = 5, olumn = 8-8.* a) 2 MB/28 K x 6 = 2MB/ 256 KB = 8 b) With 2 byte/word, 2MB/2B = 2 2, Add Bits = 2 28K addresses per chip implies 7 address bits. c) 3 address lines to decoder, decoder is 3-to-8-line

31 9-2.* Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 9 = 8 28 Pearson Education, Inc. V = 8 7 Z = F 7 + F 6 + F 5 + F 4 + F 3 + F 2 + F + F N = F * = S A + S A Y = S in B + S S B + S S B + S S in A A D D S B D D D2 D3 S S in Adder Y G A A S D D S B S S S D D D2 Adder Y 2 G D3 9-4.* (Errata: Delete after problem number) = A S + A S Y = B S S + B S S S B i A i S S D Y FA i I + G i D B i D2 B i D3 9-6.* 9-8.* a) OR =, NAND =, NOR = NOR = Out = S A B + S AB + S AB + S S AB + (one of S A B + S S A) b) The above is a simplest result. (a) (b) (c) (d)

32 Problem Solutions hapter 9 9-.* (a) R5 R4 R5 R5 = (d) R5 R R5 = (b) R6 R2 + R4 + R6 = (e) R4 sronstant R4 = (c) R5 R R5 = (f) R3 Data in R3 = 9-3.* a) Opcode = 8 bits b) 8 bits c) 262,44 d) +3,7 and 3,72 2

33 Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 28 Pearson Education, Inc. -2.* a) LD R, E b) MOV T, A c) LD E LD R2, F ADD T, B MUL F MUL R, R, R2 MUL T, ST T LD R2, D MOV T2, E LD D SUB R, R2, R MUL T2, F SUB T LD R2, MOV T3, D ST T DIV R, R2, R SUB T3, T2 LD A LD R2, A DIV T, T3 ADD B LD R3, B MOV Y, T MUL ADD R2, R2, R3 DIV T MUL R, R, R2 ST Y ST Y, R -3.* a) (A - B) x (A + ) x (B - D) = A B - A +x B D -x b, c) PUSH A PUSH B SUB PUSH A PUSH ADD A B A-B A A+ A A-B A A-B A-B MUL PUSH B PUSH D SUB MUL POP (A-B)x(A+) B D B-D (A-B)x(A+)x(B-D) (A-B)x(A+) B (A-B)x(A+) (A-B)x(A+) -6.* a) = = 4 b) = The number is negative because the branch is backwards. The assumes that the P has been incremented to point to the address after that of the address word of the instruction. -.* a) 3 Register Fields x 4 bits/field = 2 bits. 32 bits - 2 bits = 2 bits. 2 2 = b) 64 < < 28 => 7 bits. 2 Register Fields x 4 bits/field => 8 bits. 32 bits - 7 bits - 8 bits => 7 Address Bits

34 Problem Solutions hapter -4.* -7.* -9.* a) ADD R, R4 b) R 7B + 4B, R = 6, = AD R, R5 R 24 + ED +, R =, = AD R2, R6 R , R2 = E, = AD R3, R7 R3 F + +, R3 = 2, = Result OP Register SHR SHL SHRA SHLA ROR ROL ROR ROL Smallest Number = Largest Number = ( 2 26 ) * E e (e) * TEST () 6, R (AND Immediate with Register R) BNZ ADRS (Branch to ADRS if Z = ) 2

35 Problem Solutions hapter -25.* a) A = 93 B = - 92 A B = b) (borrow) =, Z = c) BA, BAE, BNE -27.* -3.* External Interrupts: ) Hard Drive 2) Mouse 3) Keyboard 4) Modem 5) Printer P SP TOS a) Initially b) After all c) After Return Internal Interrupts: ) Overflow 2) Divide by zero 3) Invalid opcode 4) Memory stack overflow 5) Protection violation A software interrupt provides a way to call the interrupt routines normally associated with external or internal interrupts by inserting an instruction into the code. Privileged system calls for example must be executed through interrupts in order to switch from user to system mode. Procedure calls do not allow this change. 3

36 -2.* -6.* ycle : Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 28 Pearson Education, Inc. a) The latency time =.5 ns x 8 = 4. ns. b) The maximum throughput is instruction per cycle or 2 billion instructions per second. c) The time required to execute is instruction + 8 pipe stages - = 7 cycles *.5ns = 8.5ns P = F ycle 2: P - =, IR = 448 2F 6 ycle 3: P -2 =, RW =, DA =, MD =, BS =, PS =, MW =, FS = 2, SH =, MA =, MB = BUS A = F, BUS B = 2F ycle 4: RW =, DA =, MD =, D = 2F2, D =, D2 = ycle 5: R = 2F2 -.* MOVA R7, R6 SUB R8, R8, R6 AND R8, R8, R IF DOF E WB Data Hazard IF DOF E WB IF DOF E WB -2.* a) MOV R7,R6 SUB R8,R8,R6 NOP AND R8,R8,R IF DOF E WB IF DOF E WB IF DOF E WB IF DOF E WB b) SUB R7,R7,R2 NOP BNZ R7,F NOP NOP AND R8,R7,R4 NOP OR R4,R8,R IF DOF E WB IF DOF E WB IF DOF E WB IF DOF E WB IF DOF E WB IF DOF E WB IF DOF E WB IF DOF E WB

37 Problem Solutions hapter -5.* Time ycle IF P: DOF P - : IR: E P -2 : A: B: RW: DA: MD: BS: PS: MW: FS: MB: MA: S: D': WB D: D: D2: RW: DA: MD: Time ycle 2 IF P: 2 DOF P - : 2 IR: A73 88 E P -2 : A: B: RW: DA: MD: BS: PS: MW: FS: MB: MA: S: D': WB D: D: D2: RW: DA: MD: Time ycle 3 IF P: 3 DOF P - : 3 IR: 93 8F E P -2 : 2 A: 3 B: RW: DA:7 MD: BS: PS: MW: FS:5 MB: MA: S: D': WB D: D: D2: RW: DA: MD: Time ycle 4 IF P: 4 DOF P - : 4 IR:83 9 E P -2 : 3 A: 2 B: RW: DA: MD: BS: PS: MW: FS: MB: MA:2 S: D': WB D: 2 D: D2: RW: DA:7 MD: P: 2 Time ycle 5 IF P: 3 R7: 2 DOF P - : 3 IR: E P -2 : 4 A: 2 B: 2 RW: DA: 8 MD: BS: PS: MW: FS: 8 MB: MA: S: D': WB D: 2 D: D2: RW: DA: MD: Time ycle 6 IF P: 4 DOF P - : 4 IR: E P -2 : 3 A: 2 B: RW: DA: 4 MD: BS: PS: MW: FS: 9 MB: MA: S: D': WB D: D: D2: RW: DA: 8 MD: Time ycle 7 IF P: 4 R7: 2 DOF P - : 4 IR: E P -2 : 3 A: B: RW: DA: MD: BS: PS: MW: FS: MB: S: D : WB D: D: D2: RW: DA: 4 MD: Time ycle 8 R4: Fields not specified above have fixed values throughout or are unused: SH. Based on the register contents, the branch is taken. The data hazards are avoided, but due to the control hazard, the last two instructions are erroneously executed. 2

38 Problem Solutions hapter -8.* AA 3: A 3: D D FAA 3: FAA 4 S DA 3: BA 3: D D FBA 3: FBA 4 BA 3: DA 3: D D FDA 3: FDA 4 B 3: D2 D 3: D2 B 3: D3 D 3: D3 S S S S A 4 B 4 D 4 D D D 2 D 3 D 4-22.* (a) Add with carry R M P M L M Action Address MZ A W D D BS S W FS MA B A B S R 3 AW 2 F 8 R 6 RSA [ ] + RSB [ ] AW 2 if (R 3 =) M AW5 AW2 AW5 F else M M + M M + (NOP) AW3 RDR [ ] R 6 + AW4 2 M IDLE AW5 IDLE (a) Subtract with borrow R M P M L M Action Address MZ A W D D BS S W FS MA B A B S R 3 R 6 RSA [ ] R[ SB] SWB 2 F 8 SWB 5 if (R 3 ) M SWB5 SWB2 SWB5 F else M M + M M + (NOP) SWB3 RDR [ ] R 6 SWB4 5 M IDLE SWB5 IDLE 3

39 Problem Solutions hapter -24.* Memory Scalar Add (Assume R[SB] > to simplify coding) R M P M L M Action Address MZ A W D D BS S W FS MA B A B S R 6 R 8 R RSB [ ] R 6 R 6 M M + R 7 M M + RSA [ ] + R 6 if (R 6 ) M MSA2 else M M + R 8 MR [ 7 ] + R 8 RDR [ ] R 7 M IDLE MSA MSA 2 MSA2 5 (NOP) MSA3 MSA4 2 (NOP) MSA5 MSA6 MSA2 MSA7 2 2 MSA8 MSA9 IDLE 4

40 2-.* Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 2 28 Pearson Education, Inc. Heads x (cylinders/head) x (sectors/cylinder) x ( cylinder/track) x (bytes/sector) a) x 23 x 63 x 52 = 32,224.5 Kbytes (K = 24) b) 4 x 89 x 63 x 52 =,32,66 Kbytes c) 6 x 6383 x 63 x 52 = 8,257,32 Kbytes 2-5.* a) If each address line is used for a different S input, there will be no way to address the four registers so 2 bits are needed to address the registers. Only 4 lines can be used for S inputs permitting at most 4 I/O Interface Units to be supported. b) Since two bits must be used to address the four registers, there are 4 bits remaining and 2 4 or 6,384 distinct I/O Interface Units can be supported. 2-7.* A given address can be shared by two registers if one is write only and one is read only. If a register is both written to and read from the bus, then it needs its own address. An 8-bit address provides 256 addresses. Suppose that the 5 % of registers requiring address is. Then the remaining 5 % of the registers, also can share addresses requiring only.5 addresses. So.5 = 256 and = 7.67 registers for a total of registers. To meet the original constraints exactly, the total number of registers must be divisible by 4, so 34 registers can be used, 7 of which are read/ write, 85 of which are read only and 85 of which are write only. There is one more address available for either one read/write register or up to a pair with a read only register and a write only register. 2-9.* (a) (b) Read Operation PU Data Bus Address Bus RD Strobe WR Strobe I/O Device Data bus Address bus Read Strobe Write Strobe From I/O Data bus Write Operation From PU Address bus Read Strobe Write Strobe 2-.* There are 7 edges in the NRZI waveform for the SYN pattern that can be used for synchronization.

41 Problem Solutions hapter * SYN 8 bits Type 4 bits heck 4 bits Device Address Endpoint Address R EOP (a) Output packet SYN 8 bits Type 4 bits heck 4 bits Data R EOP (b) Data packet (Data type) (bits LSB first) SYN 8 bits Type 4 bits heck 4 bits EOP (c) Handshake packet (Stall type) 2-6.* 2-8.* 2-2.* 2-22.* Device Device Device 2 Description PI PO RF VAD PI PO RF VAD PI PO RF VAD Initially Before PU acknowledges Device After PU sends acknowledge - - Replace the six leading s with. This is Figure 3-7 with the Interrupt and Mask Registers increased to 6 bits each, and the 4x2 Priority Encoder replaced by a 8x3 Priority Encoder. Additionally, VAD must accept a 3rd bit from the Priority Encoder. When the PU communicates with the DMA, the read and write lines are used as DMA inputs. When the DMA communicates with the Memory, these lines are used as outputs from the DMA. 2

42 Solutions to Problems Marked with a * in Logic and omputer Design Fundamentals, 4th Edition hapter 3 28 Pearson Education, Inc. 3-3.* Since the lines are 32 bytes, 5 bits are used to address bytes in the lines. Since there are K bytes, there are 24/32 = 2 5 cache lines. a) Index = 5 Bits, b) Tag = = 22 Bits c) 32 ( ) = 8928 bits 3-5.* a) See Instruction and Data aches section on page 635 of the text. b) See Write Methods section on page 63 of the text * (i) (i4) (i6) (i) (i) (d) (i7) (d) (i2) (i5) (i8) (i) (i3) (d) (i9) (d) Addresses of instructions (i) and Data (d) in sequence down and then to the right with the instructions in a loop with instruction i following i. For the split cache, the hit - miss pattern for instructions is (assuming the cache initially empty and LRU replacement) M, M, M, M, M, M, M, M, M, M, M, M, M,... since there are only eight locations available for instructions. For the unified cache, the hit-miss pattern for instructions with the same assumptions is M, M, M, M, M, M, M, M, M, M, M, M, H, H, H,... since there are 2 locations indexed appropriately for instructions and four indexed appropriately for data. 3-.* 3-3.* a) Effective Access Time =.9 * 4ns +.9 * 4 ns = 7.24 ns b) Effective Access Time =.82 * 4ns +.8* 4 ns =.48 ns c) Effective Access Time =.96 * 4ns +.4 * 4 ns = 5.44 ns a) Each page table handles 52 pages assuming 64-bit words. There are 4263 pages which requires 4263/ page tables. So 9 page tables are needed. b) 9 directory entries are needed, requiring directory page. c) *52 = 67 entries in the last page table. 3-7.* In section 4-3, it is mentioned that write-through in caches can slow down processing, but this can be avoided by using write buffering. When virtual memory does a write to the secondary device, the amount of data being written is typically very large and the device very slow. These two factors generally make it impossible to do write-through with virtual memory. Either the slow down is prohibitively large, or the buffering cost is just too high.