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1 Philadelphia University Faculty of Engineering Marking Scheme Exam Paper BSc CE Logic Circuits (630211) Final Exam First semester ate: 03/02/2019 Section 1 Weighting 40% of the module total Lecturer: Coordinator: Internal Examiner: r. adri Hamarsheh r. adri Hamarsheh r. Naser Halasa

2 Marking Scheme Logic Circuits (630211) The presented exam questions are organized to overcome course material through 6 questions. The all questions are compulsory requested to be answered. Marking Assignments uestion 1 This question is attributed with 10 marks if answered properly; the answers are the following: 1) Which of the following is not a weighted value positional numbering system: a) hexadecimal b) binary c) binary-coded decimal d) octal 2) Convert to binary. a) b) c) d) 343 3) The Gray code of the binary number 0101 is a) 1111 b) 1000 c) 0111 d) None of the above 4) Simplification of the Boolean expression AB + ABC + ABC + ABCE + ABCEF yields which of the following results? a) AB b) AB + C + EF c) ABCEF d) A + B + C + + E + F 5) Applying emorgan's Law to f AB C E will result in: a) f A B C E b) f A B C E c) f A B C ( E ) d) f A B C E 6) From the truth table below, determine the standard SOP expression. a) b) c) d) 7) The logic function implemented by the circuit below is (ground implies a logic 0 ) a) F = AN (P, ) b) F = OR (P, ) c) F = XOR (P, ) d) F = XNOR (P, ) 8) The characteristic equation of S-R latch is a) (n + 1) = S R + (n)r b) (n + 1) = (S + (n))r c) (n + 1) = SR + (n)r d) (n + 1) = S R + (n)r

3 9) The figure shown below is a) A T flip flop b) An S-R latch c) A JK flip flop d) A flip flop 10) A ripple counter is a(n) device a) asynchronous b) Combinational c) synchronous d) None of them uestion 2 This question is attributed with 6 marks if answered properly; the answers are the following: a) Prove the identity of the following Boolean equation, using algebraic manipulation: A B + B C + AB + B C = 1 (2 marks) b) raw 4-bit asynchronous binary counter using JK flip flops and its timing diagram. (4 marks)

4 uestion 3 This question is attributed with 4 marks if answered properly; the answers are the following: Implement full adder circuit using 4:1 multiplexers. uestion 4 This question is attributed with 7 marks if answered properly; the answers are the following: a) erive the Boolean equations for and B out. (3 marks) b) Implement and B out logic circuits. (2 marks) P P B in B in B out c) esign the 1-bit full subtractor using 3x8 decoder. (2 marks) Bin P 0 1 E C O E R 2 3x8 B out uestion 5 This question is attributed with 6 marks if answered properly; the answers are the following:

5 The flip flop input equations are The output equations are flip flops Thus State table State diagram uestion 6 This question is attributed with 7 marks if answered properly; the answers are the following:

6 The next state table for this state diagram (1.5 marks) Input Current State Next State Output X Y The excitation equations if J-K flip flops are used to implement this state diagram (use the Karnaugh map in your solution). J-K flip flop transition table: current next J K x x 1 0 x x 0 (2 marks) Input Current State Next State Output flip flop inputs (excitation) X Y J1 K1 J0 K x 1 x x x x 1 1 x x 0 x x 0 x x x x 0 1 x x 1 x 0 Karnaugh map J1 K1 J0 K0 (2 marks) Y X x x 11 x x J1 0 X x x x x K1 X 0 X0 The logic circuit using J-K flip flops X x 01 1 x 11 1 x 10 x 0 J 0 X 1 X x 1 01 x 1 11 x 0 10 x 1 K 0 X 1 X Y 10 (1.5 marks) J SET 1 X K CLR Y J SET 0 K CLR

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