Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals

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1 Department of Electrical and Computer Engineering Universit of Wisconsin - Madison ECE/C 352 Digital stem Fundamentals Quiz #2 olution Thursda, Octoer 26, 2000, 7:15--8:30PM 1. (15 points) (a). (5 points) NAND, NOR gates Implement the following Boolean function using 2-level NAND-NAND realization F (,, z) = ( + + z)( + + z) using minimum numer of NAND gates. Assume complements of the input Boolean variales are availale. Answer: F (,, z) = + + z (). (5 points) NOR gate implementation Convert the following logic schematic diagram into NOR-onl realization. You ma use two-input NOR gates and inverters. Assume the complements of all input Boolean variales are NOT availale. a z F(,,z) c d F(a,,c,d,e) e Answer: a F(a,,c,d,e) c e d (c) (5 points) Taular Method ECE/C 352 Quiz #2 Octoer 26,

2 Let: P(v,w,,,z) = m(12,13,14,15,29,31) + d(17,18). Eecute the Quine-McCloske algorithm to find all the Prime Implicants of the function P(v,w,,,z), where the second summation is the don't care minterms. The algorithm has een started for ou elow (minterms are listed in increasing 1's count order). Complete the algorithm and CIRCLE the PRIME IMPLICANT. m i Inde Order 1-Cues 2-Cues 18(d) (12,13) (12,13,14,15) 17(d) (12,14) (13,15,29,31) (13,15) (14,15) (13,29) (15,31) (29,31) Note that there are no three-cues and that duplicate two-cues have een eliminated. 2. (10 Points) Code Conversion, Adders A inar multiplier produces partial products that must e added together. For adding partial products ou will uild a circuit that adds a column of si inar digits, producing a three it sum, depending upon how man of the si its are one. As shown elow, the three it sum = 000 for a si inar digit column (zero ones). A sum = 110 results from a si inar digits column (si ones). A sum = 011 results from a si inar digits column (three ones). A B C D E F The circuit elow starts the process using two Full Adders (FA) connected to ABC and DEF as shown. Complete the wiring,(no additional logic is needed) connecting the first level of Full Adders to the second level of Full Adders and Half Adders so that the sum is produced. Lael the sum its 2, 1, and 0. (Hint: the first two half-adders produce two, 2-it sums. Complete the sum adding their outputs together.) ECE/C 352 Quiz #2 Octoer 26,

3 A B C D E F Co FA Ci Co Ci FA 2 Co Ci FA Co HA Aove is one solution. Alternate solutions swap the connections to the X and Y inputs of the HA elow and swap an of X, Y, and Ci inputs of the FA elow. 3. (15 Points) Decoder Implementations Two decoders constructed with NAND gates are connected to primar input variales A, B, C and D as shown in the diagram elow. The function tale for the decoder is shown elow: A B C D D3 D2 D1 D0 D3 D2 D1 D0 M L K J I H G F 1 0 R(A,B,C,D) Q(A,B,C,D) 1 0 D3 D2 D1 D ECE/C 352 Quiz #2 Octoer 26,

4 3a). (5 points) Write a Boolean equation in the o elow for the signal shown as "M" on the diagram in terms of the primar input signals A, B, C and D. M = ( A B) = A + B 3). (5 points) Using ONE gate (of the required input width) selected from the set of gates {AND, NOT, OR, NAND, NOR}, draw the gate on the diagram aove and connect it to DECODER OUTPUT (signals F,G,H,I,J,K,L,or M) to implement: Q(A,B,C,D) = (A+B+C+D) = J + F 3c). (5 points) Using one or more gates (of the required input width) selected from the set of gates {AND, NOT, OR, NAND, NOR}, draw a logic diagram on the diagram aove that uses DECODER OUTPUT (signals F,G,H,I,J,K,L,or M) to implement: R(A,B,C,D) = A B' + C D' = (( A+ B)( C + D)) = ( L H ) 4 (15 points) Multipleer Logic Implementation Use the 8-to-1 multipleer elow to implement an eclusive or function for four its. This is also known as the "odd" function. The function eor(w,,,z) is to e: eor(w,,,z) = w z Draw the circuit in the space elow. You ma use onl NOT, OR, and AND gates. (Hint: the variale "w" has een factored out). w W z D7 D6 D5 D4 D3 D2 D1 D (15 Points) igned Arithmetic, Complements, Numer Representation Fill in the tale elow with 8-it inar numers in the given signed representation. The first row has een done for ou. The decimal numers (-45) and (-120) are a "negative fort-five" and a "negative one-hundred, twent" respectivel. Convert the decimal numers to the proper ECE/C 352 Quiz #2 Octoer 26, Out 8-to-1 MUX eor(w,,,z)

5 representations, state them as an ADDITION PROBLEM in the representation, and give the correct result in each representation. If the calculation produces an overflow in an of the representations used, note it as "OVERFLOW" and omit the answer. (Hint: 120 and 45 are and epressed as 8-it unsigned inar numers) Prolem ign-magnitude 1's Complement 2's Complement (-120) Overflow OVERFLOW OVERFLOW OVERFLOW (-45) (Discard carr) (10 Points) Carr Look-ahead Adders Consider an adder with inputs A = A 3 A 2 A 1 A 0 and B= B 3 B 2 B 1 B 0, c 0 and outputs = and c 4. Recall that for the stage i in an adder, the propagate and generate functions are: P(i) = A(i) B(i) G(i) = A(i) B(i) and the output sum (i) and carr C(i+1) is defined as: (i) = P(i) C(i) C(i+1) = G(i) + P(i) C(i) Let A = 1110 and c 0 = 1. Write an epression using AND, OR or NOT operators (, +, ') for the carr, c 4 as a function of B 3, B 2, B 1, and B 0. ECE/C 352 Quiz #2 Octoer 26,

6 Answer: c 4 = G 3 +P 3 (G 2 +P 2 (G 1 +P 1 (G 0 +P 0 C 0 ))) = B 3 + B3B2 + B3 B 2B1 + B 3 B 2 B1B0 = B 3 + B 2 + B 1 + B 0 Note that G 3 = B 3, P 3 = B 3, G 2 = B 2, P 2 = B 2, G 1 = B 1, P 1 = B 1, G 0 = 0, P 0 = B 0, C 0 = 1. Alternatel, note that the onl input which does NOT generate a carr is for B = 0000, thus: C 4 ' = B 3 'B 2 'B 1 'B 0 ' and DeMorgan's Rule C 4 = B 3 + B 2 + B 1 + B (10 Points) Verilog HDL The Verilog for a structural circuit definition of module "what_is_this" is shown elow. Convert the structural definition to a logic diagram of the circuit. DRAW THE LOGIC DIAGRAM. Please place the inputs on the left and outputs on the right side of the diagram. LABLE EVERY WIRE AND GATE. module what_is_this(a, B, w,,,z, F); input A, B ;w z output F; endmodule wire A_n, B_n, p1, p2, p3, p4 ; not g0(a_n, A), g1(b_n, B) ; nand g2(p1, A_n, B_n, w), g3(p2, A_n, B, ), g4(p3, A, B_n, ), g5(p4, A, B, z), g6(f, p1, p2, p3, p4) ; A B g0 g1 A_n B_n w z g2 g3 g4 g5 p2 p1 p3 p4 g6 F 8. (10 Points) Decimal Arithmetic ECE/C 352 Quiz #2 Octoer 26,

7 (a) (6 points) BCD decimal digit adder Below is a partial logic diagram of a BCD-ased decimal digit adder. The missing part is the one that generates the carr-out to the net digit, and proper inputs to the lower 4-it inar adder. Use AND, OR, NOT gates to implement this part. Addend 4 Augend 4 K 4-it inar adder Z 3 Z 2 Z 1 Z 0 Input carr Output carr C 0 4-it inar adder () (4 points) 9's complement and 10's complement BCD um Find the 9's complement of the decimal numer 73522: Use 10's complement to perform the sutraction of two unsigned decimal numers = 193 You must show intermediate steps. Answer alone will not receive an credit. Answer: 10's complement (2188) = 7812, = 9807 carr out = 0 This implies that the solution is negative. Thus, the answer is 10's complement(9807) = 193 ECE/C 352 Quiz #2 Octoer 26,

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr.

Chapter 4. Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. elements. Dr. Chapter 4 Dr. Panos Nasiopoulos Combinational: Circuits with logic gates whose outputs depend on the present combination of the inputs. Sequential: In addition, they include storage elements Combinational