TCAD Modeling of Stress Impact on Performance and Reliability

Transcription

1 TCAD Modeling of Stress Impact on Performance and Reliability Xiaopeng Xu TCAD R&D, Synopsys March 16, 2010 SEMATECH Workshop on Stress Management for 3D ICs using Through Silicon Vias 1

2 Outline Introduction Stress in device, interconnect and TSV stack Stress impact on performance and reliability TCAD stress modeling Modeling requirements Multi-scale process simulation with layout Performance and reliability analysis Stress management with TCAD Device stress engineering Design and technology exploration Summary 2

3 Ubiquitous Mechanical Stress Gate Cap layer Spacer Low-k Si 3 N 4 Silicon die 2 μ-bump Mechanical Failure and Reliability in Stressed 3D Structures STI SiGe S/D Cu Low-k Die 1 TSV Z 001/110 Y X SiO 2 Silicon Bump Package Substrate Performance Modulation in Stressed Transistors Typical stress source: o Thermal mismatch due to temperature ramps o Lattice mismatch from epitaxy grain growth o Intrinsic stress due to material bonding o Force rebalance after etching, deposition, thinning, bumping, and stacking Stress impact: o Band structure change induces device performance variation o Mechanical deformation leads to damage and reliability degradation 3

4 Stress Impact on Device Performance Far Close Compressive ESL simulations K.V.Loiko et al AMAT/IMEC/SNPS

5 Stress Impact on BEOL Reliability 3D structure from Layout Process Distinct materials Non-uniform stress Cracking in Dielectrics J. McPherson, TI, 2006 Voiding in Copper K. Ueno, NEC 2005 De-lamination along Low k Interface T. Huang, TSMC,

6 TSV Mechanical Stress Related Concerns TSV extrusion and de-lamination - P. Ho, RTI 3D Symposium 2009 New Stress Sources New thermal mismatch stresses Copper grain growth stress in TSV New material interactions Stress Concern Examples Manufacturability Effect of thin die warping Effect of die stacking Reliability Cracking around TSV Layer de-bonding and de-lamination TSV deformation and voiding Performance (mobility) variability Stress relaxation due to thinning TSV and u-bump proximity effects Performance shifting after wafer thinning - QCT/IMEC, DATE

7 Outline Introduction Stress in device, interconnect and TSV stack Stress impact on performance and reliability TCAD stress modeling Modeling requirements Multi-scale process simulation with layout Performance and reliability analysis Stress management with TCAD Device stress engineering Design and technology exploration Summary 7

8 Stress Modeling Requirements Structure generation Fabrication process: e.g. deposition, etching Design layout Stress analysis Stress source Thermal mismatch from process flow Intrinsic bonding from material formation External loading from stacking and packaging Stress evolution Different stress laws for various materials Models for stress effect Stress-to-mobility model for performance Stress-to-damage model for reliability Design and technology exploration Design variables: size, pitch, KOZ, pattern, rules Technology variables: material, insulation, wafer thinning 8

9 TCAD TSV 3D Simulation Flow Process Info Layout Info Deposition Material=Oxide thickness=0.3 Etch mask=metal_2 Material=Oxide thickness=0.3 Process Simulation Finite Element Analysis Material Property Database Mobility Variation Global Model Reliability Effective Stress 3D Structures Solution Fields Reliability Analyses Mobility Variations Submodel 1 Submodel 2 Submodel 3 t=400um Die Thinning t=20um 9

10 TSV Process/Stress Simulation Example FEOL TSV BEOL Thinning Backside μ-bump Stacking FEOL TSV BEOL TSV: deep etch oxidize plate and fill (cu) TSV Silicon BEOL Thinning Backside Die 1 μ-bump Stacking Die 2 μ-bump Die 1 Hydrostatic Stress before and after Die 1 and 2 Stacking Die 1 High TSV Stress Die 2 Die 2 MPa Die 1 Process simulation for TSV and stacking is required to track the stress evolution. Same stress results can be used to analyze reliability and mobility change. 10

11 Stress Impact on Electrons and Holes Stressed Electron Band Change under Stress m l mt E c [001] E c [010] [001] valley lowered and [010] [100] valley raised with stress m t < m l Δ 4 Δ 2 E c [100] Carrier repopulation into lower Δ 2 valley with small transport mass along <110> Hole Band Change under Stress Relaxed Stressed <110> mass decreased with compressive stress Carrier repopulation into valley with smaller <110> mass 11

12 Stress Induced Voiding and Cracking Stress Migration Model for Metal Voiding 2 1 C 1 C = σ H D t kt K. Ueno, NEC 2005 T.C. Huang, et al., IITC T n /σ max Cohesive Zone Model normal -T t /τ max tangential Barrier Low k Δ n /δ n M Δ t /δ t X. Xu and A. Needleman, 1994, JMPS De-bonding Oxide M3 Copper M2 Oxide J. McPherson, TI, 2006 Unit: % (normalized to initial concentration) Accumulated vacancy density in metal 12

13 Silicon Mobility Variation around TSV Wafer, 110 Flat Orientation TSV Array Mobility Variation (%) n Si, Cu Via p Si, Cu Via 5 Barrier Si Distance along y axis (micron) Cu Layout: 5/25 Mobility Variation (%) n Si, Cu Via p Si, Cu Via Distance along x axis (micron) 13

14 Thermal Stress Induced TSV Pop-up Expansion Contraction Szx (MPa) ΔT > 0 ΔT < 0 Large shear stress at TSV-silicon interface leads to de-bonding 14

15 Sub-modeling Barrier (Oxide) TSV TSV Epoxy Landing Pad Oxide Low-k Nitride r a e m S Landing Pad Si Metal Lines y z x Global TSV structure and submodeling Landing pad and metal lines in the submodel (back view) 15

16 Outline Introduction Stress in device, interconnect and TSV stack Stress impact on performance and reliability TCAD stress modeling Modeling requirements Multi-scale process simulation with layout Performance and reliability analysis Stress management with TCAD Device stress engineering Design and technology exploration Summary 16

17 Stress Engineered Transistors 20nm nmos 20nm pmos Tensile CESL Recessed SiC S/D Geometry optimization Compressive CESL Elevated SiGe S/D Geometry optimization 001/110 ECS

18 Keep Out Zone around TSV 001 Wafer, 110 Flat Orientation Layout: 5/30 Si/STI/TSV Active: 0.5/1.0 STI: 0.5 KOZ: Keep Out Zone KOZ Sxx in Silicon (MPa) P-Si Mobility Variation (%) 18

19 TSV Diameter Impact on Performance TSV Diameter = 5 um 001 Wafer, 110 Flat Orientation 40 TSV Diameter = 10 um ~38% higher normal stress Sxx (MPa) Mobility Variation (%) p Si, Cu Via d=10 um d=5 um Distance along y axis (micron) Larger TSV diameter leads to larger mobility change in silicon 19

20 TSV Diameter Impact on Reliability Expansion ~112% more max displacement ΔT > 0 D = 5 um D = 10 um Szx (MPa) Szx (MPa) Larger TSV diameter leads to larger deformation and shear stress 20

21 Insulation Material Impact on Performance 001 Wafer, 110 Flat Orientation 30 Oxide > 80% modulus reduction ~50% less normal stress Sxx (MPa) Mobility Variation (%) Low k Oxide p Si, Cu Via Distance along y axis (micron) Low k Low k insulation reduces mobility variation in silicon 21

22 Insulation Material Impact on Reliability ΔT > 0 ~70% more displacement Oxide insulation Low k insulation Low k insulation provides less resistance to Cu extrusion 22

23 TSV Material Effects Cu Si W Si Cu Cu Copper TSV Tungsten TSV Effective Stress Tungsten has less mismatch with silicon but more with copper 23

24 Summary Large mechanical stresses are present in device, interconnect, and TSV stack. Complex stress interactions impact both performance and reliability. 3D TCAD process simulation of stress evolution provides valuable insights for tech tuning and stress management. Studies on stress engineering, performance and reliability trade-off are carried out for design and technology explorations. 24