Supplementary Information for On-chip cooling by superlattice based thin-film thermoelectrics

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1 Supplementary Information for On-chip cooling by superlattice based thin-film thermoelectrics Table S1 Comparison of cooling performance of various thermoelectric (TE) materials and device architectures for high heat flux cooling. TE material type and thickness Material (with references) Nanostructured thin film superlattice (<10 µm) Bi 2 Te 3 S3 SiGe S1,S2 T max at zero load at the element ( o C) 2.8@25 o C 7@100 C q max at zero cooling at the element (W/cm 2 ) 100 C q max at zero cooling for the substrate (W/cm 2 ) T max at zero hotspot load for TE cooler on the backside of chip ( o C) NA < Hotspot q max for TE cooler on the backside of chip (W/cm 2 ) 55@ 25 C 715@ 25 C NA Not reported Not reported Nanostuctured thick quantum dot superlattice (~100 µm) Thick film (10-20 µm) Thin bulk device ( µm) PbSeTe Inplane S Calculated ~45 Calculated NA Not reported Not reported Bi 2 Te S5 3 32@85 C 100 Not reported Not reported Bi 2 Te 3 S6 83 to 85 C 98 to C 44 to C Not reported Not reported The performance of the thin thermoelectric modular packaged devices are expected to degrade dramatically compared to what is achieved at the material/element level due to contact parasitics (thermal and electrical contact resistances), conduction of heat in the adjoining substrates and back conduction of heat from other thermal paths in an integrated system. This can be clearly seen for the nanostructured SiGe thin-film based thermoelectric devices when the values of T max are compared at the element and integrated device levels. 1

2 Test structure The test geometry and layout of the silicon test chip used in the experiments are shown in Fig. S1. There is a uniform heater (background heater) that supplies power throughout the chip area of mm 2. In addition there is a small, localized heater that creates a high heat flux region in the middle of the chip. This heater is µm 2. The localized heater serves to simulate the high heat flux regions in an actual microprocessor chip. Both the heaters consist of thin metal traces defined on the Si chip as shown in Fig. S1b. Current is passed through these metal traces to induce Joule heating. There is also a resistive temperature detector (RTD) located at the middle of the chip which measures the temperature of the chip at the localized high heat flux region. There are a total of 25 such temperature sensors distributed at various locations on the test chip (center, corners, and between the center and the corners). The detailed design of the background heater, the localized heater and RTD are discussed elsewhere S7. Throughout these tests, the background heater power was set at 60W while the localized heater power was set at 2W. From the dimensions given above, this translates to a background heat flux of 42.7 W/cm 2 and a local hot-spot power density of 1250 W/cm 2. Thermal grease S8 was used as the thermal interface material (TIM) between the backside of the chip and the integrated heat spreader. The thickness of the grease layer outside the thermoelectric cooler (TEC) area was approximately 125 µm. As the TEC itself is 100 µm thick, there was ~25 µm of grease between the device and the backside of the silicon chip. Spacers were used to protect both the device and the test chip from any mechanical damage that could potentially occur during the testing process. We would like to point out that although it is possible to maintain a thin layer of TIM beneath the 2

3 TEC due to its small size ( mm), it is difficult to achieve the same level of thickness over the entire chip area. This is because of practical challenges such as degradation in the thermal performance due to various mechanical stresses arising from the coefficient of thermal expansion mismatch between the different layers of an electronic package S9. In general, the thermal and mechanical requirements in an electronic package place opposing constraints on the design rules. Details on thermal testing and experimental results The first set of experiments was conducted to measure the effective thermal conductivity (k TIM ) of the thermal interface material (TIM) in the packaged environment. In these experiments, the heat spreader was attached to the test chip without the TEC. The chip temperature was measured for different background heater powers without switching on the hotspot. The slope of the temperature vs. power graph provided the value of thermal resistance from the chip (junction) to the ambient (Ψ ja ). Knowing this value and by subtracting out the thermal resistance of other elements in the stack-up (silicon chip, copper heat spreader, and cooling solution), we extracted the thermal resistance of the TIM in the packaged environment. Effective k TIM was estimated to be ~1.75 W/m-K. The next set of experiments was conducted with the TEC inserted in the setup, hotspot switched on and with different currents through the device. The results from these experiments are shown in Fig. 3a. As mentioned earlier, in addition to the temperature sensor at the center of the chip, there were 24 other sensors covering various locations from the center to the corners of the chip. The experimental measurements from the 3

4 center sensor are reported in the paper. However, it was noted that none of the other temperature sensors showed any increase in temperature compared to the baseline when the TEC was inserted. This implies that the addition of the TEC does not hurt the thermal performance at other locations, while cooling down the hot-spot. The superlattice thermoelectric material was characterized by various techniques including Hall Effect measurements for electrical resistivity, Seebeck coefficient measurements, thermal conductivity measurements, and direct measurement of the device ZT by the Harman technique S10. Some of the measured quantities are given below in Table S2. These are average values based on separate measurements on the p- and n-type superlattice thermo-elements. These values give an intrinsic ZT of ~2.1 at 300K. The effective thermal conductivity of the thermoelectric cooler module was calculated to be ~ 17 W/m-K based on volume averaging over the superlattice thermoelectric material and the metal contact pads on either side. However it is to be noted that in the numerical model, the metal pads and the superlattice are modeled separately with appropriate interfacial resistances and material properties. The bulk averaged property of the TEC module is calculated to just show that it is much higher than the effective thermal conductivity of the TIM. Also, the power through the thermoelectric cooler at the optimum current of 3A was measured to be ~7W. Note that a part of the 60W background power also goes through the TEC. Through thermal modeling (next section) we found that the total heat passing through the cold side is ~13W (i.e. ~11 W background power also goes through the thermoelectric cooler) at 3A current, while providing active cooling of about 7.5 o C. 4

5 Table S2 Values of superlattice material properties obtained from separate experiments Property Seebeck coefficient (α) Electrical resistivity (ρ) Thermal conductivity (k) Value 301 µv/k Ω-m 1.2 W/m-K Numerical modeling technique We also performed numerical modeling to understand the theoretical cooling potential and the non-idealities, while the TEC is in operation inside the chip package using a compact model of the device. The model for the TEC is illustrated in the inset in Fig. S1a. The entire 7 7 array of p-n couples was modeled using three layers to represent the superlattice thermoelectric structure and the metal contact pads on either side. Volume averaged thermal and electrical properties were assigned to these elements based on the detailed TEC structure, consistent with the fabrication steps in Fig. 2. The properties of the superlattice that were used in the simulation are given in Table S2. These are average values based on actual measurements on the p- and n-type superlattice thermo-elements. The thermal model itself was based on thermoelectric equations that are well-known in the literature S11. One significant feature of this model was the addition of contact resistance (both electrical and thermal) terms both at the solder interface between the thermoelectric cooler and the integrated heat spreader and also at the interfaces between the superlattice and the metal contacts as shown in Fig. S1a. 5

6 The accuracy of the model was verified by simulating the temperature of the no TEC baseline case in Fig. 3a by assuming a k TIM of 1.75 W/m-K as discussed earlier. Temperature from the thermal model was in excellent agreement with the experimentally measured value. The model was then modified to include the thermoelectric cooler itself. The electrical contact resistance of Ω-m 2 at the superlattice-metal interface was measured using TLM measurements on contact metals evaporated on the superlattice structures. The corresponding thermal contact resistance was estimated at 10-6 m 2 -K/W based on the Wiedemann-Franz Law. The value of the thermal contact resistance between the thermoelectric cooler and the integrated heat spreader was then extracted from the model by matching the model with measured temperature from the passive cooling experiment (zero current in the device). Once the thermal contact resistance between the thermoelectric cooler and integrated heat spreader was known the only remaining unknown was the electrical contact resistance at that interface which was then obtained by matching the model with the experimental data for the active cooling experiment at current of 3A. The resulting model fit is plotted in Fig. 3a. 6

7 a TEC TIM Substrat e IHS Test chip Substrate Convective cooling with a fan heat-sink Spacer Metal contact Superlattice Metal contact Solder contact resistance Interfacial contact resistance b Background heater Metal traces Localized heater Temperature sensor Figure S1 Details of the test geometry. a, Cross-section of the electronic test package with the TEC attached to the underside of the integrated heat spreader. The inset illustrates the basic thermoelectric device structure with the superlattice material sandwiched between metal contact pads on either side. The heaters and temperature sensors are located at the bottom of the silicon test chip. There are a total of 25 temperature sensors on the chip but only one is shown here for clarity. b, Schematic layout of the silicon test chip showing the metal traces that make up the heater structures. 7

8 References for Supplementary Information S1. Fan, X. et al. SiGeC/Si superlattice microcoolers. Appl. Phys. Lett. 78, (2001). S2. Y. Zhang et al. Experimental characterization of bonded microcoolers for hot spot removal. Proc. InterPack 2005, July 17 22, San Francisco, CA (2005). S3. Bulman, G.E., Siivola, E., Shen, B., & Venkatasubramanian, R. Large external T and cooling power densities in thin-film Bi 2 Te 3 -super-lattice thermoelectric cooling devices. Appl. Phys. Lett. 89, (2006). S4. Harman, T.C., Taylor, P.J., Walsh, M.P. & LaForge, B.E. Quantum dot superlattice thermoelectric materials and devices. Science 297, (2002). S5. Böttner, H. et al. in Thermoelectrics Handbook: Macro to Nano, D.M. Rowe, Ed., 46-1 (CRC Press, Boca Raton, FL, 2006). S6. Semenyuk, V. Miniature thermoelectric modules with increased cooling power International Conference on Thermoelectrics (IEEE, Piscataway, NJ, 2006), pp S7. Chang, J-Y., et al. Convective performance of package based single phase microchannel heat exchanger. Proc. InterPack 2005, July 17 22, San Francisco, CA (2005). S8. Goh, T.J., Seetharamu, K.N., Quadir, G.A, Zainal, Z.A. & Ganeshamoorthy, K.J. Thermal investigations of microelectronics chip with non-uniform power distribution: temperature prediction and thermal placement design optimization. Microelectronics International 21, (2004). S9. Prasher, R. Thermal interface materials: historical perspective, status, and future directions. Proc. IEEE 94, (2006). S10. Venkatasubramanian, R., Siivola, E., Colpitts, T. & O Quinn, B. Thin-film thermoelectric devices with high room-temperature figures of merit. Nature 413, (2001). 8

9 S11. Goldsmid, H.J. in CRC Handbook of Thermoelectrics (ed. Rowe, D.M.) (CRC Press, Boca Raton, FL, 1995). 9

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