Lecture 9. Strained-Si Technology I: Device Physics

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1 Strain Analysis in Daily Life Lecture 9 Strained-Si Technology I: Device Physics Background Planar MOSFETs FinFETs Reading: Y. Sun, S. Thompson, T. Nishida, Strain Effects in Semiconductors, Springer, 010. multiple research articles (reference list at the end of this lecture)

2 Mechanical Stress/Strain Analysis Stress: results from the repulsive electromagnetic force between ionic cores when the lattice atoms deviate from their equilibrium positions. Stress = lim F s F n L Strain = lim L Extensional Stress Types Shear Stress Tensor Tensile Compressive

3 Strain-Stress Relationship Elasticity Tensor: assuming strain has linear response to stress (Hooke s Law) can be simplified into 3 independent variables, for cubic lattices (e.g. Si) If x, y, z along main crystal axis: OR for a certain direction: Extensional Strain/Stress Shear Strain/Stress 3

4 Impact of Strain on Semiconductors Energy Band Splitting Evs. k curvature change Si Ge w/o s CB VB w/ hs w/ us 4 HH LH GaAs Unstrained 1GPa <110> Compressive Y. Sun, JAP (007) 4

Strain Impact on Si Bandstructure: Planar N-MOSFET Unstrained Longitudinal Vertical Electrons Δ Electron Gate Gate Gate [110] Source Drain Source Drain Source Drain Lower DOS available for

5 Strain Impact on Si Bandstructure: Planar N-MOSFET Unstrained Longitudinal Vertical Electrons Δ Electron Gate Gate Gate [110] Source Drain Source Drain Source Drain Lower DOS available for Scattering Reduced (Inter-valley) Scattering Rates Energy Splitting applying strain Sub-band reoccupation Lowered average m * E-k Curvature Change Transport m * Reduction K. Uchida, IEDM (008) 5

Strain Impact on Si Bandstructure: Planar P-MOSFET [110] Gate Gate Gate Source Drain Source Drain Source Drain Unstrained Longitudinal Vertical Holes Heavy Hole Light Hole Split-off Hole Lower

6 Strain Impact on Si Bandstructure: Planar P-MOSFET [110] Gate Gate Gate Source Drain Source Drain Source Drain Unstrained Longitudinal Vertical Holes Heavy Hole Light Hole Split-off Hole Lower DOS available for Scattering Reduced (Inter-sub-band) Scattering Rates Energy Splitting applying strain Sub-band reoccupation Lowered average m * E-k Curvature Change Transport m * Reduction 6

7 Strain Enhancement on Si MOSFET Carrier Mobility [110] Electron Hole D. Esseni, JCE (009) F. Conzati, SSE (009) For N-MOSFET, electron mobility enhancement saturates at ~1.5 GPa <110>-uniaxial tensile stress. For P-MOSFET, hole mobility enhancement saturates at very high <110>-uniaxial compressive stress. 7

8 Impact of Quantum Confinement Electrons under Biaxial Tensile Stress Holes under Uniaxial Comp. Stress O. Weber, IEDM (007) E. X. Wang, TED (006) N-MOSFET: e % degrades at higher E eff, due to the quantum confinement counters the strain-induced sub-band splitting. P-MOSFET: h % maintains vs. E eff due to the dominant m * reduction. 8

9 Analytical Modeling for Carrier Mobility Enhancement due to Strain Piezoresistance (PR) Model Sub-band Reoccupation Model Too simple Limited predictive ability (by ignoring E eff, Straindependence ) J.-S. Lim, EDL (004) Analytically models the energy-band top and m * change vs. strain Trade-off between computing loads and accuracy 10/5/013 9 Nuo Xu EE 90D, Fall 013

10 Numerical Approach: Self-Consistent Poisson-Schrödinger Simulation scps Approach Schrödinger equation d e() z () () * n z Enn z m z dz g n nn( z) dk f( E ) (, ) k n k z k nz ( ) nn( z) n d d( z) ( z) en D NA pz ( ) nz ( ) dz dz Poisson equation 6x6 Luttinger-Kohn Hamiltonian for Holes L PQ L M 0 M 3 L PQ 0 M Q L 3 M 0 PQ L L Q L 0 M L PQ M L 3 Q L M P 0 3 L M L Q 0 P P k k k m 0 0 1( x y z) Q k k k m 0 ( x y z) L 3 3( k ik ) k m 0 x y z M 3[ ( kx ky) i 3kxky) m Impacts of strain on energy-band top as well as curvature change will be completely included into the Hamiltonian. Computationally intensive. 10

11 Impact of Si Body Thickness Scaling Electron Mobility ( cm /V.s) [110] N-Channel (Electron) 1GPa Longitudinal Tensile 1GPa Vertical Compressive Unstrained (100)/<110> N inv =1.0e13cm Silicon Film Thickness (nm) scps simulations, N. Xu, VLSI-T (011) Electron Mobility Change ( e e ) Hole Mobility ( cm /V.s) P-Channel (Hole) (100)/<110> 1GPa Longi. Comp. 1GPa Verti. Tens. 1GPa Trans. Tens. Unstrained P inv =1.0e13cm Silicon Film Thickness (nm) Stress enhancement diminishes for electrons as t SOI scaled below 5nm, but not for holes Hole Mobility Change ( h h ) 11

12 Piezo-Coefficient (10-11 Pa -1 ) Impact of t Si Scaling on Piezoresistive [110] 0 zz 0 Coefficients Open symbols Simulated Closed Symbols Measured N-Channel (Electron) yy xx Vertical zz Transverse yy Longitudinal xx Uchida, IEDM 04,08 Xu, VLSI Silicon Body Thickness (nm) N. Xu, SOI Conf. (01) P-Channel (Hole) -0 yy -40 zz Silicon Body Thickness (nm) 1 Piezo-Coefficient (10-11 Pa -1 ) xx Longitudinal xx Transverse yy Vertical zz Uchida, IEDM 08 Xu, VLSI 11 As t Si decreases, Π xx decreases due to diminished sub-band reoccupation and inter-valley scattering reduction.

13 [110] Strain Enhancement on FinFET Carrier Mobility: Electrons (110)-sidewall N-FinFET Unstrained Strained (100)-sidewall N-FinFET 4, nd,1 st 4, 1 st (110)-sidewall N-FinFET N. Serra, TED (010) 13

14 Strain Enhancement on FinFET Carrier Mobility: Holes Equi-energy contours from the 1 st HH Planar MOSFET (100)/<110> (100) Surface [110] FinFET (110)/<110> [110] (110) Surface unstrained σ x = -1 GPa Courtesy of L. Smith (Synopsys) 14

15 Piezo-Coefficient (10-11 Pa -1 ) [110] Impact of Fin Width Scaling on Piezoresistive Coefficients Open symbols Simulated Closed Symbols Measured N-Channel (Electron) zz Xu, EDL 1 Serra, TED 10 yy xx Saitoh, VLSI 08 Shin, EDL 06 Suthram, EDL Silicon Fin Width (nm) P-Channel (Hole) No substantial degradation in piezo-resistance is seen with decreasing fin width. Piezo-Coefficient (10-11 Pa -1 ) xx Xu, EDL 1 Saitoh, VLSI 08 Krishinamohan, IEDM 08 Suthram, EDL 08 zz yy N. Xu, SOI Conf. (01) Silicon Fin Width (nm) 15

<100> CESL (Uniaxial) <100> Biaxial Tensile <110> CESL (Uniaxial) <110> Biaxial Tensile Open: H Si = 58nm, W Si = 0nm Filled: H Si = 0nm, W Si = 58nm 100 0 00 400 600 800 1000

16 Impact of Fin Aspect-Ratio scps simulations, N. Xu, IEDM (010) N-Channel (Electron) P-Channel (Hole) 400 N inv = 9x10 1 cm Open: H Si = 58nm, W Si = 0nm Filled: H Si = 0nm, W Si = 58nm Electron Mobility (cm /Vs) <100> CESL (Uniaxial) <100> Biaxial Tensile <110> CESL (Uniaxial) <110> Biaxial Tensile Open: H Si = 58nm, W Si = 0nm Filled: H Si = 0nm, W Si = 58nm Stress (MPa) μ n is highest for <100> uniaxial-strained Tri-Gate, μ p is highest for <110> uniaxial-strained Tri-Gate at high level stress. Hole Mobility (cm /Vs) CESL(Uniaxial) Biaxial Compressive Biaxial Tensile <110> Fin Stress (MPa) P inv =1x10 13 cm - 16

17 Strain Enhancement on Short-Channel MOSFET Performance Stress-induced Enhancement (%) Mobility vs. Gate Length Long Channel +1% short channel % I d,lin % Gate Length (nm) Expt. results, N. Xu, VLSI-T (011,01) 300K P inv =9.5e1cm I d,lin V ds =10mV (%) Enhancement in apparent mobility is maintained vs. L g scaling. ~50% of Δµ/µ can be transferred to ΔI ON /I ON. 17 I on V ds =1V (%) ΔI ON /I ON vs. Δi dlin /I dlin under strain p-channel FDSOI L g = 30nm ~ 80nm P inv =7.0e1cm - Forward Back Bias V back = -0.5 ~ -1.0V Wafer Bending S xx = -70 ~ -170MPa S = 0.59 S = 0.54

18 References 1. Y. Sun et al., Physics of Strain Effects in Semiconductors and metal-oxide-semiconductor fieldeffect transistors, Journal of Applied Physics, 101, , F. Conzati et al., Drain Current Improvements in Uniaxially Strained P-MOSFETs: A Multi-Subband Monte Carlo Study, Solid-State Electronics, vol.53, pp , D. Esseni et al., Semi-Classical Transport Modeling of CMOS Transistors with Arbitrary Crystal Orientations and Strain Engineering, Journal of Computational Electronics, vol.8, pp.09-4, N. Xu et al., Stress-induced Performance Enhancement in Ultra-Thin-Body Fully Depleted SOI MOSFETs: Impacts of Scaling, Symposium on VLSI Technology Dig., p , K. Uchida et al., Physical Mechanisms of Electron Mobility Enhancement in Uniaxial Stressed MOSFETs and Impacts of Uniaxial Stress Engineering in Ballistic Regime, IEEE International Electron Device Meeting, Tech. Dig., p.9-3, K. Uchida et al., Carrier Transport and Stress Engineering in Advanced Nanoscale Transistors From (100) and (110) Transistors To Carbon Nanotube FETs and Beyond, IEEE International Electron Device Meeting, Tech. Dig., p , N. Serra et al., Mobility Enhancement in Strained n-finfets: Basic Insight and Stress Engineering, IEEE Transactions on Electron Devices, vol.57, p , T. Krishnamohan et al., Comparison of (001), (110) and (111) Uniaxial- and Biaxial- Strained-Ge and Strained-Si PMOS DGFETs for All Channel Orientations: Mobility Enhancement, Drive Current, Delay and Off-State Leakage, IEEE International Electron Device Meeting, Tech. Dig., p , M. Saitoh et al., Three-Dimensional Stress Engineering in FinFETs for Mobility/On-Current Enhancement and Gate Current Reduction, Symposium on VLSI Technology Dig., p.18-19, K. Shin et al., Study of Bending-Induced Strain Effects on MuGFET Performance, IEEE Electron Device Letters, vol.7, p ,

19 References 11. S. Suthram et al., Comparison of Uniaxial Wafer Bending and Contact-Etch-Stop-Liner Stress Induced Performance Enhancement on Double-Gate FinFETs, IEEE Electron Device Letters, vol.9, p , J.-S. Lim et al., Comparison of Threshold Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed n-mosfets, IEEE Electron Device Letters, vol.5, no.11, pp , E. X. Wang et al., Physics of Hole Transport in Strained Si MOSFET Inversion Layers, IEEE Transactions on Electron Devices, vol.53, no.8, pp , O. Weber et al., Examination of Additive Mobility Enhancement for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge Channel MOSFETs, IEEE International Electron Device Meeting, Tech. Dig., p.719-7, N. Xu et al., MuGFET Carrier Mobility and Velocity: Impacts of Fin Aspect Ratio, Orientation and Stress, IEEE International Electron Device Meeting, Tech. Dig., p , N. Xu et al., Impact of Back Biasing on Carrier Transport in Ultra-Thin Body and BOX (UTBB) Fully Depleted SOI MOSFETs, Symposium on VLSI Technology Dig., p ,

Courtesy of S. Salahuddin (UC Berkeley) Lecture 4

Courtesy of S. Salahuddin (UC Berkeley) Lecture 4 MOSFET Transport Issues semiconductor band structure quantum confinement effects low-field mobility and high-field saturation Reading: - M. Lundstrom,