Thermo-structural Model of Stacked Field-programmable Gate Arrays (FPGAs) with Through-silicon Vias (TSVs)

Transcription

1 Manuscript for Review Thermo-structural Model of Stacked Field-programmable Gate Arrays (FPGAs) with Through-silicon Vias (TSVs) Journal: Electronics Letters Manuscript ID: draft Manuscript Type: Letter Date Submitted by the Author: Complete List of Authors: Zhang, Chunbo; Utah State University, Mechanical & Aerospace Engineering Dasu, Aravind; Utah State University, Electrical and Computer Engineering Li, Leijun; Utah State University, Mechanical & Aerospace Engineering Keywords: 3-D circuits, SOLID MODELLING, THERMAL ANALYSIS

2 Page 1 of 9 Thermo-structural Model of Stacked Fiel d- programmabl e Gate Arrays (FP GAs) wi th Throughsilicon Vias (TSVs) C. Zhang, A. Dasu, and L. Li 1 Micron Research Center, Utah State University A new 3-D full-scale thermo-structural finite element model of two-stack FPGA with TSVs, which is developed from an experimentally validated single-stack FPGA model, is proposed. Typical 3-D distributions and evolutions of temperature and von Mises stress on both the active layers and TSVs are presented. Introduction: 3-D chip stacking offers a much higher level of silicon integration where orders of magnitude I/O density advancement may be possible [1]. It is believed that through silicon via (TSV) interconnection is the ultimate way for 3-D die stack application. Copper-through-via interconnection offers the shortest wiring length between dies, thereby leading to higher chip performance. TSVs are formed by mechanical drilling, laser drilling, or dry etching, followed by deposition of a layer of SiO 2 or Si 3 N 4 for electrical insulation. The via is then filled with chemical vapor deposition (CVD) of tungsten or copper, or electrochemical deposition (ECD) of copper. Induced stresses in 3-D circuits are known to affect transistor performance by the piezo-resistive effects. TSVs may impact on the performance of 1 Department of Mechanical and Aerospace Engineering, Utah State University, 4130 Old Main Hill, Logan, Utah , USA; leijun.li@usu.edu 1

3 Page 2 of 9 transistors that are close to them because of the high stresses from coefficient of thermal expansion (CTE) mismatch between copper and silicon. Thus, the successful application of 3-D integration requires significant thermo-structural analysis. Several authors have used finite element method for insights on the temperature and stress distributions in 3-D multi-stack circuits [2-3]. The thermo-structural characteristics of stacked field-programmable gate array (FPGA) with TSVs have rarely been studied. The objective of this work is to identify and predict 3-D temperature/stress for typical TSV designs and reliability estimations with a new finite-element model. For design consideration, the influence of TSV s material, geometry, and position on temperature/stress fields under different thermal cycling conditions can be studied using the developed model. Finite Element Model: Considering the symmetry of the chip, a 3-D quartersize thermo-structural coupled finite element model has been developed based on the experimentally determined configuration and dimensions of the FPGA (Xilinx Spartan 3E-250K), shown in Fig. 1(a). This layer-structured chip is composed of, following a sequence from bottom to top and represented by different colours, epoxy mold, copper heat spreader, substrate attachment, silicon substrate, bottom device layer, in-between silicon layer, and top device layer. The Si substrate has a thickness of 280 µm, and for the two active layers each has a thickness of 10 µm. It is assumed that the two active device layers are bonded together with a face-to-back configuration, sandwiching a thinned substrate layer underneath the top device layer. Nine through silicon vias (TSVs) are inserted to connect the two active device layers. Although 2

4 Page 3 of 9 various TSV structures have been reported or proposed, the mainstream configuration is cylindrical. Fig. 1(b) illustrates the fine meshed annular copper TSVs and connection pads. All the TSVs have a uniform dimension of 50 µm diameter and 100 µm length. The space between TSVs is 500 µm. Since there is no reference about the dimensions of the Cu pads in FPGA, it is assumed to be 100 µm square plate according to other types of 3-D circuits. The 3-D 10-node coupled-field element (Solid227) is chosen during mesh generation. For simplicity, mechanical and thermal properties of different material are assumed to be constant. This new two-device layer model is based on a single layer model that has been verified by thermocouplemeasured temperature [4]. Conductive heat flow is included in the finite element model and the governing equation is as follows: # T r r $ c ( + ( v "!) T ) = q& +! " (( K "!) T ) (1) # t where " is density, c is specific heat, T is temperature, t is time, r v is the velocity vector for mass transport of heat, q& is the heat generation rate per unit volume, r K is the conductivity vector, and " = # #x + # #y + # #z. The exposed surfaces are subject to the convective heat flow that is calculated by: {q} T {"} = h f (T S # T B ) (2) 3

5 Page 4 of 9 where q is heat flux vector, " is unit outward normal vector, h f is film coefficient, T B is bulk temperature of the adjacent fluid, T S is temperature at the surface of the model. The stress caused by the thermal strain is calculated by: el {' } = [ D]{ & } el th {& } = {& } # {& } {& th } = $ T $ T = T # T se se se T!% x % y % z 0 0 0" ref (3) where {"} is stress vector, [D] is elastic stiffness matrix; {"}, {" el }, and {" th } are the total, elastic, and thermal strain vectors, respectively; T is the current temperature at the point in question; T ref is reference (strain-free) se temperature; " x,y,z is secant coefficient of thermal expansion in the x, y and z directions. A fixed boundary is applied to the bottom surface of the chip. The cut surfaces for the quarter-chip model are set with the symmetric boundary conditions, with no displacement and heat flow along the direction normal to symmetric planes. The convective boundary conditions are used on all the surfaces exposed to the air. The TSVs are subjected to a heat flux generated on the active layers, which is 2.35 W for the condition of 100% slices utilization, clocked at 100MHz and all look up tables (LUTs) and flip-flops (FFs) toggling at the maximum possible rate for the modelled device [4]. It is assumed that the working units are uniformly distributed on the active layers, thus the heat flux generated by the units is also evenly distributed. 4

6 Page 5 of 9 Simulation Results: A higher temperature zone exists at the centre of the active layer, in Fig. 2(a), because of the worst heat dissipation condition at the centre. In regions close to TSVs, more heat can be dissipated compared with surrounding areas since the thermal conductivity of Cu is higher than Si. The von Mises stress concentrates on the interface of the active layers and Cu pads, illustrated in Fig. 2(b), which can be explained by the large CTE mismatch between the copper and the silicon. The stress level is high enough to cause possible fracture in the silicon or delaminating at the interface of the copper/silicon materials. Reliability problems such as electrical breakdown may occur. Similarly, the average temperature at TSVs decreases when the TSVs are located further away from the chip centre, shown in Fig. 3(a). Fig. 3(b) illustrates the 3-D von Mises stress distributions on TSVs. The maximum stress in TSVs is located near the connection between the TSVs and Cu pads, an area for possible debonding failure in the through-wafer copper interconnects. The sharp angle between the TSV and Cu pad (90 ) causes a high stress level, which could be harmful. Therefore, proper design of connection shape is required to reduce the stress level and improve the chip reliability. A possible solution reported is the tapered opening of vias made by gradient DRIE (Deep Gradient Ion Etching). Such design has produced a better high-frequency signal transmission performance [5]. Both the temperature field on the active layers and the thermal stress field on the TSVs have a saturation state, illustrated in Fig. 4. The peak temperature on active layers saturates at 133 C for the condition of 2.35 W thermal power. 5

7 Page 6 of 9 Because of the high thermal conductivity of Cu and Si, little temperature difference between the bottom and top active layers can be found (Fig. 4(a)). Fig. 4(b) shows the evolution of distribution band of maximum von Mises stress in TSVs. As can be observed, the maximum stresses increase to constant values ranging from 407 MPa to 431 MPa depending on TSV locations. Conclusions: A new full-scale 3-D thermo-structural finite element model of two-stack FPGAs with TSVs has been developed. With this model, typical thermo-structural characteristics, including 3-D temperature and stress fields and profiles, have been identified. This model can be applied to study the effects of TSV parameters on thermo-structural fields and its optimization for FPGA design. References 1 Knickerbocker, J.U., Patel, C.S., Andry, P.S., Tsang, C.K., Buchwalter, L.P., Sprogis, E.J., Gan, H., Horton, R.R., Polastre, R.J., Wright, S.L., and Cotte, J.M.: 3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias. IEEE Journal of Solid-state Circuits, August 2006, Vol. 41, No. 8, pp Hsieh, M.C., and Yu, C.K. : Thermo-mechanical Simulations For 4-Layer Stacked IC Packages. 9th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro- Systems, 2008, EuroSimE 3 Takana, N., Sato, T., Yamaji, Y., Morifuji, T., Umemoto, M., and Takahashi, K. : Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module. Electron. Comp. and Tech. Conf Zhang, C., Kallam, R., Deceuster, A., Dasu, A., and Li, L. : A Thermalmechanical Coupled Finite Element Model with Experimental Temperature Verification for Vertically Stacked FPGAs. Microelectronic Engineering, 2009, under review 5 Zhao, L., Liao, H., Miao, M., and Jin, Y. : Design and Analysis of an I- shaped TSV Structure for 3D SiP.10th Electronics Packaging Technology 6

8 Page 7 of 9 Conference, 2008, pp Figure captions: Fig. 1 (a) 3-D quarter-size thermo-structural model for two-stack FPGAs; (b) Meshed TSVs Fig. 2 (a) Temperature distribution on the bottom active layer (t=4s, ºC); (b) Von Mises stress distribution on the bottom active layer (t=4s, MPa) Fig. 3 (a) Temperature distribution on TSVs (t=4s, ºC); (b) Von Mises stress distribution on TSVs (t=4s, MPa) Fig. 4 (a) Temperature evolutions of active layers; (b) Distribution band of maximum von Mises stress evolution in TSVs 7

9 Page 8 of 9 Figure 1 (a) (b) Figure 2 (a) (b) 8

10 Page 9 of 9 Figure 3 (a) (b) Figure 4 (a) (b) 9