EV Group. Engineered Substrates for future compound semiconductor devices

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1 EV Group Engineered Substrates for future compound semiconductor devices

2 Engineered Substrates HB-LED: Engineered growth substrates GaN / GaP layer transfer Mobility enhancement solutions: III-Vs to silicon (e.g. GaAs, GaP, InP, GaN) GOI (Germanium on Insulator) ssoi (strained silicon on insulator) SOS (Silicon on Sapphire) SOI (Silicon on Insulator) Heterogeneous integration: Optical solutions on silicon MEMS on silicon Thermal management: Silicon on Silicon Carbide Silicon on Diamond Multi-Junction solar cells Courtesy of OSRAM OS Courtesy of Soitec Courtesy of J. Bowers UCSB Novel applications such as graphene, spintronics, Courtesy of RIT Courtesy of D. Awschalom UCSB EV Group Semicon Europa

3 Integration of Compound Semiconductors Hetero- Epitaxy CS growth on dissimilar substrates (e.g Si) Dissimilar crystal and physical parameters High dislocation densities of the grown films Wafer bonding Layer transfer from growth wafers to a functional substrate Hybrid Integration Integration of multiple CS materials by epitaxial growth & layer transfer EV Group Semicon Europa

4 Integration of Compound Semiconductors cont d Problem Different states in manufacturing and operation demand different substrates properties: Structural properties (lattice matching, thermal expansion, etc.) Electrical properties Mechanical properties Engineered Substrates Creating a substrate with unique, combined properties as desired for the further processing Joining materials of different properties Altering the material properties by pre-treatment EV Group Semicon Europa

5 Outline EV Group Semicon Europa

6 Outline Direct wafer bonding for compound semiconductor layer transfer and growth substrate manufacturing Temporary bonding for thin wafer/film handling of compound semiconductors EV Group Semicon Europa

7 HB-LEDs GaN on sapphire or silicon Problem Hetero epitaxy of GaN on sapphire or silicon results in a high density of threading dislocations, due to: Lattice mismatch CTE mismatch Solutions Patterned sapphire substrates Pendeo epitaxy / ELOG Chung et al. Appl.Phys.Lett. 95 (2009) EV Group Semicon Europa

8 Patterned Sapphire Substrates (PSS) Improved GaN quality with higher efficiency Increased light extraction efficiency Faster etching with smaller PSS features Faster coalescence for following epitaxial growth step Clear Clear trend trend is is visible visible to to move move from from micron-sized features to to sub-micron features Adapted H. Kuo, NCTU EV Group Semicon Europa

9 Pendeo-Epitaxy / Epitaxial Layer Overgrowth Hard mask GaN seed layer GaN etching Substrate (SiC, Si, etc) GaN overgrowth AlGaN overgrowth K.J. Gehrke et al, MRS Internet J. Semicond. Res. (1999) 4S1, G3.2 EV Group Semicon Europa

10 UV NIL Process flow Nanoimprint Lithography (NIL) (NIL) enables the the cost-efficient, large large area area generation of of micro- micro-and nanometer scale scale growth growth structures. EV Group Semicon Europa

11 UV NIL Process flow UV - Nanoimprint Lithography (UV-NIL, UV Molding) Benefits of UV-NIL with soft stamps: - Micro- and nano-features in one imprint - Achieved Resolution: < 15nm - Low CoO with soft stamp technology - 3D structures Master provided by NILT

12 From R&D to HVM Equipment Portfolio HVM UV-NIL THERMAL NIL R&D

13 Photon management θ in > θ crit θ in > θ crit n 1 n 2 n 1 n 2 HB-LEDs Light extraction features like PhCs on the LED surface results in: Higher extraction efficiency Extraction of lower order modes Direction of extracted light (quasi periodic PhCs) Photovoltaics Texturization increases the cell efficiency due to: Reduced reflectivity Deflection of incoming light resulting in light trapping Nanoimprint Lithography (NIL) (NIL) enables innovative surface surface textures for for photon photon management.

14 Outline Nanoimprint lithography (NIL) for growth enhancement structures Direct wafer bonding for compound semiconductor layer transfer and growth substrate manufacturing Temporary bonding for thin wafer/film handling of compound semiconductors

15 Overview Wafer Bonding Processes

16 Ex situ process flow Mechanical alignment accuracy ~50µm Optical alignment accuracy ~1µm Applications - Substrates manufacturing (SOI, GOI, SSOI, etc.) - Engineered substrates - MEMS (e.g. 3D assembly, packaging, capping) - 3D interconnects

17 SOI by Wafer Bonding Bonding interface Bonded SOI wafers (SOITEC - FRANCE) Cross section TEM image of a bonded SOI substrate.

18 High mobility logic application InGaAs carries high potential for the n-mos transistor in future CMOS High mobility requirements are closely tied to the structural material properties Low annealing budget after bonding (InGaAs damage) Plasma-activated fusion bonding TEM cross section of InGaAs channel bonded to a silicon carrier Takagi et al. VLSI Summit 2010

19 InP-based Si photonics Challenge: Silicon s indirect band-gap results in emission of phonons (heat) Photon generation internal quantum efficiency is as low as 1:10 6 Room-temperature applications demand the integration of III-Vs with silicon Solution: Wafer bonding of III-Vs (e.g. InP) on silicon Plasma activation for low temperature bonding (SOI wafer manufacturing and InP to silicon bonding) Liang et al. Nature Photonics 4 (2010) 511 Bowers, Optics & Photonics News, May 2010, p.28

20 Engineered Growth Substrates GaN and sapphire feature around 16% lattice mismatch (RT) Sapphire prices expected to increase by ~40% in 2011 Courtesy of Soitec Highly lattice & CTE matched substrates for epitaxial growth of GaN with low defect density Increased throughput Higher internal quantum efficiency Improved yield and lower binning Courtesy of J. Bowers / UCSB

21 Outline Nanoimprint lithography (NIL) for growth enhancement structures Direct wafer bonding for compound semiconductor layer transfer and growth substrate manufacturing

22 Thin wafer processing Thinning

23 Thin wafer processing Temporary bonding and debonding Enables utilization of existing equipment and existing processes (Back thinning, TSV formation, backside metallization, etc..)

24 Conclusion Engineered substrates are gaining importance with the increasing market size of compound semiconductor devices. Different technologies for the creation of engineered substrates have been introduced: Nanoimprint Lithography Wafer bonding Temporary bonding Engineered substrates will play an important role for the implementation of compound semiconductors on silicon. Monolithic device layouts Higher integration and miniaturization Engineered growth substrates for HB-LEDs offer a high potential for increasing efficiency, higher crystal quality and reduced binning.

25 EV Group