EE 292L : Nanomanufacturing. Week 5: Advanced Process Technology. Oct

Transcription

1 EE 292L : Nanomanufacturing Week 5: Advanced Process Technology Oct Advanced Process Technology 1 HAR etch 2 3 HAR Gapfill Metal ALD 4 Reflow 5 6 SAC Airgap 7 8 Strain Ge/III-V Engineering High-k / ALD Metal gate 2 EE292L: Aneesh Nainani 1

2 Deep Trenches & Skyscrapers Mariana Trench Burj Khalifa 3 Deep Trenches & Skyscrapers Mariana Trench H = 2550 km W =70 km AR = H/W = 2550/70 ~ 37 4 EE292L: Aneesh Nainani 2

3 Deep Trenches & Skyscrapers Burj Khalifa H = 828 m W av =100 m W bot =175 m 1.5B USD AR = H/W = 828/100 ~ B USD 5 Deep Trenches & Skyscrapers: DRAM H = 2000nm W =30nm AR = H/W = 2000/30 ~ 67 6 EE292L: Aneesh Nainani 3

4 7 8 EE292L: Aneesh Nainani 4

5 Deep Trenches & Skyscrapers: NAND Along WL H = 217m W =20-30nm AR ~ 10 Non scaling of STI depth due to no voltage scaling No voltage scaling due to no Tox scaling 9 Deep Trenches & Skyscrapers: FinFET AR ~ 5-10 TSMC, IEDM 10 Fin height to be tall for isolation Width small to ensure good gate control with L G scaling 10 EE292L: Aneesh Nainani 5

6 Deep Trenches & Skyscrapers: TSV TSV + 3-D Stacking <10 um System-in-Package SoC Package DRAM SoC AR ~ Width to be small to reduce keep out zone / layout penalty Height determined by wafer thickness 11 1 HAR etch High Aspect Ratio Etch Specs Vertical sidewall High anisotropy / selectivity No sidewall damage Effects : Charging Limited flux at higher depth 12 EE292L: Aneesh Nainani 6

7 1 HAR etch Aspect Ratio Dependent Etch 13 Deep Trenches & Skyscrapers: TSV Bosch process : borrowed from MEMS Cyclic : passivation and etching Fast 1 HAR etch 14 EE292L: Aneesh Nainani 7

8 Bosch Etch: TSV 1 HAR etch Looks like the outer surface of a screw 15 Pattern Collapse Stacked Capacitor DRAM Pattern collapse of HAR structures major yield limiter 16 EE292L: Aneesh Nainani 8

9 Pattern Collapse Fundamental Yield Limiter for Planar NAND --Structure deformation Design Rules define d and L. Nothing we can do about this HAR Gapfill Ideal world bottom step coverage = 1 side step coverage = 1 18 EE292L: Aneesh Nainani 9

10 2 HAR Gapfill High Aspect Ratio Fill: PVD? Physical vapor deposition (PVD) : Evaporation, Sputtering conventional metal deposition technique: widely used for Al interconnects produces Cu films with strong (111) texture and smooth surface, in general poor step coverage: not tolerable for filling high-aspect ratio features Deposited film 19 2 HAR Gapfill CVD with low S c Reactant transport at low pressure Mean free path >> interconnect dimension Sticking Coefficient Shadowing of the direct flux by the walls reduces the flux at the bottom corners of a via or a trench resulting in thinner deposition Lower Sc increases the number of bounces, increasing the probability of deposition precursors reaching the bottom. This, improving step coverage 20 EE292L: Aneesh Nainani 10

11 2 HAR Gapfill Step Coverage in PVD & CVD CVD W used extensively for via filling 21 2 HAR Gapfill ALD Pros Ideal sidewall coverage Cons : Slow High R films Carbon contamination 22 EE292L: Aneesh Nainani 11

12 4 Reflow Reflow Capillary action 23 4 Reflow Reflow Reflow being adapted for BEOL Cu 24 EE292L: Aneesh Nainani 12

13 Questions? 25 Parasitics : R and C we don t need 26 EE292L: Aneesh Nainani 13

14 Parasitics : R and C we don t need Intel 22nm R T = R ch + R par PMOS : R T = 72kΩ/µm NMOS : R T = 64kΩ/µm R par = 20-30kΩ/µm 27 5 SAC No space for contacts! 28 EE292L: Aneesh Nainani 14

15 5 SAC Self Aligned Contact : immunity to misalignment Good old days C B A Tough, but manageable C B1 A B2 B1 C1 Uh oh B2 C2 A2 B3 Overlay complexity is non-trivial to manage A SAC How to make SAC K. Mistry, Semicon EE292L: Aneesh Nainani 15

16 5 SAC Immunity to misalignment K. Mistry, Semicon SAC SAC in NOR flash 45nm NOR 32 EE292L: Aneesh Nainani 16

17 5 SAC SAC in DRAM 65nm DRAM 33 5 SAC SAC bad for parasitics Synopsys 34 EE292L: Aneesh Nainani 17

18 5 SAC SAC bad for parasitics Synopsys 35 Parasitics : R and C we don t need global semiglobal local RC delay drives latency in global interconnects 36 EE292L: Aneesh Nainani 18

19 Parasitics : R and C we don t need 37 Parasitics : R and C we don t need Black are the good capacitances Red are the parasitics Red can be 50% of the overall 38 EE292L: Aneesh Nainani 19

20 6 Airgap Airgap advantages 39 6 Airgap Airgap advantages: Better Electromigration and stress performance Electromigration Cumulative Probability Air-gap Dielectric Hours Air-Gap splits show significantly longer lifetimes than Gapfill split Leakage data indicates no breakdown well above operating voltage. Airgap can absorb this stress Ref: Shieh, et al., IEEE IITC, EE292L: Aneesh Nainani 20

21 6 Airgap Airgap in NAND Reduced FG-FG coupling Tighter VT distribution 41 6 Airgap Airgap using sacrificial polymer Issues : Heating to remove sacrifical polymer Corrosion of metal if wet etch Park, Journal of Electronic Materials, EE292L: Aneesh Nainani 21

22 6 Airgap Airgap using sacrificial polymer Park, Journal of Electronic Materials, Airgap Airgap using non-conformal CVD Issues : Seam formation CMP 44 EE292L: Aneesh Nainani 22

23 6 Airgap Airgaps where we need them Airgap only in the narrow trenches Most needed in narrow trenches 45 6 Airgap Mutilevel Airgap Scheme Issues : Selectivity Collapse Toshiba 46 EE292L: Aneesh Nainani 23

24 Questions? 47 THE interface is THE device 48 EE292L: Aneesh Nainani 24

25 49 THE interface is THE device G S D 90nm : Planar < 1% 22nm : FinFET 10-15% Interface volume : interface area x 1nm 50 EE292L: Aneesh Nainani 25

26 THE interface is THE device Old l A New (scaled) 90nm < 1% 22nm 5-10% Interface volume : interface area x 1nm 1. Semiconductor/dielectric: Gate Stack 2. Metal/metal : BEOL (Cu/TaN) 3. Semiconductor/metal: S/D contact 51 7 Ge/III-V Motivation for Alternate Channel Materials Electron Mobility (cm 2 /V-s) Hole Mobility (cm 2 /V-s) Si Ge InAs Bandgap (ev) Dielectric Constant Melt T (ºC) STI Oxide 52 EE292L: Aneesh Nainani 26

27 Mobility in scaled transistors E eff Electron t ox=35 Å t ox=70 Å eff E eff Hole -2 E eff µ Interface Roughness E eff 1 µm CMOS 0.1 µm CMOS E eff (MV/cm) E eff Mobility at high electric field limited by interface scattering 53 Interface dominates FinFETs with scaling Synopsys 54 EE292L: Aneesh Nainani 27

28 7 Ge/III-V Ge Gate Interface Approaches Si Cap for HfO 2 -based Al 2 O 3 Interface Layer 200 Hole Mobility (cm 2 /V-s) nm Si Cap w/o Si Cap Hole Density (x10 12 cm -2 ) Source: Intel, IEDM 2010 Source: S, 2010 Advantages of high-mobility material limited by poor interface 55 Metal-metal interface Effective resistivity (microohm-cm) Technology Node (µm) Global T=100 0 C T=27 0 C Year Kapur, McVittie & Saraswat IEEE Trans. Electron Dev. April EE292L: Aneesh Nainani 28

29 Quiz Metal B (TaN) Metal A (Cu) R 1 R 2 Metal B (TaN) Metal A (Cu) R = R 1 R 2 /(R 1 +R 2 ) 57 Quiz Feldman, APL 2009 Rossnagel, JVST 2004 Depositing Ta layer on top of copper degrades overall resistance 58 EE292L: Aneesh Nainani 29

30 Thin Film Resistivity: Surface Scattering ρ ρ o = (1 p) l w ρ is the resistivity of thin film ρ o is the resistivity of the bulk p is the fraction of electrons scattered at the surface w is the width of the wire (smallest dimension of the interconnect) l is the mean free path of the bulk material. p = 0 p = 1 Diffuse scattering Lower Mobility Elastic scattering No Change in Mobility E. H. Sondheimer, Adv. Physics, Metal-semiconductor contact 60 EE292L: Aneesh Nainani 30

31 Questions? 61 Physics & Chemistry 62 EE292L: Aneesh Nainani 31

32 Formation of Energy Bands (1) If atoms are close to each other, potential barrier is strong, energy bands are narrowed and spaced far apart. (Corresponds to crystals in which electrons tightly bond to ion cores, and wave functions do not overlap much with adjacent cores) (2) If atoms are far apart, potential barrier is weak, energy bands are wide and spaced close together. 63 Si bandstructure Silicon Band Structure m t m l (z) 001 (y) 010 (x)100 6 equivalent types of electrons are involved in conduction regime of nmos 2 types of holes are involved in conduction regime of pmos : heavy and light Source: F. Boeuf (ST Microelectronics) 64 EE292L: Aneesh Nainani 32

33 Strain breaks crystal symmetry Band structure without strain Band structure deformation Band Splitting Sub-band carrier redistribution - Carriers occupy valleys with lighter mass Less intervalley phonon scattering Mobility is increased Iso-energy ellipsoid m l m t m t m t < m l 65 Desired valley property Silicon 1 = 1 d 2 E m * h 2 dk 2 k =k 0 DOS α (m*) 3/2 Valley should have the desired property of - Low m transport along channel - High m width along width - High m perpendicular normal to surface 66 EE292L: Aneesh Nainani 33

34 What happens to electrons in strained Si? Unstrained Si Strained Si 2-fold perpendicular valleys <001> 4-fold in-plane valleys Lower µ n e 3D <100> <010> c 2D (001) Higher µ n In strained Si the 6 fold degenerate valleys split into 2 types of valleys. More electrons occupy the 2 fold degenerate valleys where the conductivity effective mass is lower and hence the mobility is higher 67 Effects of Strain E-k diagrams of valance band of strained Si Heavy hole band Light hole band LH HH HH LH When spacing of atoms in a crystal is altered the energy band structure changes and the shape of the E-k diagrams changes Energy levels, effective mass and density of states (DOS) change 1 = 1 d 2 E m * h 2 dk 2 k =k 0 vα(m*) -1/2 and DOS α (m*) 3/2 68 EE292L: Aneesh Nainani 34

35 Holes in Strained Si Unstrained Si Tensile strained Si 2 fold degenerate band split into light and heavy hole bands Light hole band is at lower energy and has more holes in it Reduction in conductivity mass Supression of inter-valley scattering higher µ 69 Redistribution in subbands and scattering reduction Fermi-Dirac Energy (ev) Si bulk N Unstrained Si SO HH LH >80 % in HH Energy (ev) Si/Si 0.5 Ge 0.5 E(LH-HH) Strained-Si LH < 1 % in H SO HH -0.5 [100] Γ [110] -0.3 [100] Γ [110] E In strained Si more holes occupy the band where the conductivity effective mass is lower and hence the mobility is higher Source: F. Boeuf (ST Microelectronics) 70 EE292L: Aneesh Nainani 35

36 Stress in novel transistor options? 71 MASTAR demo: will be used in PS-2 72 EE292L: Aneesh Nainani 36

37 pmos : hole bands under strain (MASTAR) 73 Strain Doodle : 74 EE292L: Aneesh Nainani 37