Emerging Interconnect Technologies for CMOS and beyond-cmos Circuits

Transcription

1 Emerging Interconnect Technologies for CMOS and beyond-cmos Circuits Sou-Chi Chang, Rouhollah M. Iraei Vachan Kumar, Ahmet Ceyhan and Azad Naeemi School of Electrical & Computer Engineering Georgia Institute of Technology

2 The Interconnect Problem Total Dynamic Power 0.13μm % Composition of Circuit Delay (NAND2 FOM short routes) Data from Intel, N. Magen et al., SLIP Workshop, Nagaraj NJ from Texas Instruments, SRC Interconnect Forum, Sept

3 RC product of a 10-Gate Pitch long Wire MOSFET Intrinsic Delay Lengths of within-core interconnects scale with technology. RC Delay (s) Various size effect parameters Bulk Cu Resistivity ε r scaling as ITRS projects R int C int ρε r L 2 WT Not constant any more!! Minimum Wire Width (nm) 3

4 Impact on Delay and Power Dissipation Worst-case capacitance c m c g c g c m W T Average capacitance c max =4c m +2c g c ave =2c m +2c g Increase in aspect ratio, substantially increases average and worst-case capacitance. Total interconnect and repeater power dissipation will increase proportionally. 4

5 Carbon Nanotubes and nanoribbons [1] [1] One dimensional Nature Strong covalent bonds Peculiar bandstructure of graphene [2] Potential candidates for switches and interconnects. [1] Images courtesy of A. Krasheninnikov, University of Helsinki [2] P. Avouris, Acc. Chem. Res., vol. 35, pp ,

6 Mobility in 2D graphene on various substrates Net mobility (cm 2 /Vs) h BN SiC SiO 2 STO HfO 2 B A 300K A (SiO 2 ) J.H. Chen et al., Nature Nano, B (h BN) C. Dean et al., Nature Nano, C (SiO 2 ) V. Dorgan et al., APL, , Electron concentration, N s (cm 2 ) C 1) Electron mobility reduces monotonically with carrier concentration. 2) Good match with experiments. 3) For h-bn, electron mobility in graphene is cm 2 /Vs for N s = cm -2. Sh. Rakheja et al. Proc. IEEE,

7 Graphene Nanoribbons 10 3 bulk = 1.2 µm Bolotin et al., 2008 air sub = 1.2 µm 1) λ eff degrades due to the presence of substrate. eff (nm) > 10x drop h BN = 300nm sub SiO 2 = 100nm sub P GNR = 0.2 E f = 0.2 ev Solid lines E f = 0.4 ev Dashed lines 2) Edge roughness degrades λ eff drastically especially for narrow ribbons. 3) λ eff ~ (75-80) nm for h- BN substrate with P GNR = 0.2 and W = 10 nm Width (nm) Must develop GNRs with perfectly smooth edges and perfectly matched dielectrics to preserve the intrinsic properties. Sh. Rakheja et al. Proc. IEEE,

8 Status Update on Key Metrics Parameters Needed Demonstrated Fermi Energy Shift (Doping) >0.2eV Edge Scattering Probability < ev in SiC Graphene 0.13 ev in exfoliated (measured) (IFC) >0.4 ev (extrapolated for sub 100nm) (IFC) 0.2 (FENA &MSD) [1] ~0 templated SiC grown GNRs [3] Contact resistance (including Quantum resistance) Mean free path in bulk material <100 Ω.µm 185±20 Ω.µm (IBM) [2] 1µm 300nm (exfoliated on h-bn) [4] >1 µm (suspended exfoliated) [5] 16 µm (templated SiC grown GNRs) [3] [1] L.Xie et.al, Journal of American Chemical Society, 2011, 133, pp [2] F. Xia et.al, Naute Nanotechnology, 2011, vol. 6, pp [3] J. Baringhaus et. al, Nature, Feb [4] C. Berger et.al, J. Phys. Chem. B 2004, 108, pp [5] K. I. Bolotin et. al, Solid State Communications 146, (2008) 8

9 Low Power Applications At low supply voltages, graphene interconnects are more attractive because of their low capacitance nm Technology Node Delay (ps) 10 3 L=10 L=50 Cu GNR Length in gate pitch (10 and 50) Energy (pj) 9

10 Novel State Variables Electron spin and magnetic moment are two of the most widely investigated new state variables to overcome power limit or bring in new functionality. All Spin Logic Device [1] Spin Torque Memory [2] Spin Wave Bus [3] Domain Wall Movement [4] [1] B. Behin-Aein et al, Nature Nanotechnology, Feb [2] A. Khitun et al, IEEE Tran. Electron Devices, vol. 54, [3] X. Wang, Seagate Technology. [4] W.S. Zhao et al, Jour. App. Phys., 109,

11 All Spin Logic _ V _ V _ V _ V _ V Communication Computation The boundary between devices and interconnects is blurring. 11

12 Drift-Diffusion Spin Devices/Interconnects -V -V Non-Local Spin torque configuration provides nonreciprocity. Channel material: Metals such as Cu, Al B. Behin-Aein, et al., Proposal for an allspin logic device with built-in memory, Nat. Nanotechnol., vol. 5, no. 4, pp , A tunnel barrier in a conventional spin torque device blocks electrons from moving back to the transmitting magnet. Channel material: Cu, Al, Si D. Datta, et al., Voltage Asymmetry of Spin-Transfer Torques, IEEE Trans. Nanotechnol., vol. 11, no. 2, pp , Mar

13 Spin Relaxation in Cu and Al Spin Relaxation Length (nm) Aluminum Copper No Size Effects 10 1 P=0.0 and R= Width (nm) L s net = κ λ d λ ph ( λ d + λ ph ) a ph λ d + a d λ ph ( ) a d a ph Size effects can lower spin diffusion length in narrow metallic wires substantially. Sh. Rakheja et al., IEEE Trans. Electron Devices, Nov

14 Spin relaxation in silicon Spin relaxation time (ns) /cm 3 Symbols: Experiment Line: Theory /cm 3 Spin relaxation time (ns) Temperature (K) Good match w/ experiments s (ns) error < 12 % 10 2 T = 300K 10 1 Symbols: experiment (Kodera, 1966) Line: theory Suzuki, App. Phys. Exp. 4, Doping (1/cm 3 ) Restrepo & Windl, 2011 Good match w/ theory IEEE Trans. Nanotechnology, Sept Temperature (K) 14

15 Spin Torque Devices and Circuits Spin Mixing Conductance Stochastic LLG for nanomagnet dynamic d m = γµ 0 m H eff dt + α m d m dt + I S, qn s V Applied V 2 FM(Co) m FM(Co) m Interconnect(Cu) Spin Mixing Conductance s t = D 2 s s µe 2 x x s Spin Drift-Diffusion in non-magnetic channel τ s 15

16 Complete Circuit Model V Applied V2 FM m FM m Interconnect(Cu) Ph. Bonhomme, et all. IEEE Trans. Electron Devices, May

17 Delay and Energy-per-bit vs. Length Typical: R =0.2 P=0 Ideal: R =0.0 P=1 Interconnect: W int =40 nm T int /W int =2.0 Magnet Size a = 80nm b = 40nm c = 3nm Delay (n Sec) Typical Cu Ideal Cu Size Effects Energy (pj) Typical Cu Ideal Cu Size Effects Interconnect Length (nm) Interconnect Length (nm) Size effects increase delay and energy in interconnects substantially. Spin interconnects can be used only for very short lengths. 17

18 Drift-Diffusion Spin Devices/Interconnects -V -V Non-Local Spin torque configuration provides nonreciprocity. Channel material: Metals such as Cu, Al B. Behin-Aein, et al., Proposal for an allspin logic device with built-in memory, Nat. Nanotechnol., vol. 5, no. 4, pp , A tunnel barrier in a conventional spin torque device blocks electrons from moving back to the transmitting magnet. Channel material: Cu, Al, Si D. Datta, et al., Voltage Asymmetry of Spin-Transfer Torques, IEEE Trans. Nanotechnol., vol. 11, no. 2, pp , Mar

19 Spin Injection to Si: Methodology The conducting electrons in F are modeled by majority and minority parabolic conduction bands. The band bending at the Si interface is obtained by solving Poisson s equation under the Thomas-Fermi approximation. S. Chang, et all. To appear in IEEE Trans. Magnetics (Si). S. Chang, et all. To appear in IEEE Trans. Electron Devices (Cu). 19

20 Comparing various Constant Delay Cu Al Silicon Conventional Spin Valve devices/interconnects are more energy efficient. Metallic channels are better for shorter lengths and Si for longer lenghts. 20

21 Conclusions Interconnects have been and will continue to be an evergrowing challenge. Major breakthroughs are needed before we can use SWNT and graphene interconnects. Carbon-based interconnects are more promising for low power applications. Post CMOS devices will benefit from Improvements in Cu-low k technology or novel materials. Conventional spin valve interconnects are more energy efficient compared to ASL interconnects. Si spin interconnects are more energy efficient for long length scales. 21