Electronics with 2D Crystals: Scaling extender, or harbinger of new functions?
|
|
- Beverly Pearson
- 5 years ago
- Views:
Transcription
1 Electronics with 2D Crystals: Scaling extender, or harbinger of new functions? 1 st Workshop on Data Abundant Systems Technology Stanford, April 2014 Debdeep Jena (djena@nd.edu) Electrical Engineering, University of Notre Dame 1
2 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 2
3 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 3
4 The Transistor: Up against fundamental limits G S D The transistor is an electronic switch: Digital Electronics It is also an amplifier: it has gain high speed: RF electronics high voltages: Power electronics 4
5 Charge-based electronics wins for digital electronics Energy (fj) SpinFET Energy vs. delay of inverters with fanout 4 with current-controlled switching, V dd =0.01 V ST: Spin-Torque Spin-wave ST transfer triad BISFET CMOS high performance Graphene pn junction All-spin logic ST Majority gate ST oscillator ST Transfer/ Domain-Wall Nanomagnet Logic Preferred Corner Heterojunction III- V Graphene nanoribbon Physics hiding under the hood Delay (ps) CMOS low power Charge- vs spin-based LOGIC (industry benchmarks)
6 Electronic switches today Conventional Silicon CMOS: The reports of my death are greatly exaggerated FETs Need breakthroughs in Bipolars Need breakthroughs in Scaling Surfaces/Interfaces Power consumption Efficiency/cost Scaling Surfaces/Interfaces Power consumption Efficiency/cost Complementary logic 22nm FinFET Neo TFETs Need breakthroughs in Other candidates Need breakthroughs in Scaling Surfaces/Interfaces Performance Complementary logic Realistic demos Scaling Surfaces/Interfaces Performance Complementary logic BisFETs, MottFETs, etc 6
7 Bandstructure of traditional semiconductors Real-space picture of Electron Orbitals sp 3 hybridization 3D semiconductors: sp 3 orbitals. Conduction by carriers near band edges. Conduction band (electrons): s-like spherical, isotropic Valence band (holes): p-like highly anisotropic 7
8 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 8
9 2D Crystals: Graphene, Semiconductors, and more Graphene, BN MoS 2, MX 2 family Graphene Family: Graphene: symmetry zero bandgap Boron Nitride: broken symmetry 5.2 ev bandgap MX 2 Family: Semiconducting Metallic, Charge-density wave Magnetic, Superconducting Common characteristics: No out-of-plane chemical bonds Thinnest materials known 9
10 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 10
11 As 3D Crystal semiconductors become small 11
12 2D Crystals offer a NEW electronic phase space 2D crystals 12
13 Scaling and electrostatics with 2D crystals 2D crystals 2D crystal semiconductors extend vertical scaling. Excellent electrostatics in 2D geometries. Double-gates natural (this is what SOI always wanted to be!). Lateral scaling: Controllable by doping/bandgaps. 13
14 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 14
15 Bonds/Interfaces/Heterostructures Chemical bonds are made of s, p, and d-orbitals. No out-of plane bonds No dangling bonds Low chance of interface traps. Interfaces are pristine, no strain as in 3D heteroepitaxial materials. Heterostructures are formed by stacking or van-der-waal epitaxy. Band-offsets are pristine and easily measured. 15
16 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 16
17 Dielectrics for 2D Crystals: HfO 2 SS ~ 74 mv/decade. On/Off~10 8. Conventional ALD seems to work, but hysteresis may be present. Nature Nano (Kis group, 2011). 17
18 TFT switches today & the case for layered materials log(id) Traditional TFT materials (amorphous Si, organics, oxides) have either Low mobilities (< 1 cm 2 /V.s) or Very high subthreshold slopes (~1 V/decade) due to defects SS off MOSFET on VDD mobility VG Layered materials offer a unique solution IEDM
19 Multilayer MoS 2 Thin-Film Transistor (TFT) SS ~ 70 mv/decade. On/Off~10 7. Robust current saturation: first time in a 2D layered crystal! Current saturation is very important in transistors for gain & fan-out Nat. Comm
20 Dielectrics for 2D Crystals: 2D crystal BN! 2D BN breakdown field ~8 MV/cm! No dangling bonds, much cleaner. 2D dielectrics for 2D crystals seems feasible. Columbia group. 20
21 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 21
22 Carrier inversion in MoS 2 : Observed Switching from n-channel to p-channel achieved with ALD dielectric. Contacts to one type of carriers inversion is slow. Very essential for complementary logic with 2D crystal semiconductors! Notre Dame. 22
23 First MoS 2 circuits First rudimentary logic circuits using MoS 2 EPFL (2012) and MIT (2012). 23
24 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 24
25 Effective masses, Mobilities In-plane effective masses are large DOS is high, mobility is low (~few 100 s cm 2 /V.s) Electron and hole effective masses are similar Guo group (Florida). 25
26 Effective masses, Mobilities of MoS 2 TMD semiconductors to date (expt) Experimental mobilities are VERY LOW! What are the fundamental limits of transport and mobility of TMD semiconductors? 26
27 Current drives in the ballistic limit: Projected pmos nmos What is lost in transport is gained back in electrostatics: high current drives in scaled limits. Guo group (Florida). 27
28 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 28
29 Mobility (cm 2 /Vs) Scattering and Mobility limits in Monolayer MoS 2 Intrinsic mobility accessible in CLEAN, SUSPENDED layers 10 4 Air/Air 1 m ~ 4200cm2 Vs N I cm -2 ( ) Currently reported electron mobilities are limited by Ionized impurity scattering BN/BN 5.1 Very low impurity densities: intrinsic/remote phonon scattering determine the highest attainable mobilities SiO 2 /Air AlN/Al 2 O 3 SiO 2 /HfO 2 ZrO 2 /HfO 2 Phonon scattering e T=300 K n s =10 13 cm -2 Charged impurity scattering High-κ gate dielectrics can increase the electron mobility only for samples infected with very high impurity densities Impurity density (cm -2 ) 29
30 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 30
31 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 31
32 Quasi-2D properties in a Wide-Bandgap 3D Crystal Ga 2 O 3 devices demonstrated in 2012/2013 There are crystals between 2D and 3D quasi-2d? A wholly unexplored arena for new high temperature & high-voltage logic devices 32
33 Quasi-2D high-voltage transistors: on-chip power conditioning Nanomembrane high-voltage transistors with Ga 2 O 3 33
34 MBE growth of extreme-bandgap oxides MBE Ga 2 O 3 Initial MBE growths of Ga 2 O 3 at Notre Dame 2e-8 5e-8 8e-8 1.1e ev 4.9 ev No growth No growth 34
35 Outline Charge-based electronics Conventional Neo 2D Crystals Electrostatics Scaling Bonds/Interfaces/Heterostructures Dielectrics Inversion Transport Effective masses, conventional transport Tunability Contacts Neo electronics possibilities enabled by 2D crystals Challenges moving forward 35
36 2D Crystal Device Roadmap We are here today 36
37 Materials challenge: TMD/layered semiconductors Molecular Beam Epitaxy of 2D Crystal Heterostructures For precise DOPING & Heterostructures (Xing, Furdyna, Jena) 37
38 2D Crystal Electronics Benchmarking 38
39 Herbert Kroemer s message 39
40 Surprises in d-orbitals: Superconductivity Case in point: Superconductivity in MoS 2 FETs: d-orbital effects show up!! 40
41 The Golden Pavilion temple in Kyoto 41
Classification of Solids
Classification of Solids Classification by conductivity, which is related to the band structure: (Filled bands are shown dark; D(E) = Density of states) Class Electron Density Density of States D(E) Examples
More informationOperating Principles of Vertical Transistors Based on Monolayer Two-Dimensional Semiconductor Heterojunctions
Operating Principles of Vertical Transistors Based on Monolayer Two-Dimensional Semiconductor Heterojunctions Kai Tak Lam, Gyungseon Seol and Jing Guo Department of Electrical and Computer Engineering,
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationSelf-study problems and questions Processing and Device Technology, FFF110/FYSD13
Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationDrift-diffusion model for single layer transition metal dichalcogenide field-effect transistors
Drift-diffusion model for single layer transition metal dichalcogenide field-effect transistors David Jiménez Departament d'enginyeria Electrònica, Escola d'enginyeria, Universitat Autònoma de Barcelona,
More informationStretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa
Stretching the Barriers An analysis of MOSFET Scaling Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa Why Small? Higher Current Lower Gate Capacitance Higher
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationOperation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS
Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2
More informationNormally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development
Center for High Performance Power Electronics Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Dr. Wu Lu (614-292-3462, lu.173@osu.edu) Dr. Siddharth Rajan
More information2D MBE Activities in Sheffield. I. Farrer, J. Heffernan Electronic and Electrical Engineering The University of Sheffield
2D MBE Activities in Sheffield I. Farrer, J. Heffernan Electronic and Electrical Engineering The University of Sheffield Outline Motivation Van der Waals crystals The Transition Metal Di-Chalcogenides
More informationSurfaces, Interfaces, and Layered Devices
Surfaces, Interfaces, and Layered Devices Building blocks for nanodevices! W. Pauli: God made solids, but surfaces were the work of Devil. Surfaces and Interfaces 1 Role of surface effects in mesoscopic
More informationSemiconductor Physics fall 2012 problems
Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each
More informationCMOS Scaling. Two motivations to scale down. Faster transistors, both digital and analog. To pack more functionality per area. Lower the cost!
Two motivations to scale down CMOS Scaling Faster transistors, both digital and analog To pack more functionality per area. Lower the cost! (which makes (some) physical sense) Scale all dimensions and
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationChapter 3 Basics Semiconductor Devices and Processing
Chapter 3 Basics Semiconductor Devices and Processing Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 Objectives Identify at least two
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More information(a) (b) Supplementary Figure 1. (a) (b) (a) Supplementary Figure 2. (a) (b) (c) (d) (e)
(a) (b) Supplementary Figure 1. (a) An AFM image of the device after the formation of the contact electrodes and the top gate dielectric Al 2 O 3. (b) A line scan performed along the white dashed line
More informationSupporting Information
Supporting Information Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits Yuanda Liu, and Kah-Wee Ang* Department of Electrical and Computer Engineering National University
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
More informationMonolayer Semiconductors
Monolayer Semiconductors Gilbert Arias California State University San Bernardino University of Washington INT REU, 2013 Advisor: Xiaodong Xu (Dated: August 24, 2013) Abstract Silicon may be unable to
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationEE410 vs. Advanced CMOS Structures
EE410 vs. Advanced CMOS Structures Prof. Krishna S Department of Electrical Engineering S 1 EE410 CMOS Structure P + poly-si N + poly-si Al/Si alloy LPCVD PSG P + P + N + N + PMOS N-substrate NMOS P-well
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects
More informationHigh Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs
High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs Prof. (Dr.) Tejas Krishnamohan Department of Electrical Engineering Stanford University, CA & Intel Corporation
More informationSurfaces, Interfaces, and Layered Devices
Surfaces, Interfaces, and Layered Devices Building blocks for nanodevices! W. Pauli: God made solids, but surfaces were the work of Devil. Surfaces and Interfaces 1 Interface between a crystal and vacuum
More informationChallenges and Opportunities. Prof. J. Raynien Kwo 年
Nanoelectronics Beyond Si: Challenges and Opportunities Prof. J. Raynien Kwo 年 立 Si CMOS Device Scaling Beyond 22 nm node High κ,, Metal gates, and High mobility channel 1947 First Transistor 1960 1960
More informationECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationThin Film Transistors (TFT)
Thin Film Transistors (TFT) a-si TFT - α-si:h (Hydrogenated amorphous Si) deposited with a PECVD system (low temp. process) replaces the single crystal Si substrate. - Inverted staggered structure with
More informationLow Frequency Noise in MoS 2 Negative Capacitance Field-effect Transistor
Low Frequency Noise in MoS Negative Capacitance Field-effect Transistor Sami Alghamdi, Mengwei Si, Lingming Yang, and Peide D. Ye* School of Electrical and Computer Engineering Purdue University West Lafayette,
More informationMSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University
MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures
More informationDigital Electronics Part II - Circuits
Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The
More informationNATO Advanced Research Workshop on Fundamental and Applied NanoElectroMagnetics (FANEM), May 25-27, 2015, Minsk, Belarus.
NATO Advanced Research Workshop on Fundamental and Applied NanoElectroMagnetics (FANEM), May 25-27, 2015, Minsk, Belarus 2D Crystals for Nanoelectronics and Beyond.. Kaustav Banerjee Department of Electrical
More informationSolid State Device Fundamentals
Solid State Device Fundamentals ENS 345 Lecture Course by Alexander M. Zaitsev alexander.zaitsev@csi.cuny.edu Tel: 718 982 2812 Office 4N101b 1 Outline - Goals of the course. What is electronic device?
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationCarbon-Based Electronics: Will there be a carbon age to follow the silicon age? Jeffrey Bokor EECS Department UC Berkeley
Carbon-Based Electronics: Will there be a carbon age to follow the silicon age? Jeffrey Bokor EECS Department UC Berkeley jbokor@eecs.berkeley.edu Solid State Seminar 9-13-13 1 Outline Review of development
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationLecture 20: Semiconductor Structures Kittel Ch 17, p , extra material in the class notes
Lecture 20: Semiconductor Structures Kittel Ch 17, p 494-503, 507-511 + extra material in the class notes MOS Structure Layer Structure metal Oxide insulator Semiconductor Semiconductor Large-gap Semiconductor
More informationSolid Surfaces, Interfaces and Thin Films
Hans Lüth Solid Surfaces, Interfaces and Thin Films Fifth Edition With 427 Figures.2e Springer Contents 1 Surface and Interface Physics: Its Definition and Importance... 1 Panel I: Ultrahigh Vacuum (UHV)
More informationIndex. buried oxide 35, 44 51, 89, 238 buried channel 56
Index A acceptor 275 accumulation layer 35, 45, 57 activation energy 157 Auger electron spectroscopy (AES) 90 anode 44, 46, 55 9, 64, 182 anode current 45, 49, 65, 77, 106, 128 anode voltage 45, 52, 65,
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 6: September 14, 2015 MOS Model You are Here: Transistor Edition! Previously: simple models (0 and 1 st order) " Comfortable
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold
More informationLong-channel MOSFET IV Corrections
Long-channel MOSFET IV orrections Three MITs of the Day The body ect and its influence on long-channel V th. Long-channel subthreshold conduction and control (subthreshold slope S) Scattering components
More informationTHE INVERTER. Inverter
THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)
More informationCHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS
98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC
More informationApplication II: The Ballistic Field-E ect Transistor
Chapter 1 Application II: The Ballistic Field-E ect Transistor 1.1 Introduction In this chapter, we apply the formalism we have developed for charge currents to understand the output characteristics of
More informationCarbon Nanotube Electronics
Carbon Nanotube Electronics Jeorg Appenzeller, Phaedon Avouris, Vincent Derycke, Stefan Heinz, Richard Martel, Marko Radosavljevic, Jerry Tersoff, Shalom Wind H.-S. Philip Wong hspwong@us.ibm.com IBM T.J.
More informationEE301 Electronics I , Fall
EE301 Electronics I 2018-2019, Fall 1. Introduction to Microelectronics (1 Week/3 Hrs.) Introduction, Historical Background, Basic Consepts 2. Rewiev of Semiconductors (1 Week/3 Hrs.) Semiconductor materials
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationCarbon based Nanoscale Electronics
Carbon based Nanoscale Electronics 09 02 200802 2008 ME class Outline driving force for the carbon nanomaterial electronic properties of fullerene exploration of electronic carbon nanotube gold rush of
More informationModelling of Diamond Devices with TCAD Tools
RADFAC Day - 26 March 2015 Modelling of Diamond Devices with TCAD Tools A. Morozzi (1,2), D. Passeri (1,2), L. Servoli (2), K. Kanxheri (2), S. Lagomarsino (3), S. Sciortino (3) (1) Engineering Department
More informationLecture 6: 2D FET Electrostatics
Lecture 6: 2D FET Electrostatics 2016-02-01 Lecture 6, High Speed Devices 2014 1 Lecture 6: III-V FET DC I - MESFETs Reading Guide: Liu: 323-337 (he mainly focuses on the single heterostructure FET) Jena:
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationGaN based transistors
GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute
More informationProspects for Ge MOSFETs
Prospects for Ge MOSFETs Sematech Workshop December 4, 2005 Dimitri A. Antoniadis Microsystems Technology Laboratories MIT Sematech Workshop 2005 1 Channel Transport - I D I D =WQ i (x 0 )v xo v xo : carrier
More informationHow a single defect can affect silicon nano-devices. Ted Thorbeck
How a single defect can affect silicon nano-devices Ted Thorbeck tedt@nist.gov The Big Idea As MOS-FETs continue to shrink, single atomic scale defects are beginning to affect device performance Gate Source
More informationLECTURE 23. MOS transistor. 1 We need a smart switch, i.e., an electronically controlled switch. Lecture Digital Circuits, Logic
LECTURE 23 Lecture 16-20 Digital Circuits, Logic 1 We need a smart switch, i.e., an electronically controlled switch 2 We need a gain element for example, to make comparators. The device of our dreams
More informationSub-Boltzmann Transistors with Piezoelectric Gate Barriers
Sub-Boltzmann Transistors with Piezoelectric Gate Barriers Raj Jana, Gregory Snider, Debdeep Jena Electrical Engineering University of Notre Dame 29 Oct, 2013 rjana1@nd.edu Raj Jana, E3S 2013, Berkeley
More informationLecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure
Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More information3C3 Analogue Circuits
Department of Electronic & Electrical Engineering Trinity College Dublin, 2014 3C3 Analogue Circuits Prof J K Vij jvij@tcd.ie Lecture 1: Introduction/ Semiconductors & Doping 1 Course Outline (subject
More informationJ. Price, 1,2 Y. Q. An, 1 M. C. Downer 1 1 The university of Texas at Austin, Department of Physics, Austin, TX
Understanding process-dependent oxygen vacancies in thin HfO 2 /SiO 2 stacked-films on Si (100) via competing electron-hole injection dynamic contributions to second harmonic generation. J. Price, 1,2
More informationSemiconductor Polymer
Semiconductor Polymer Organic Semiconductor for Flexible Electronics Introduction: An organic semiconductor is an organic compound that possesses similar properties to inorganic semiconductors with hole
More informationEnhanced Mobility CMOS
Enhanced Mobility CMOS Judy L. Hoyt I. Åberg, C. Ni Chléirigh, O. Olubuyide, J. Jung, S. Yu, E.A. Fitzgerald, and D.A. Antoniadis Microsystems Technology Laboratory MIT, Cambridge, MA 02139 Acknowledge
More informationGraphene and new 2D materials: Opportunities for High Frequencies applications
Graphene and new 2D materials: Opportunities for High Frequencies applications April 21th, 2015 H. Happy, E. Pallecchi, B. Plaçais, D. Jiménez, R. Sordan, D. Neumaier Graphene Flagship WP4 HF electronic
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V
More informationInGaAs Double-Gate Fin-Sidewall MOSFET
InGaAs Double-Gate Fin-Sidewall MOSFET Alon Vardi, Xin Zhao and Jesús del Alamo Microsystems Technology Laboratories, MIT June 25, 214 Sponsors: Sematech, Technion-MIT Fellowship, and NSF E3S Center (#939514)
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationFuture trends in radiation hard electronics
Future trends in radiation hard electronics F. Faccio CERN, Geneva, Switzerland Outline Radiation effects in CMOS technologies Deep submicron CMOS for radiation environments What is the future going to
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationExtensive reading materials on reserve, including
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today MOS MOS. Capacitor. Idea
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 9: September 26, 2011 MOS Model Today MOS Structure Basic Idea Semiconductor Physics Metals, insulators Silicon lattice
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationLecture 0: Introduction
Lecture 0: Introduction Introduction q Integrated circuits: many transistors on one chip q Very Large Scale Integration (VLSI): bucketloads! q Complementary Metal Oxide Semiconductor Fast, cheap, low power
More informationResonant photo-ionization of point defects in HfO 2 thin films observed by second-harmonic generation.
Optics of Surfaces & Interfaces - VIII September 10 th, 2009 Resonant photo-ionization of point defects in HfO 2 thin films observed by second-harmonic generation. Jimmy Price and Michael C. Downer Physics
More information6.012 Electronic Devices and Circuits
Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless
More informationNanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal
More informationGraphene and Carbon Nanotubes
Graphene and Carbon Nanotubes 1 atom thick films of graphite atomic chicken wire Novoselov et al - Science 306, 666 (004) 100μm Geim s group at Manchester Novoselov et al - Nature 438, 197 (005) Kim-Stormer
More informationIII-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis
III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis Microsystems Technology Laboratories, MIT 1 presently with Teledyne Scientific 23rd International
More informationFIELD-EFFECT TRANSISTORS
FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation
More informationB. Both A and R are correct but R is not correct explanation of A. C. A is true, R is false. D. A is false, R is true
1. Assertion (A): A demultiplexer can be used as a decode r. Reason (R): A demultiplexer can be built by using AND gates only. A. Both A and R are correct and R is correct explanation of A B. Both A and
More informationChun Yung Sung Science and Technology Strategy Department IBM T.J. Watson Research Center Yorktown, NY, USA
51. Reconfigurable Multi-Function Logic Based on Graphene P-N Junctions Sansiri Tanachutiwat, Ji Ung Lee, and Wei Wang College of Nanoscale Science and Engineering University at Albany, State University
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationan introduction to Semiconductor Devices
an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -
More informationContact Engineering of Two-Dimensional Layered Semiconductors beyond Graphene
Contact Engineering of Two-Dimensional Layered Semiconductors beyond Graphene Zhixian Zhou Department of Physics and Astronomy Wayne State University Detroit, Michigan Outline Introduction Ionic liquid
More informationPN Junction
P Junction 2017-05-04 Definition Power Electronics = semiconductor switches are used Analogue amplifier = high power loss 250 200 u x 150 100 u Udc i 50 0 0 50 100 150 200 250 300 350 400 i,u dc i,u u
More information1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00
1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.
More informationJournal of Electron Devices, Vol. 18, 2013, pp JED [ISSN: ]
DrainCurrent-Id in linearscale(a/um) Id in logscale Journal of Electron Devices, Vol. 18, 2013, pp. 1582-1586 JED [ISSN: 1682-3427 ] SUITABILITY OF HIGH-k GATE DIELECTRICS ON THE DEVICE PERFORMANCE AND
More informationVLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More information! Previously: simple models (0 and 1 st order) " Comfortable with basic functions and circuits. ! This week and next (4 lectures)
ESE370: CircuitLevel Modeling, Design, and Optimization for Digital Systems Lec 6: September 14, 2015 MOS Model You are Here: Transistor Edition! Previously: simple models (0 and 1 st order) " Comfortable
More information