Beyond Si: Opportunities and Challenges for CMOS Technology Based on High-Mobility Channel Materials T.P. Ma Yale University

Transcription

1 Beyond Si: Opportunities and Challenges for CMOS Technology Based on High-Mobility Channel Materials T.P. Ma Yale University Acknowledgments: Abigail Lubow, Xiao Sun, Shufeng Ren

2 Switching Speed of CMOS Transistor Intrinsic Speed ~ Id/Qsw I d = W/L µ C (Vg V T ) 2 = W/L µ C V 2 W: Channel Width L: Channel Length µ: Carrier Mobility Dielectric Constant C: Inversion Cap ~ /tox Vg: Gate Voltage VT: Threshold Voltage Oxide Thickness

3 Iddq (A / um / stage) Measured CMOS Inverter Speed vs Id (65 nm Node Si Technology) Intrinsic Speed ~ Id/Qsw 1E-6 Baseline PDSOI esige SOI 1E-7 1E Inverter Delay (ps)

4 Channel Length Evolution

5 The silicon transistor in manufacturing 45 nm technology 20 nm Gate Length generation

6 Gate Oxide Scaling

7 Microprocessor Speed ( )

8 90, 65, 45 nm Generation Gate Oxide

9 Tunneling current increases exponentially with decreasing oxide thickness Taur, IEEE Spectrum, July 1999

10 Source: Intel webpages

11 Chip Power Density with Scaling 1000 Exponential Rise of Power Density Nuclear reactor Rocket nozzle Sun s surface Watts/cm i386 Hot plate i486 Pentium Pentium III Pentium II Pentium Pro Pentium m 1m 0.7m 0.5m 0.35m 0.25m 0.18m 0.13m 0.1m 0.07m From New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies Fred Pollack, Intel Corp. Micro32 conference key note

12 Clock Speed (MHz) Microprocessor Clock Speed leveled off between 90 and 45nm node Cooling costs are limiting clock speeds E+04 Source: Intel E E

13 Switching Speed of MOS Transistor Speed Increases with I d = W/L µcv 2 Dielectric constant where C = /d Oxide thickness To Increase C: Decrease d Increase ( = k o ) High-k dielectrics

14 Intel News Release 1/27/2007 Intel's Transistor Technology Breakthrough Represents Biggest Change to Computer Chips In 40 Years; Intel embraces high-k gate dielectrics for 45 nm C SANTA CLARA, Calif., Jan. 27, 2007 In one of the biggest advancements in fundamental transistor design, Intel Corporation today revealed that it is using two dramatically new materials to build the insulating walls and switching gates of its 45 nanometer (nm) transistors. Hundreds of millions of these microscopic transistors or switches will be inside the next generation Intel Core 2 Duo, Intel Core 2 Quad and Xeon families of multi-core processors. The company also said it has five early-version products up and running - - the first of fifteen 45nm processor products planned from Intel.

15 Si CMOS Innovation Will Continue: up to Physical Gate length 37 nm 25 nm 18 nm 13 nm 9 nm 6 nm Ultra thin SOI High k gate dielectric Double-Gate CMOS FinFET doped channel raised source/drain Strained Si, Ge, SiGe Gate buried oxide halo depletion layer isolation Silicon Substrate buried oxide isolation Silicon Substrate Source Drain In general, growing power dissipation and increasing process variability will be addressed by introduction of new materials and device structures, and by design innovations in circuits

16 Switching Speed of CMOS Transistor Intrinsic Speed ~ Id/Qsw I d = W/L µ C (Vg V T ) 2 = W/L µ C V 2 W: Channel Width L: Channel Length µ: Carrier Mobility Dielectric Constant C: Inversion Cap ~ /tox Vg: Gate Voltage VT: Threshold Voltage Oxide Thickness

17 Beyond-Silicon CMOS: (Beyond 2020) High-Mobility Channels Carbone Nanotubes (CNTs) Graphene III-V Semiconductors

18 CNTs as High-mobility Materials 1D, quasi-ballistic transport faster small m*, high mobility (Courtesy Jia Chen) Si (p): Si (n): InSb (n): NT (p ): Mobility at RT 450 cm 2 /Vs 1,500 cm 2 /Vs 77,000 cm 2 /Vs >100,000 cm 2 /Vs! Dürkop, et al., Nano Letters (2004)

19 Ids (A) Ids(A) CNT Transistor Characteristics (Courtesy Jia Chen, IBM) -6 Before Doping Post Doping Vds (V) S=200 mv/dec Vds (V) S=85mV/dec Vgs (V) I on improved by 2 orders of magnitude Leakage completely suppressed S decreased from 200 to 85 mv/dec dopant : ( C H ) O SbCl Vgs(V) Pd SbCl 6 - Interface Dipole J. Chen, et al Appl. Phys. Lett SbCl 6 - F M > F M, favors h + injection, suppresses e - injection

20 Source Nanotube The evolution of CNT-FETs SiO 2 Drain CNT-FET logic gate Top-gated CNTFET 2004 (Courtesy Jia Chen) Self-aligned and doped CNTFET Fully-integrated CMOS circuit

21 Carbon Nanotube: W 200nm Unlikely to Succeed Si as Mainstream CMOS Channel, Due to Difficulties with Selective Growth of CNT on Si Placement of CNTs on Selected Sites Low-resistance Contacts Process Integration

22 Beyond-Silicon CMOS: (By 2020) High-Mobility Channels Carbone Nanotubes Graphene III-V Semiconductors

23 What is graphene? Single sheet of 2d carbon atoms arranged in a honeycomb lattice 2.5Å Figure from Ishigami et al. Figures from Geim et al. 0 d: Fullerenes Smalley (1985) 1 d: Nanotubes Iijima (1991) 2 d: Graphene Andre Geim (2004) 3 d: Graphite

24 Hall Mobility Measured in Top-gate Graphene MOSFET Avouris et.al., IEDM Dec. 2010

25 Back-Gate Graphene MOSFET (IBM-MIT Group) Y.Q. Wu et.al, IEDM, Dec. 2010

26 Output Characteristics of IBM Graphene MOSFET with L=70nm Vbg: 0-25V Y.Q. Wu et.al, IEDM, Dec. 2010

27 Cross-section of Front-Gate Graphene MOSFET (IBM-MIT) Y.Q. Wu et.al, IEDM, Dec. 2010

28 Transfer Characteristics of Graphene MOSFET (IBM-MIT) Y.Q. Wu et.al, IEDM, Dec. 2010

29 Graphene MOSFET (Columbia Group) Measured Modeled for R=0

30 Graphene: Unlikely to Succeed Si as Mainstream CMOS Channel, Due to Difficulties with Growth of High-quality Graphene on Si Adequate Bandgap for CMOS Logic (Too much off current) Low-resistance Contacts Process Integration Competition against III-V channels

31 Beyond-Silicon CMOS: (By 2020) High-Mobility Channels Carbone Nanotubes Graphene III-V Semiconductors

32 Properties of Si, Ge, GaAs, InGaAs, and InAs Si Ge GaAs In 0.53 Ga 0.47 As InAs E g (ev) µ n (cm 2 /v- s) 1,350 3,900 4,600 >8,000 40,000 µ p (cm 2 /v- s) 480 1, <500 m*/m o

33 Drift velocity (cm/s) Drift velocity vs. electric field theory Ge In 0.53 Ga 0.47 As InP GaAs Si theory InAs breakdown field Electric field (V/cm) (From Jerry Woodall)

34 Effect of Density of States High electron mobility in III-V semiconductor is primarily due to low effective mass Which gives rise to low density of states Which negatively impacts the drive current

35 Inversion electron concentration (#/cm 3 ) Inversion Electron Spatial Distribution EOT=2nm 2.5E+20 Si 2E+20 Ge 1.5E+20 1E+20 5E+19 GaAs InGaAs Si Nen(x) Ge Nen(x) GaAs Nen(x) InAs Nen(x) InGaAs Nen(x) 0 InAs Distance from SiO 2- semiconductor interface (nm)

36 Capacitance (F/cm2) 1nm EOT p-si, p-gaas, InGaAs, InAs Si GaAs InAs Si Tox=1nm GaAs Tox=1nm InGaAs Tox=1nm InAs Tox=1nm Id = W/LµCV Volts (V) 0

37 Capacitance (F/cm2) 0.5nm EOT p-si, p-gaas, InGaAs and InAs 6.00E E-06 Si 4.00E E E-06 GaAs Si Tox=0.5nm GaAs Tox=0.5nm InGaAs Tox=0.5nm InAs Tox=0.5nm 1.00E-06 InAs Id = W/LµCV E Volts (V)

38 N-Channel EOT=1nm m (cm /V- s) C inv m *C inv Si E E Ge E E GaAs E E InGaAs E E InAs E E EOT=0.5nm m (cm/v- s) C inv m *C inv Si E E Ge E E GaAs E E InGaAs E E InAs E E Id ~ µcinv Id ratio Id ratio

39 Id~mu*Cinv Comparison of Id in N-Channel Si, Ge, GaAs, InGaAs, and InAs N-Channel 6.00E E-02 InAs 4.00E-02 InAs InGaAs 3.00E E-02 GaAs InGaAs GaAs Ge Si 1.00E-02 Ge 0.00E+00 Si EOT (nm)

40 Peide Ye, et.al, IEDM,

41 TiN/Al 2 O 3 /GGO/In 0.53 Ga 0.47 As/InP MOSFET Raynien Kwo and Minghwei Hong, MRS Fall Meeting, Output Characteristics t TiN = 160nm, t Al2 O 3 =2nm, t GGO =5nm, W/L=10/1μm I d,max =1.05 g =2V,V d =2V g m,max =714 V d =2V, V g =0.85V V th ~0.3V, m FE =1306 cm 2 /V.s, f t ~18 GHz Sub-threshold swing~ 104 mv/dec 41

42 Performance Trend: Laterally Scalable Kwo and Hong, MRS Fall Meeting, Si NMOSFET 32nm node L g ~18nm (0.018μm) I d,sat ~1.5 ma/mm Estimated Performance for L g =0.5mm L g 20mm 10mm 8mm 4mm 2mm 1mm 0.5mm I d,sat (ma/mm) g m,max (ms/mm) June 23, DRC ~2mA/mm ~1.4mS/mm

43 InGaAs Quantum Well FET (Intel-IQE)

44 InGaAs Quantum Well FET Long Channel (Intel-IQE)

45 InGaAs Quantum Well FET Short Channel (Intel-IQE)

46 Most Promising Post-Silicon CMOS: High-Mobility III-V MOSFET s Challenges (Research Opportunities): Gate dielectrics on III-V Growth of III-V on Si P-channel drive current (hole mobility) Process integration

47 Problem with III-V PMOSFET Low Hole Mobility!! Si Ge GaAs In 0.53 Ga 0.47 As InAs E g (ev) µ n (cm 2 /v- s) 1,350 3,900 4,600 7,800 40,000 µ p (cm 2 /v- s) 480 1, <500 m*/m o CMOS requires very fat PMOSFET!!

48 Novel Solution All N-Channel CMOS Logic!! (Unipolar Logic)

49 Conventional CMOS Inverter output

50 Unipolar CMOS Inverter Based on Double-gate NMOSFETs No current path between VDD and Ground in either steady state

51 Unipolar 2-Input NOR Gate Same structure can serve as NAND, AND, OR, simply by exchanging A,B with ~A,~B; and exchanging GND with Vdd.

52 Unipolar CMOS for TFT Difficulty in realizing P-N FET pairs - ZnO, IGZO - Amorphous Si - Many organic systems Large disparity in electron/hole mobility in many TFT s

53 Example of TFT with IGZO on Polyimide N.C. Su, et al, IEEE EDL,,VOL.31, NO.7, JULY 2010

54 Transistor Characteristics of IGZO TFT N.C. Su, et al, IEEE EDL,,VOL.31, NO.7, JULY 2010

55 Dual-Rail Logic NAND Gate Based on IGZO TFT V A V DD V out TaN HfLaO V B V A VB

56 Dual-Rail Logic NAND Gate Based on Double Gate Design

57 Summary Conventional Si CMOS scaling will end III-V semiconductors are most promising One major challenge for III-V CMOS: * P-Channel (low hole mobility) Unipolar CMOS a possible solution TFT technology may also benefit from Unipolar CMOS

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