Performance Analysis of Multilayer Graphene Nano Ribbon as on chip Interconnect.

Transcription

1 Performance Analysis of Multilayer Graphene Nano Ribbon as on chip Interconnect. G.Chitra 1, P.Murugeswari 2 1 (Post Graduate Student, VLSI Design, Theni Kammavar Sangam College of Technology, Theni, India) 2 (Academic professor, Theni Kammavar Sangam College of Technology, Theni, India) ABSTRACT Equivalent single conductance model along with simple analytical formulas for calculating different circuit parameters of zigzag MLGNR has been proposed. The results obtained from proposed model are verified against Cu, SWCNT bundle, SLGNR and MLGNR in voltage mode and current mode signaling. GNR interconnect time delay at 7nm, 10nm, 14nm technology node is calculated using proposed model.extreme reduction in power dissipation has also been justified with the results. Thus it obeys Moore s law even when technology scales into tens of nanometer. Keywords Current mode signaling, Single Walled CNT (SWCNT), Graphene Nanoribbon (GNR), Single Layer GNR (SLGNR), Power Delay Product(PDP). I. INTRODUCTION Demand of better VLSI interconnects increases nowadays. Graphene Nano ribbon is playing an important role in the area of interconnection because of its outstanding properties. Graphene Nano-ribbon is a flat two dimensional sheet. Like carbon nanotube Graphene can be conducting and semi conducting [1][2]. There are two variants of Graphene sheet namely Fig.1 (a) arm-chair GNR and (b) zigzag GNR [3]. Fig.1 (a) armchair GNR In this paper the effect of equivalent circuits of MLGNR along with DIL system have been studied in terms of propagation delay using HSPICE. The multi conductor equivalent circuit [5] carries mutual inductances and mutual capacitances along with quantum resistance, quantum capacitance, electrostatic Capacitance, kinetic inductance and electrostatic inductance. For this work contact resistance of 3.2kΩ has been considered. The type of MLGNR which has been used in this work is neutral MLGNR means with no doping and with E F = 0.4eV. The inter layer distance of 0.34 nm has been considered for the MLGNR. Mean free path equal to 419 nm has been taken in this work [6]. II. INTERCONNECT MODEL GNR interconnect can be classified as SLGNR and MLGNR interconnect. Our model takes into account the effect of carrier concentration; impurity concentration; dielectric constant and temperature. Cleaner dielectric sample will result in lower impurity concentration while dirtier samples will have higher impurity concentration. Based on the above analysis, we compute equivalent RLC parameters per unit length (p.u.l.) for SC-MLGNRs with interlayer dielectric insertion. Various interconnect performance metrics such as delay, energy delay product (EDP) and bandwidth density (BWD) are computed next. We propose a new performance metric, BWD/EDP that can be used to optimize the interconnect performance. Our analysis shows that our proposed SC-MLGNRs with interlayer dielectric insertion can outperform traditional GNR, Cu and optical interconnects. Our proposed structure can be a potential candidate for local and global interconnects applications.. On the other hand, current mode signaling scheme has been relatively less explored, and, therefore more research work in this are still required. In the CMS scheme, signal swing over the interconnect is reduced by incorporating specialized low-input impedance receiver circuits [11] [14]. CMS scheme has fundamental advantage of smaller propagation delay, higher bandwidth, and higher immunity to electrostatic discharge induced damage of MOS transistors [11],[15],[16]. (b) Zigzag GNR [4]. ISSN: Page 13

2 A. ESC MODEL The shrinkage in feature size of copper interconnect limit interconnect performance and reliability in terms of delay, power and bandwidth. Fig.2 Schematic of MLGNR interconnect architecture Fig. 3(a) Multi-conductor circuit model (b) ESC model of the MLGNR interconnect [5] Fig.4 Driver-interconnect-load system used to evaluate the performance of interconnects. Equivalent circuit of a GNR interconnect is shown in the rectangle Fig. 3 Geometries of (a) single- and (b) N-Iayer GNR interconnects, together [5] ISSN: Page 14

3 III. DEVELOPMENT OF OUR PROPOSED MODEL The components of multi conductor circuit expressed by the authors in [7][8][3] have been used in this work to calculate the values for quantum capacitance, electrostatic capacitance, kinetic inductance, electrostatic Inductance and quantum resistance. (3.8) (3.7) (3.9) R Q = (h/2q 2 )/N ch N layer = 12.λ4 KΩ/ N ch N layer (3.1) C Q = N ch N layer 4q 2 /hv f = N ch N layer * 1λ3.18 af/ m (3.2) C E = ε 0 *w/d af/ m (3.3) L K = (h/4q 2 v f )/ N ch N layer = / N ch N layer nh/ m (3.4) L E = 0 *(d/w) nh/ m where, Nch =Nch,electron + Nch,hole (3.5) N ch =Σ [1 + exp((e n,electron E F )/k B T )] -1 +Σ [1 + exp((e F - E n,hole )/k B T)] -1 (3.6) N ch = number of conducting channels in one layer, N layer= number of GNR layers, h = Plank s constant =6.626*10-34 J.s, q = electronic charge =1.6*10-19 C, v f = Fermi velocity = 8* 10 5 m/s Where is distance between two adjacent layers, 0 and ε 0 are the magnetic permeability and electrostatic permittivity of free space respectively. Also the components of single conductor circuit which has been given by Cui in [10] used in this work which are given as, R ESC = 12.λ4 KΩ/ N ch N layer Where is mean free path. L = L + L ESC K E C ESC = (C Q + C) -1 A. Copper interconnect Copper based chips are semiconductor integrated circuits, usually microprocessors, which use copper for interconnections. Since copper is a better conductor than aluminium, chips using this technology can have smaller metal components, and use less energy to pass electricity through them. Together, these effects lead to higher-performance processors. Fig 6 shows equivalent circuit model of copper interconnect [5]. (1) (3.10) (2) (3) (3.11) (4) Where R-resistance,(5) ρ-resistivity, l-length of the interconnect, w-width of the interconnect, t-thickness (thickness is determined by t=ar*w), s-spacing, L- inductance, C-capacitance, ε r - relative dielectric permittivity of copper, ε 0 - dielectric permittivity, d- distance between two layers, µ -permeability. Due to the high density interconnect the pitch (spacing between interconnects) s is assumed equal to the width of the interconnect i.e. s=w. Hence the distance between layers of interconnect d is assumed equal to be twice the interconnect width. Fig 7 The 2-D structural model of copper interconnect showing its dimensions B.SLGNR interconnect SLGNR is unzipped version of SWCNT.As compared to conventional Cu interconnects, single layer GNRs exhibit smaller capacitance due to their smaller thickness. The interconnect behavior of single layer GNR has been modelled as transmission line with RLC model as explained by authors in [4]. Fig 3.9 shows interconnect structure model of SLGNR. Fig 6 Equivalent circuit model for copper interconnect. Based on the demonstrated model, interconnect resistance R, capacitance C and inductance L can be calculated for various technology nodes. Fig 8 Equivalent RLC circuit model for SLGNR. (3.12) (3.13) (3.14) ISSN: Page 15

4 Where typical value is 20 kω. is imperfect resistance and it is is quantum resistance, is kinetic inductance, is magnetic inductance, is electrostatic capacitance, is quantum Capacitance. 22nm to 14nm delay also reduces which shows that carbon Nano structures confirm the Moore's law for future technology nodes. (3.15) = Nch* ) (3.11) (3.13) (3.16) = (3.12) = (3.14) Where is number of conducting Channels, h is Planck s constant, is Fermi Velocity, is Mean free path, =450*W, is relative permittivity, q is charge density, W is width of GNR, t is the distance between surface and Conducting material, t=1*10^-6. Here,,, and are vary with respect to length [9]. Fig 3.11 distances between surface and conducting material. ) IV. PERFORMANCE ANALYSIS Equivalent circuit are implemented with RLC values given above for GNR interconnects. Simulation result has done for 22nm, 14nm, 10nm, and 7nm technology node. The performance metrics such as power, delay, power delay product have measured from simulation results for various length of the interconnect.performance comparisons have been made between copper, SWCNT, SLGNR and MLGNR interconnects. Fig 10. Delay comparison between SWCNT Bundle and MLGNR in 14nm Technology POWER DELAY PRODUCT COMPARISONS: DELAY COMPARISONS: Figure10 and 11 shows the comparison of delay in copper Interconnect, SWCNT and MLGNR in various technology nodes (14nm, 10nm and 7nm). The scale of the delay axis is taken in logarithmic measurement. At the local and intermediate level, both SWCNT and MLGNR delay performance over the Cu interconnect. Deep analysis of the results obtained in 22nm technology node, explains that, MLGNR minimal delay compared to Cu and SWCNT. Below 22nm, Cu interconnect produces a huge delay which is Unacceptable. The ballistic transport property and large mean free path make the MLGNR and SWCNT exhibit only 0.5% and 0.7% of the delay observed in copper interconnects respectively. From Plot it is revealed that when technology scales down from Table-2. Comparison of PDP ISSN: Page 16

5 REFERENCES: BANDWIDTH Bandwidth comparison of copper, SWCNT and SLGNR for 22nm and 14nm technology nodes is shown in Table II. Bandwidth is calculated by 0.35/rise time. SLGNR have wide bandwidth compare to copper and SWCNT interconnect. SLGNR is more suitable candidate for high speed operation for future interconnects technology. Table.3 Comparison of Bandwidth [1]. A. Naeemi and J. D. Meindl, Conductance modelling for grapheme nanoribbon (GNR) Interconnects, IEEE Electron Device Lett., vol. 28,no. 5, 2007, pp [2]. A. Naeemi and J. D. Meindl, Performance benchmarking for Graphene nanoribbon, carbon nanotube, and Cu interconnects, in Proc. IEEE Int. Interconnect Technol. Conf., San Francisco, CA, 2008, pp [3]. C. Xu, H, Li, and K. Banerjee, Modelling, analysis, and design of Graphene Nano-ribbon interconnects, IEEE Trans. Electron Devices, vol. 56, no. 8, pp, 2008, , [4]. T. Ragheb and Y. Massoud, On the Modelling of Resistance in Graphene Nanoribbon (GNR) for Future Interconnect Applications, in Proc. IEEE/ACM Int. Conf. on Computer- Aided Design (ICCAD 2008), 2008, pp [5]. Y. Fang, W. Zhao, X. Wang, F. Jiang, and W. Yin, Circuit modelling of multilayer Graphene nanoribbon (MLGNR) interconnect, in IEEE Conference (APEMC), 2012 Asia-Pacific Symposium, 2012, pp [6]. L. X. Benedict, V. H. Crespi, S. G. Louie, and M. L. Cohen, Static conductivity and superconductivity of carbon nanotubes Relations between tubes and sheets, Phys. Rev. B, Condens. Matter, vol. 52, no. 20, 1995, pp [7]. M. K. Majumdar, N. Reddy K., B. K. Kaushik, and S. K. Manhas, Comparison of propagation delay in single and multi -layer Graphene nanoribbon interconnects th International conference on computers and devices for communication (CODEC), 2012, pp. 1-4, [8]. V. Kumar, S. Rakheja and A. Naeemi, Modelling and optimization for multilayer Graphene nanoribbon conductors, IEEE International Technology Conference 2011 and Materials for advance metallization (IITC/MAM), 2011, pp. 1-3, [9]. D. A. Areshkin, D. Gunlycke, and C. T. White, Ballistic transport in Graphene nanostrips in the presence of disorder: importance of edge effects, Nano letters, vol. 7, no. 1, 2007, pp [10]. J.-P, Cui, W,-S. Zhao, W.-Y. Yin and 1. Hu, Signal transmission analysis of multilayer Graphene Nano-ribbon (MLGNR) interconnects, IEEE Trans. Electromagn. Compat" vol. 53, no, 4, CONCLUSION In this paper, we have compared the performance of carbon Nano structures (such as MLGNR, SWCNT Bundle and SLGNR) with Cu interconnect for on-chip interconnects applications. Carbon Nano structures have less delay and more bandwidth when compared to Cu. SLGNR and SWCNT produces only 0.5% and 0.7% of copper delay in global interconnect level. Carbon Nano structures have much higher energy efficiency approximately 1000 times better than copper due to its Ballistic transport and excellent thermal and electrical Conductivity has less power dissipation compared than Cu from this, it has been concluded that Carbon Nano structures are suitable candidate to replace copper on-chip interconnect to hold the Moore's law for future technology nodes. ISSN: Page 17