Prospects for Ge MOSFETs
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1 Prospects for Ge MOSFETs Sematech Workshop December 4, 2005 Dimitri A. Antoniadis Microsystems Technology Laboratories MIT Sematech Workshop
2 Channel Transport - I D I D =WQ i (x 0 )v xo v xo : carrier velocity at virtual source Q i (x 0 ) C ox inv [V G* -V t* (V D )] I D /W=Q i (x 0 )v xo V G* =V G -I D R s R s : Source parasitic resistance I off and subthreshold swing, S, determine V t V t* = V t0 -(V D -2R s I D )δ where δ is DIBL in V/V and V t0 =V t* (V D =0) Simple model for I D in saturation: inv ( I D / W ) = C ox ( V G V t ) v E C V S V G V D R s v xo L 0 x x o Q i (x o ) where: vxo v = and Vt = Vt 0 δv D inv [ 1+ Cox RsW (1 + 2δ ) vxo] Sematech Workshop
3 MOSFET Switch Performance Figures of Merit: Switch ideality: I on /I off Intrinsic switch speed: τ =Q G /I eff Energy/switch: Q G V Energy-Delay: Q G 2 V/I on (dynamic only) (dynamic only) Q G is the total gate charge per switch, including fringing capacitances τ is indicative of gate-limited circuit performance τ = V dd V t + ( C * f V dd [(3 δ ) / 4] V dd / C V where δ=dibl(v/v), C f * = effective gate fringing cap. ~ 0.5 ff/μm inv ox t L) L v (Based on I eff model and effective gate discharge trajectory theory by Na et al., IEDM 02) Sematech Workshop
4 MOSFET Switching Delay - historical nfet Si nfet Strained-Si pfet Si pfet Strained-Si Projected Guide: x=y Gate Length (μm) Sematech Workshop
5 Virtual source and carrier velocities in FETs 0 V V G V D Q i (x o ) Velocity at virtual source: E C v θ v xo L 0 x x o v xo =Tv θ Transmission coefficient: 1 r λ / l T = = 1 + r 2 + λ / l were r: backscattering coefficient λ: mean free path l: critical channel length v θ : unidirectional thermal velocity Sematech Workshop
6 Carrier Velocity at Virtual Source Electrons Si Electrons Strained-Si Holes Si Holes Strained-Si Projected Gate Length (μm) State-of-the-art values (2005): Electrons: T~0.6 v θ ~2.2x10 7 cm/s Holes: T~0.6 v θ ~1.4x10 7 cm/s Sematech Workshop
7 Observations The Si ballistic limit, v θ, is a moving target because the unidirectional thermal velocity depends on strain. In principle strained-si channel at the ballistic limit could meet intrinsic τ vs. L g scaling (at target I off ) to at least L g ~10 nm ( 20 nm CMOS ) However, transmission coefficient for practical FETs unlikely to increase much above ~0.7. Therefore alternative channel materials with significantly higher v θ must be sought well before L g ~10 nm. Ge and Ge/SiGe heterostructures do offer high mobility and v θ. Many challenges Sematech Workshop
8 Dielectric Interface Reduced D it still an open question: Is the ideal interface completely free of GeO x? Is this even possible? If interfacial layer is not GeON, what is the relation of interfacial layer to GeO x? Prevent GeO x, stabilize GeO x, or reduce GeO x High-k dielectric? It is necessary for scaling reasons Sematech Workshop
9 Junctions and Contacts Ge and SiGe have lower bandgap than Si, but high junction leakage observed to date is not intrinsic, rather likely due to poor passivation (surface generation) B activation and diffusion in Ge and SiGe is compatible with L g ~10 nm FET requirements P and As do not activate enough and diffuse a lot, using conventional junction formation methods. Fundamental or related to I/I? Schottky S/D very challenging. No good metal-ge workfunction choices. Need negative potential barrier. Sematech Workshop
10 Substrate/Channel Engineering The most workable substrates appear to by Si/Ge/Si/OI for pfet (HOI) and SSDOI for nfet. HOI addresses the surface passivation/dielectric interface problem and minimizes the thickness of the narrow bandgap layer, thus mitigating leakage. HOI pfet will likely meet the scaled performance requirements. SSDOI nfet will not Defect levels are probably acceptable with HOI and SSDOI materials. Sematech Workshop
11 Integration/Manufacturing Bulk-Ge wafers impractical. Ge, Si/SiGe/Ge heterostructures can all be grown epitaxially on Si. Same for GOI, and HOI. No fundamental problems here. In HOI Ge should not be allowed to diffuse to the dielectric interface. Limited thermal budget. Sematech Workshop
12 Future Directions Ge n-fet is disappointing so far. More research needed to understand fundamental limitations. Si/Ge/Si and Si/Ge/Si/OI very promising for p-fet. May have to be combined with another material if n- FET proves unworkable. GaAs is lattice-matched to Ge and may offer integration opportunity. Sematech Workshop
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