Prospects for Ge MOSFETs

Size: px
Start display at page:

Download "Prospects for Ge MOSFETs"

Transcription

1 Prospects for Ge MOSFETs Sematech Workshop December 4, 2005 Dimitri A. Antoniadis Microsystems Technology Laboratories MIT Sematech Workshop

2 Channel Transport - I D I D =WQ i (x 0 )v xo v xo : carrier velocity at virtual source Q i (x 0 ) C ox inv [V G* -V t* (V D )] I D /W=Q i (x 0 )v xo V G* =V G -I D R s R s : Source parasitic resistance I off and subthreshold swing, S, determine V t V t* = V t0 -(V D -2R s I D )δ where δ is DIBL in V/V and V t0 =V t* (V D =0) Simple model for I D in saturation: inv ( I D / W ) = C ox ( V G V t ) v E C V S V G V D R s v xo L 0 x x o Q i (x o ) where: vxo v = and Vt = Vt 0 δv D inv [ 1+ Cox RsW (1 + 2δ ) vxo] Sematech Workshop

3 MOSFET Switch Performance Figures of Merit: Switch ideality: I on /I off Intrinsic switch speed: τ =Q G /I eff Energy/switch: Q G V Energy-Delay: Q G 2 V/I on (dynamic only) (dynamic only) Q G is the total gate charge per switch, including fringing capacitances τ is indicative of gate-limited circuit performance τ = V dd V t + ( C * f V dd [(3 δ ) / 4] V dd / C V where δ=dibl(v/v), C f * = effective gate fringing cap. ~ 0.5 ff/μm inv ox t L) L v (Based on I eff model and effective gate discharge trajectory theory by Na et al., IEDM 02) Sematech Workshop

4 MOSFET Switching Delay - historical nfet Si nfet Strained-Si pfet Si pfet Strained-Si Projected Guide: x=y Gate Length (μm) Sematech Workshop

5 Virtual source and carrier velocities in FETs 0 V V G V D Q i (x o ) Velocity at virtual source: E C v θ v xo L 0 x x o v xo =Tv θ Transmission coefficient: 1 r λ / l T = = 1 + r 2 + λ / l were r: backscattering coefficient λ: mean free path l: critical channel length v θ : unidirectional thermal velocity Sematech Workshop

6 Carrier Velocity at Virtual Source Electrons Si Electrons Strained-Si Holes Si Holes Strained-Si Projected Gate Length (μm) State-of-the-art values (2005): Electrons: T~0.6 v θ ~2.2x10 7 cm/s Holes: T~0.6 v θ ~1.4x10 7 cm/s Sematech Workshop

7 Observations The Si ballistic limit, v θ, is a moving target because the unidirectional thermal velocity depends on strain. In principle strained-si channel at the ballistic limit could meet intrinsic τ vs. L g scaling (at target I off ) to at least L g ~10 nm ( 20 nm CMOS ) However, transmission coefficient for practical FETs unlikely to increase much above ~0.7. Therefore alternative channel materials with significantly higher v θ must be sought well before L g ~10 nm. Ge and Ge/SiGe heterostructures do offer high mobility and v θ. Many challenges Sematech Workshop

8 Dielectric Interface Reduced D it still an open question: Is the ideal interface completely free of GeO x? Is this even possible? If interfacial layer is not GeON, what is the relation of interfacial layer to GeO x? Prevent GeO x, stabilize GeO x, or reduce GeO x High-k dielectric? It is necessary for scaling reasons Sematech Workshop

9 Junctions and Contacts Ge and SiGe have lower bandgap than Si, but high junction leakage observed to date is not intrinsic, rather likely due to poor passivation (surface generation) B activation and diffusion in Ge and SiGe is compatible with L g ~10 nm FET requirements P and As do not activate enough and diffuse a lot, using conventional junction formation methods. Fundamental or related to I/I? Schottky S/D very challenging. No good metal-ge workfunction choices. Need negative potential barrier. Sematech Workshop

10 Substrate/Channel Engineering The most workable substrates appear to by Si/Ge/Si/OI for pfet (HOI) and SSDOI for nfet. HOI addresses the surface passivation/dielectric interface problem and minimizes the thickness of the narrow bandgap layer, thus mitigating leakage. HOI pfet will likely meet the scaled performance requirements. SSDOI nfet will not Defect levels are probably acceptable with HOI and SSDOI materials. Sematech Workshop

11 Integration/Manufacturing Bulk-Ge wafers impractical. Ge, Si/SiGe/Ge heterostructures can all be grown epitaxially on Si. Same for GOI, and HOI. No fundamental problems here. In HOI Ge should not be allowed to diffuse to the dielectric interface. Limited thermal budget. Sematech Workshop

12 Future Directions Ge n-fet is disappointing so far. More research needed to understand fundamental limitations. Si/Ge/Si and Si/Ge/Si/OI very promising for p-fet. May have to be combined with another material if n- FET proves unworkable. GaAs is lattice-matched to Ge and may offer integration opportunity. Sematech Workshop

Microsystems Technology Laboratories, MIT. Teledyne Scientific Company (TSC)

Microsystems Technology Laboratories, MIT. Teledyne Scientific Company (TSC) Extraction of Virtual-Source Injection Velocity in sub-100 nm III-V HFETs 1,2) D.-H. Kim, 1) J. A. del Alamo, 1) D. A. Antoniadis and 2) B. Brar 1) Microsystems Technology Laboratories, MIT 2) Teledyne

More information

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs Prof. (Dr.) Tejas Krishnamohan Department of Electrical Engineering Stanford University, CA & Intel Corporation

More information

Enhanced Mobility CMOS

Enhanced Mobility CMOS Enhanced Mobility CMOS Judy L. Hoyt I. Åberg, C. Ni Chléirigh, O. Olubuyide, J. Jung, S. Yu, E.A. Fitzgerald, and D.A. Antoniadis Microsystems Technology Laboratory MIT, Cambridge, MA 02139 Acknowledge

More information

Technology Development for InGaAs/InP-channel MOSFETs

Technology Development for InGaAs/InP-channel MOSFETs MRS Spring Symposium, Tutorial: Advanced CMOS Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco Technology Development for InGaAs/InP-channel MOSFETs Mark Rodwell University

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold

More information

The Prospects for III-Vs

The Prospects for III-Vs 10 nm CMOS: The Prospects for III-Vs J. A. del Alamo, Dae-Hyun Kim 1, Donghyun Jin, and Taewoo Kim Microsystems Technology Laboratories, MIT 1 Presently with Teledyne Scientific 2010 European Materials

More information

III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis

III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis Microsystems Technology Laboratories, MIT 1 presently with Teledyne Scientific 23rd International

More information

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Scaling Issues in Planar FET: Dual Gate FET and FinFETs Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Lecture #27. The Short Channel Effect (SCE)

Lecture #27. The Short Channel Effect (SCE) Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

Simple Theory of the Ballistic Nanotransistor

Simple Theory of the Ballistic Nanotransistor Simple Theory of the Ballistic Nanotransistor Mark Lundstrom Purdue University Network for Computational Nanoechnology outline I) Traditional MOS theory II) A bottom-up approach III) The ballistic nanotransistor

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).

A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room). The Final Exam will take place from 12:30PM to 3:30PM on Saturday May 12 in 60 Evans.» All of

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

EE410 vs. Advanced CMOS Structures

EE410 vs. Advanced CMOS Structures EE410 vs. Advanced CMOS Structures Prof. Krishna S Department of Electrical Engineering S 1 EE410 CMOS Structure P + poly-si N + poly-si Al/Si alloy LPCVD PSG P + P + N + N + PMOS N-substrate NMOS P-well

More information

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00 1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.

More information

GaN based transistors

GaN based transistors GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute

More information

Part 5: Quantum Effects in MOS Devices

Part 5: Quantum Effects in MOS Devices Quantum Effects Lead to Phenomena such as: Ultra Thin Oxides Observe: High Leakage Currents Through the Oxide - Tunneling Depletion in Poly-Si metal gate capacitance effect Thickness of Inversion Layer

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

MOSFET Capacitance Model

MOSFET Capacitance Model MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

More information

Carbon Nanotube Electronics

Carbon Nanotube Electronics Carbon Nanotube Electronics Jeorg Appenzeller, Phaedon Avouris, Vincent Derycke, Stefan Heinz, Richard Martel, Marko Radosavljevic, Jerry Tersoff, Shalom Wind H.-S. Philip Wong hspwong@us.ibm.com IBM T.J.

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

Chapter 5 MOSFET Theory for Submicron Technology

Chapter 5 MOSFET Theory for Submicron Technology Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are

More information

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

More information

30 nm In 0.7 Ga 0.3 As Inverted-type HEMT with Reduced Gate Leakage Current for Logic Applications

30 nm In 0.7 Ga 0.3 As Inverted-type HEMT with Reduced Gate Leakage Current for Logic Applications 30 nm In 0.7 Ga 0.3 As Inverted-type HEMT with Reduced Gate Leakage Current for Logic Applications T.-W. Kim, D.-H. Kim* and J. A. del Alamo Microsystems Technology Laboratories MIT Presently with Teledyne

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

VLSI Design and Simulation

VLSI Design and Simulation VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

Current mechanisms Exam January 27, 2012

Current mechanisms Exam January 27, 2012 Current mechanisms Exam January 27, 2012 There are four mechanisms that typically cause currents to flow: thermionic emission, diffusion, drift, and tunneling. Explain briefly which kind of current mechanisms

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Stretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa

Stretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa Stretching the Barriers An analysis of MOSFET Scaling Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa Why Small? Higher Current Lower Gate Capacitance Higher

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

Supporting information

Supporting information Supporting information Design, Modeling and Fabrication of CVD Grown MoS 2 Circuits with E-Mode FETs for Large-Area Electronics Lili Yu 1*, Dina El-Damak 1*, Ujwal Radhakrishna 1, Xi Ling 1, Ahmad Zubair

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Components Research, TMG Intel Corporation *QinetiQ. Contact:

Components Research, TMG Intel Corporation *QinetiQ. Contact: 1 High-Performance 4nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (V CC =.5V) Logic Applications M. Radosavljevic,, T. Ashley*, A. Andreev*, S.

More information

Recent Development of FinFET Technology for CMOS Logic and Memory

Recent Development of FinFET Technology for CMOS Logic and Memory Recent Development of FinFET Technology for CMOS Logic and Memory Chung-Hsun Lin EECS Department University of California at Berkeley Why FinFET Outline FinFET process Unique features of FinFET Mobility,

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

Nanoscale CMOS Design Issues

Nanoscale CMOS Design Issues Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal

More information

Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs

Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs Cheng-Ying Huang 1, Sanghoon Lee 1, Evan Wilson 3, Pengyu Long 3, Michael Povolotskyi 3, Varistha Chobpattana

More information

Appendix 1: List of symbols

Appendix 1: List of symbols Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination

More information

A Simple Semiempirical Short-Channel MOSFET Current- Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters

A Simple Semiempirical Short-Channel MOSFET Current- Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters A Simple Semiempirical Short-Channel MOSFET Current- Voltage Model Continuous Across All Regions of Operation and Employing Only Physical Parameters The MIT Faculty has made this article openly available.

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

Electronics with 2D Crystals: Scaling extender, or harbinger of new functions?

Electronics with 2D Crystals: Scaling extender, or harbinger of new functions? Electronics with 2D Crystals: Scaling extender, or harbinger of new functions? 1 st Workshop on Data Abundant Systems Technology Stanford, April 2014 Debdeep Jena (djena@nd.edu) Electrical Engineering,

More information

VLSI Design The MOS Transistor

VLSI Design The MOS Transistor VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V

More information

Surfaces, Interfaces, and Layered Devices

Surfaces, Interfaces, and Layered Devices Surfaces, Interfaces, and Layered Devices Building blocks for nanodevices! W. Pauli: God made solids, but surfaces were the work of Devil. Surfaces and Interfaces 1 Interface between a crystal and vacuum

More information

A Multi-Gate CMOS Compact Model BSIMMG

A Multi-Gate CMOS Compact Model BSIMMG A Multi-Gate CMOS Compact Model BSIMMG Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga, Ali Niknejad and Chenming Hu University of California, Berkeley

More information

Ultimately Scaled CMOS: DG FinFETs?

Ultimately Scaled CMOS: DG FinFETs? Ultimately Scaled CMOS: DG FinFETs? Jerry G. Fossum SOI Group Department of Electrical and Computer Engineering University of Florida Gainesville, FL 32611-6130 J. G. Fossum / 1 Outline Introduction -

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Decemb er 20, Final Exam

Decemb er 20, Final Exam Fall 2002 6.720J/3.43J Integrated Microelectronic Devices Prof. J. A. del Alamo Decemb er 20, 2002 - Final Exam Name: General guidelines (please read carefully b efore starting): Make sure to write your

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS 98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC

More information

Performance Enhancement of P-channel InGaAs Quantum-well FETs by Superposition of Process-induced Uniaxial Strain and Epitaxially-grown Biaxial Strain

Performance Enhancement of P-channel InGaAs Quantum-well FETs by Superposition of Process-induced Uniaxial Strain and Epitaxially-grown Biaxial Strain Performance Enhancement of P-channel InGaAs Quantum-well FETs by Superposition of Process-induced Uniaxial Strain and Epitaxially-grown Biaxial Strain Ling Xia 1, Vadim Tokranov 2, Serge R. Oktyabrsky

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since

Step 1. Finding V M. Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since Step 1. Finding V M Goal: Þnd V M = input voltage for the output = V M both transistors are saturated at V IN = V M since V DSn = V M - 0 > V M - V Tn V SDp = V DD - V M = (V DD - V M ) V Tp Equate drain

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the

More information

Errata of K Introduction to VLSI Systems: A Logic, Circuit, and System Perspective

Errata of K Introduction to VLSI Systems: A Logic, Circuit, and System Perspective Errata of K13126 Introduction to VLSI Systems: A Logic, Circuit, and System Perspective Chapter 1. Page 8, Table 1-1) The 0.35-µm process parameters are from MOSIS, both 0.25-µm and 0.18-µm process parameters

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Long-channel MOSFET IV Corrections

Long-channel MOSFET IV Corrections Long-channel MOSFET IV orrections Three MITs of the Day The body ect and its influence on long-channel V th. Long-channel subthreshold conduction and control (subthreshold slope S) Scattering components

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

CHAPTER 3. EFFECT OF STRUCTURAL AND DOPING PARAMETER VARIATIONS ON f t, NQS DELAY, INTRINSIC GAIN AND NF IN N-TYPE FINFETS

CHAPTER 3. EFFECT OF STRUCTURAL AND DOPING PARAMETER VARIATIONS ON f t, NQS DELAY, INTRINSIC GAIN AND NF IN N-TYPE FINFETS 34 CHAPTER 3 EFFECT OF STRUCTURAL AND DOPING PARAMETER VARIATIONS ON f t, NQS DELAY, INTRINSIC GAIN AND NF IN N-TYPE FINFETS In this chapter, the effect of structural and doping parameter variations on

More information

Journal of Electron Devices, Vol. 18, 2013, pp JED [ISSN: ]

Journal of Electron Devices, Vol. 18, 2013, pp JED [ISSN: ] DrainCurrent-Id in linearscale(a/um) Id in logscale Journal of Electron Devices, Vol. 18, 2013, pp. 1582-1586 JED [ISSN: 1682-3427 ] SUITABILITY OF HIGH-k GATE DIELECTRICS ON THE DEVICE PERFORMANCE AND

More information

MOSFET SCALING ECE 663

MOSFET SCALING ECE 663 MOSFET SCALING Scaling of switches Moore s Law economics Moore s Law - #DRAM Bits per chip doubles every 18 months ~5% bigger chips/wafers ~5% design improvements ~50 % Lithography ability to print smaller

More information

Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies. Philips Research, The Netherlands

Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies. Philips Research, The Netherlands Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies Hans Tuinhout, The Netherlands motivation: from deep submicron digital ULSI parametric spread

More information

Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development

Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Center for High Performance Power Electronics Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Dr. Wu Lu (614-292-3462, lu.173@osu.edu) Dr. Siddharth Rajan

More information

Towards a Scalable EKV Compact Model Including Ballistic and Quasi-Ballistic Transport

Towards a Scalable EKV Compact Model Including Ballistic and Quasi-Ballistic Transport 2011 Workshop on Compact Modeling Towards a Scalable EKV Compact Model Including Ballistic and Quasi-Ballistic Transport Christian Enz 1,2, A. Mangla 2 and J.-M. Sallese 2 1) Swiss Center for Electronics

More information

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

More information

Semiconductor Physics fall 2012 problems

Semiconductor Physics fall 2012 problems Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each

More information

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

! MOS Capacitances.  Extrinsic.  Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance

More information

Transport Enhancement Techniques for Nanoscale MOSFETs. Ali Khakifirooz

Transport Enhancement Techniques for Nanoscale MOSFETs. Ali Khakifirooz Transport Enhancement Techniques for Nanoscale MOSFETs by Ali Khakifirooz M.Sc., Electrical Engineering University of Tehran, 1999 B.Sc., Electrical Engineering University of Tehran, 1997 Submitted to

More information

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University

EE 466/586 VLSI Design. Partha Pande School of EECS Washington State University EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Lecture 2. Introduction to semiconductors Structures and characteristics in semiconductors

Lecture 2. Introduction to semiconductors Structures and characteristics in semiconductors Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation

More information

Beyond Si: Opportunities and Challenges for CMOS Technology Based on High-Mobility Channel Materials T.P. Ma Yale University

Beyond Si: Opportunities and Challenges for CMOS Technology Based on High-Mobility Channel Materials T.P. Ma Yale University Beyond Si: Opportunities and Challenges for CMOS Technology Based on High-Mobility Channel Materials T.P. Ma Yale University Acknowledgments: Abigail Lubow, Xiao Sun, Shufeng Ren Switching Speed of CMOS

More information

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 10, Number 2, 2007, 189 197 MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations S. EFTIMIE 1, ALEX. RUSU

More information

ENABLEMENT OF COMPACT MODELS FOR

ENABLEMENT OF COMPACT MODELS FOR ENABLEMENT OF COMPACT MODELS FOR ULTRA-SCALED CMOS TECHNOLOGIES D. YAKIMETS, P. SCHUDDINCK, D. JANG, M. GARCIA BARDON, N. SHARAN, B. PARVAIS*, P. RAGHAVAN, AND A. MOCUTA IMEC, KAPELDREEF 75, 3001 LEUVEN,

More information

Index. buried oxide 35, 44 51, 89, 238 buried channel 56

Index. buried oxide 35, 44 51, 89, 238 buried channel 56 Index A acceptor 275 accumulation layer 35, 45, 57 activation energy 157 Auger electron spectroscopy (AES) 90 anode 44, 46, 55 9, 64, 182 anode current 45, 49, 65, 77, 106, 128 anode voltage 45, 52, 65,

More information

Negative Bias Temperature Instability (NBTI) Physics, Materials, Process, and Circuit Issues. Dieter K. Schroder Arizona State University Tempe, AZ

Negative Bias Temperature Instability (NBTI) Physics, Materials, Process, and Circuit Issues. Dieter K. Schroder Arizona State University Tempe, AZ Negative Bias Temperature Instability (NBTI) Physics, Materials, Process, and Circuit Issues Dieter K. Schroder Arizona State University Tempe, AZ Introduction What is NBTI? Material Issues Device Issues

More information

MOSFET. Id-Vd curve. I DS Transfer curve V G. Lec. 8. Vd=1V. Saturation region. V Th

MOSFET. Id-Vd curve. I DS Transfer curve V G. Lec. 8. Vd=1V. Saturation region. V Th MOSFET Id-Vd curve Saturation region I DS Transfer curve Vd=1V V Th V G 1 0 < V GS < V T V GS > V T V Gs >V T & Small V D > 0 I DS WQ inv WC v WC i V V VDS V V G i T G n T L n I D g V D (g conductance

More information

Overview of Modeling and Simulation TCAD - FLOOPS / FLOODS

Overview of Modeling and Simulation TCAD - FLOOPS / FLOODS Overview of Modeling and Simulation TCAD - FLOOPS / FLOODS Modeling Overview Strain Effects Thermal Modeling TCAD Modeling Outline FLOOPS / FLOODS Introduction Progress on GaN Devices Prospects for Reliability

More information

Glasgow eprints Service

Glasgow eprints Service Palmer, M.J. and Braithwaite, G. and Prest, M.J. and Parker, E.H.C. and Whall, T.E. and Zhao, Y.P. and Kaya, S. and Watling, J.R. and Asenov, A. and Barker, J.R. and Waite, A.M. and Evans, A.G.R. (2001)

More information

The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices

The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices The Critical Role of Quantum Capacitance in Compact Modeling of Nano-Scaled and Nanoelectronic Devices Zhiping Yu and Jinyu Zhang Institute of Microelectronics Tsinghua University, Beijing, China yuzhip@tsinghua.edu.cn

More information

Application of High-κ Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology

Application of High-κ Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology Application of High-κ Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology Robert Chau, Justin Brask, Suman Datta, Gilbert Dewey, Mark Doczy, Brian Doyle, Jack

More information

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6

R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition. Figures for Chapter 6 R. Ludwig and G. Bogdanov RF Circuit Design: Theory and Applications 2 nd edition Figures for Chapter 6 Free electron Conduction band Hole W g W C Forbidden Band or Bandgap W V Electron energy Hole Valence

More information