Recent Development of FinFET Technology for CMOS Logic and Memory

Transcription

1 Recent Development of FinFET Technology for CMOS Logic and Memory Chung-Hsun Lin EECS Department University of California at Berkeley

2 Why FinFET Outline FinFET process Unique features of FinFET Mobility, workfunction engineering, corner r effect,, QM, volume inversion Issues Recent FinFET Develop Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high gate/high-k FinFET, Strained FinFET,, Bulk FinFET Memory DRAM, SONOS, SRAM Conclusion NTUEE Seminar 2006/04/29 Chung-Hsun Lin -2

3 MOSFET Scaling ITRS 2001 Projection 100 The first transistor 1947 Technology Scaling The Power5 microprocessor GATE LENGTH (nm) 10 LOW POWER HIGH PERFORMANCE YEAR Investment Market Growth Better Performance/Cost Same transistor design concept NTUEE Seminar 2006/04/29 Chung-Hsun Lin -3

4 Scaling : Moore s s law Technology Drivers Reduced cost / function Improved performance Greater circuit functionality Source: Intel NTUEE Seminar 2006/04/29 Chung-Hsun Lin -4

5 Bulk-Si MOSFET Scaling Issues Leakage current is the primary barrier to scaling To suppress leakage, we need to employ: Higher body doping lower carrier mobility, higher junction capacitance, increased junction leakage Thinner gate dielectric higher gate leakage Ultra-shallow S/D junctions higher Rseries G Desired characteristics: L g - High ON current (I dsat ) T ox S - Low OFF current Gate D courtesy of Prof. Kuroda Keio University Source Substrate L eff X j Drain N sub NTUEE Seminar 2006/04/29 Chung-Hsun Lin -5

6 Issues for Scaling L g to <25 nm V T variation (statistical dopant fluctuations) Leakage Incommensurate gains in I dsat with scaling limited carrier mobilities parasitic resistance NTUEE Seminar 2006/04/29 Chung-Hsun Lin -6

7 Advanced MOSFET Structures Leakage can be suppressed by using a thin body Ultra-Thin Body Double Gate Source Gate SOI SiO 2 Drain T BOX Silicon Substrate T Si Source T ox Gate 1 SOI Gate 2 V g Drain T Si NTUEE Seminar 2006/04/29 Chung-Hsun Lin -7

8 Thin-Body MOSFETs Control short-channel effects with T body No channel doping needed! Relax gate oxide (T ox ) scaling Double-Gate is even more effective Scalable to 10nm gate lengths Gate Gate Source Drain Source Drain Buried Oxide Substrate Ultra-Thin Body T body Gate Double-Gate NTUEE Seminar 2006/04/29 Chung-Hsun Lin -8

9 Electric Field Reduction Reduced vertical field in DG and UTB E eff = ηq inv ε No doping = No Q depl! + Q Si Expected to benefit: Mobility Gate Leakage depl Gate Bulk Gate Buried Oxide Substrate Thin-Body Q inv Q depl Q inv NTUEE Seminar 2006/04/29 Chung-Hsun Lin -9

10 Thin-Body MOSFETs Control short-channel effects with T body No channel doping needed! Relax gate oxide (T ox ) scaling No channel doping needed! I on Improved mobility Lower vertical electric field No impurity scattering Improved swing Better control of SCE Idrain DG Bulk Vgate C load Lower V T No depletion or junction capacitance Double-Gate is even more effective Scalable to 10nm gate lengths Potentially less V t scatter (dopant fluctuation) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -10

11 Circuit level benefits Thin body devices Good control of SCE Steep Sub-threshold swing Higher I dsat Lower Capacitance - No C junc and C depl Better CV/I delay at lower power FO4 Inverter Delay [ps] T body,utb < 5nm Bulk UTB DG T body,utb = 5nm Technology L gate [nm] Source: Leland Chang NTUEE Seminar 2006/04/29 Chung-Hsun Lin -11

12 Double-Gate MOSFETs S Gate 1 Gate 2 D Current flow Planar DG MOSFET Current flow S Gate 2 D Gate 1 Gate 2 D Gate 1 FinFET Current flow S Vertical DG MOSFET NTUEE Seminar 2006/04/29 Chung-Hsun Lin -12

13 Multi-Gate FinFET Source Gate Gate Drain Gate Gate Drain Gate Drain Gate Drain Source Gate Drain Planar DG-FET Source 90 Rotation Source FinFET Rotation allows for self-aligned gates Layout similar to standard SOI FET NTUEE Seminar 2006/04/29 Chung-Hsun Lin -13

14 FinFET Process Flow Si Fin SiO 2 Resist BOX Si 3 N 4 Spacer SOI Substrate Fin Patterning Poly Poly Gate Deposition/Litho NiSi Gate Etch Spacer Formation S/D Implant + RTA Silicidation NTUEE Seminar 2006/04/29 Chung-Hsun Lin -14

15 FinFET Device Structure Source Gate Drain All features defined by optical lithography and aggressive trimming NTUEE Seminar 2006/04/29 Chung-Hsun Lin -15

16 10nm FinFET TEM Poly-Si Si Fin NiSi 220Å SiO2 cap Lg=10nm BOX NTUEE Seminar 2006/04/29 Chung-Hsun Lin -16

17 10nm FinFET I-VI Dual N + /P + poly gates: - Need V T control Low DIBL NMOS: PMOS: 120 mv/v 71 mv/v Good SCE despite thick T ox (27Å EOT) & W fin (26nm) - Due to large S/D doping gradient & spacer thickness Drain Current [A/μm] V d =-1.2V -0.1V NMOS S=125 mv/dec PMOS S=101 mv/dec Gate Voltage [V] V d =1.2V 0.1V NTUEE Seminar 2006/04/29 Chung-Hsun Lin -17

18 Short-Channel Effects Acceptable DIBL and subthreshold slope down to below 20nm L gate Nearly ideal (60mV/dec) subthreshold slope at long L gate NMOS better than PMOS due to slower As 0 diffusion Subthreshold Slope (mv/dec) NMOS PMOS W fin =26nm Gate Length (nm) DIBL (mv/v) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -18

19 Orientation <100> Gate Source Drain (110) Surface (110) (100) <110> ~(111) (110) Rotation by 45º changes orientation from (110) to (100) Intermediate rotation similar to (111) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -19

20 How Mobility Changes Electron Mobility [cm 2 /Vs] Oxynitride (100) (111) (110) Effective Field [MV/cm] Hole Mobility [cm 2 /Vs] Oxynitride (110) (111) (100) Effective Field [MV/cm] By shifting away from (100): μ e is degraded, μ h is enhanced Can we benefit from changing the N/P ratio? NTUEE Seminar 2006/04/29 Chung-Hsun Lin -20

21 Gate Delay PMOS enhancement (20%) is larger than NMOS degradation (8%) Net delay improvement Trade off μ h and μ e NOR: PMOS stack μ h very important Most improvement NAND: NMOS stack μ h less important Least improvement % Delay Speedup vs. (100) L gate =35nm μ h, μ e NOR Inv (100) (111) (110) Orientation Fanout=4 NAND Oxynitride (100) NMOS (110) PMOS NTUEE Seminar 2006/04/29 Chung-Hsun Lin -21

22 Optimized FinFET Gate Source Drain Source Gate Source Drain (110) PMOS Drain Source (100) NMOS Drain Trade off layout area for performance NTUEE Seminar 2006/04/29 Chung-Hsun Lin -22

23 FinFET Layout Area (100) (110) (111) 45 o N / 90 o P 90 o N / 45 o P Layout Area [μm 2 ] Layout Area [μm 2 ] Inverter I dsatn,p =1.1mA I dsatn,p =110mA Non-(100) orientation saves area Higher PMOS I dsat reduces drawn W 45º orientation is less area efficient for smaller W These devices are small anyway does it matter? Use only in critical path? NTUEE Seminar 2006/04/29 Chung-Hsun Lin -23

24 Hybrid-Orientation-Technology (HOT) Super HOT: SOI version DSB: bulk version NTUEE Seminar 2006/04/29 Chung-Hsun Lin -24

25 V T : What CMOS Needs Need symmetrical V T s for proper CMOS operation Need low V T s for speed V DD Output Inverter Response V IN = V TN V IN = V DD -V TP 0 Input V DD NTUEE Seminar 2006/04/29 Chung-Hsun Lin -25

26 Gate Work Function Threshold Voltage [V] N + Poly V T =0.2V 4.52eV V Tn -V Tp V T =0.4V 4.95eV P + Poly Gate Workfunction [ev] Single gate material V Tn = -V Tp = 0.4V N + /P + Poly V Tn = -V Tp = -0.2V For low body doping, desired Φ M values are: ~ 4.5 ev for NMOS ~ 5.0 ev for PMOS Need two separate work functions for NMOS and PMOS! NTUEE Seminar 2006/04/29 Chung-Hsun Lin -26

27 Molybdenum Φ M Engineering by Ion Implantation Φ M can be lowered by N + implantation and thermal anneal ΔΦ M increases with dose energy (N segregates to SiO 2 interface & forms Mo 2 N) P. Ranade et al., IEDM 2002 Anneal time = 15m except for 900 o C (15s) T Mo = 15nm NTUEE Seminar 2006/04/29 Chung-Hsun Lin -27

28 Mo-Gated FinFETs (PMOS) Y.-K. Choi et al., IEDM 2002 Drain Current, Id [A/um] L g =80nm, T Si =10nm V ds =0.05V V t shift Mo MoN(N 2 =5x10 15 cm -2 ) Gate Voltage, V g [V] V t =0.2V for lightly doped body, and is adjustable by N + implantation Alternative technique: Full silicidication (NiSi) of n+/p+ Si gates (J. Kedzierski et al., W. Maszara et al., Z. Krivokapic et al., IEDM 2002) Potential issues include: - dopant penetration - thermal stability - stress/adhesion - gate dielectric reliability NTUEE Seminar 2006/04/29 Chung-Hsun Lin -28

29 Corner Effect in Triple or More Gates Corner Effect Different V th at corner region Significant subthreshold leakage current Strong corner radius, body doping dependence B. Doyle et al., VLSI Tech., p. 133, 2003 NTUEE Seminar 2006/04/29 Chung-Hsun Lin -29

30 Corner Effect [1] Vg=0.2 V z Vg=1 V z D y y G S 2D current density distribution 2D current density distribution DESSIS 3-D 3 D device simulator Ideal rectangular fin shape N sub =1e15cm -3 Current Density (A/cm 2 ) Position (nm) z direction y direction Current Density (A/cm 2 ) 4x10 6 3x10 6 2x10 6 1x10 6 z direction y direction Position (nm) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -30

31 Corner Effect [2] N sub =5e18cm -3 corner z y Current Density (A/cm 2 ) 2.0x x10 7 flat Vg=0.2 V 1.0x x10 6 2D current density distribution X Axis Y Axis z 4x10 20 y Vg=1 V Electron Density (cm -3 ) 3x x x D current density distribution NTUEE Seminar 2006/04/29 Chung-Hsun Lin X Axis Y Axis

32 3D Simulation w/ Various Shape of Corner Lg=1μm, Wsi=30nm, Hsi=30nm, Tox=1nm R=0, 5, 10, 15m Normalized Drain Current (A/μm) 1E-5 1E-7 1E-9 1E-11 R=15nm R=10nm R=5nm R=0nm 1E Gate Voltage (V) Normalized Drain Current (A/μm) 8.0x x x x10-5 R=15nm R=10nm R=5nm R=0nm Gate Voltage (V) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -32

33 Short Channel Behavior MG device with sharp corner shows better short channel behavior than the rounded corner R=0nm R=15nm DIBL (mv/v) Gate Length (nm) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -33

34 Double-humps induced by cap transistor 30x30nm structure, T ox =3nm, L g =1mm, N sub =5e18cm -3 Cap transistor induced lower V t is very significant. It may attribute to thicker T ox, and more partial depleted. dgm/dvg 4.0x x x x x30nm L g =1μm, T ox =3nm N sub =5e18cm -3 Drain Current (A) 1E-5 1E-7 1E-9 1E-11 1E-13 1E Gate Voltage (V) 1E Gate Voltage (V) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -34

35 Volume Inversion [1] Gate Gate Gate Gate edensity edensity 6.1E E E E+13 T si 4.5E+13 T si 4.5E E E E E E+13 N sub =10 15 cm -3 N sub =10 18 cm E+13 Oxide Oxide The electron density distribution from the 3-D ISE device simulator. Volume inversion is significant in intrinsic channel SDG (left). NTUEE Seminar 2006/04/29 Chung-Hsun Lin -35

36 Electric Potential (V) 0.6 N sub = cm Volume Inversion [2] ϕ s0, 10nm ϕ s, 10nm ϕ s0, 20nm ϕ s, 20nm Gate Voltage (V) Inversion charge sheet density (C/cm 2 ) 1E For intrinsic channel doping, volume inversion is valid and the potential through the Si film is flat in the subthreshold region. The inversion charge (current) in the subthreshold region is proportional to T si. NTUEE Seminar 2006/04/29 Chung-Hsun Lin -36 1E-5 1E-7 1E-9 1E-11 1E-13 N sub = cm -3 T si Tsi = 10 nm Tsi = 20 nm Gate Voltage (V)

37 QM Surface Potential Correction Undoped case NTUEE Seminar 2006/04/29 Chung-Hsun Lin -37

38 I-V V Verification Model can predict both subthreshold and strong inversion region well. 1E-4 6.0x10-5 Drain Current (A/μm) 1E-6 1E-8 1E-10 1E-12 Symbols: 2D simulation Lines: Model Classic QM Drain Current (A/μm) 5.0x x x x x10-5 Symbols: 2D simulation Lines: Model Classic QM 1E Gate Voltage (V) Gate Voltage (V) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -38

39 S/D Series Resistance Issue J. Kedzierski et al., IEDM 2001 S/D series resistance will degrade the performance of thin body device Can be improved by the selective Si epitaxy raised S/D NTUEE Seminar 2006/04/29 Chung-Hsun Lin -39

40 Why FinFET Outline FinFET process Unique features of FinFET Mobility, workfunction engineering, corner r effect,, QM, volume inversion Issues Recent FinFET Develop Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high gate/high-k FinFET, Strained FinFET,, Bulk FinFET Memory DRAM, SONOS, SRAM Conclusion NTUEE Seminar 2006/04/29 Chung-Hsun Lin -40

41 Triple-Gate Transistor B. Doyle et al., VLSI Tech NTUEE Seminar 2006/04/29 Chung-Hsun Lin -41

42 Omega-Gate Transistor NTUEE Seminar 2006/04/29 Chung-Hsun Lin -42

43 5nm Nanowire FinFET NTUEE Seminar 2006/04/29 Chung-Hsun Lin -43

44 Independent Gate FinFET Control the threshold voltage Ideal rectangular shape of Si fin NTUEE Seminar 2006/04/29 Chung-Hsun Lin -44

45 Independent Gate FinFET NTUEE Seminar 2006/04/29 Chung-Hsun Lin -45

46 Multi-Channel FinFET NTUEE Seminar 2006/04/29 Chung-Hsun Lin -46

47 Metal Gate FinFET NTUEE Seminar 2006/04/29 Chung-Hsun Lin -47

48 Metal-Gate FinFET K.G. Anil et al., VLSI Tech Vth adjustment Improvement of Ion NTUEE Seminar 2006/04/29 Chung-Hsun Lin -48

49 TiN/HfO2 FinFET Vth adjustment Reduce Gate leakage N. Collaert et al., VLSI Tech NTUEE Seminar 2006/04/29 Chung-Hsun Lin -49

50 Inverted T Channel (ITFET) UTB + FinFET Continuous effective width L. Mathew et al., IEDM 2005 NTUEE Seminar 2006/04/29 Chung-Hsun Lin -50

51 Strained FinFET 25% drain current enhancement of PFET by introducing recessed Si 0.8 Ge 0.2 S/D Compressive stress and raised S/D P. Verheyen et al., VLSI 2005 NTUEE Seminar 2006/04/29 Chung-Hsun Lin -51

52 Impact of Gate-Induced Strain MuGFETs with TiSiN gate (+3GPa stress as deposited) % (100) metal (110) metal (100) poly ref (110) poly ref % (100) metal (110) metal (100) poly ref (110) poly ref % NMOS % PMOS z E eff =0.4MV/cm Experiment σ xx Stress [MPa] σ yy σ zz (100) NMOS 4 Mobility Enhancement [%] (110) NMOS 59 (100) PMOS 8 (110) PMOS 10 x y Inverse PR Model NTUEE Seminar 2006/04/29 Chung-Hsun Lin -52

53 Issue of Fin Formation K. Endo et al., IEDM 2005 Neutral beam etching can accomplish damage (defect) free fabrication of high aspect ratio fin. Higher mobility is obtained in NB device due to atomically-flat surface NTUEE Seminar 2006/04/29 Chung-Hsun Lin -53

54 Sidewall Spacer Transfer (SWT) Process A. Kaneko et al., IEDM 2005 Both gate and fin are formed by SWT SiN is selected as hard mask material for Si RIE on top of fin Can be used as the CMP stopper during poly gate planarization (important for gate SWT) Suppress the agglomeration of Si fin during selective Si epi Prevent the leakage of the top corner Used as RIE stopper in the gate RIE process NTUEE Seminar 2006/04/29 Chung-Hsun Lin -54

55 SWT Process The threshold voltage uniformities for SWT FinFETs of 15nm fin and 15nm gate length over the wafer is better than ArF and EB lithography NTUEE Seminar 2006/04/29 Chung-Hsun Lin -55

56 Selective Gate Sidewall Spacer Formation NTUEE Seminar 2006/04/29 Chung-Hsun Lin -56

57 FinFET on Bulk Si Substrate Bulk FinFET has the advantages of cheaper wafer cost, ease of combination with conventional bulk CMOS. K. Okano et al., IEDM 2005 NTUEE Seminar 2006/04/29 Chung-Hsun Lin -57

58 Characteristics of Bulk FinFET Better subthreshold swing Better short channel control Negligible body effect T. Park et al., VLSI 2003 NTUEE Seminar 2006/04/29 Chung-Hsun Lin -58

59 Why FinFET Outline FinFET process Unique features of FinFET Mobility, workfunction engineering, corner r effect,, QM, volume inversion Issues Recent FinFET Develop Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal-gate/high gate/high-k FinFET, Strained FinFET,, Bulk FinFET Memory DRAM, SONOS, SRAM Conclusion NTUEE Seminar 2006/04/29 Chung-Hsun Lin -59

60 DRAM application of Bulk FinFET NTUEE Seminar 2006/04/29 Chung-Hsun Lin -60

61 DRAM application of Bulk FinFET Negative word line bias is introduced due to lower VT NTUEE Seminar 2006/04/29 Chung-Hsun Lin -61

62 NWL Scheme Lower V T (doping concentration) FinFET combined with NWL scheme can provide lower leakage and higher performance NWL bias is critical to refresh fail bit NTUEE Seminar 2006/04/29 Chung-Hsun Lin -62

63 SONOS Application of FinFET J. Hwang et al., TSMC 2005 High Performance FinFET SONOS flash cells with gate length of 20nm is demonstrated. Program/erase window of 2V with high P/E speed (Tp=10ms, TE=1ms) NTUEE Seminar 2006/04/29 Chung-Hsun Lin -63

64 SONOS Application of FinFET Excellent endurance: up to 10K P/E cycles Good retention: 1.5V after 10years retention time J. Hwang et al., TSMC 2005 NTUEE Seminar 2006/04/29 Chung-Hsun Lin -64

65 FinFETs based 6-T 6 T SRAMs BL load WL V DD M 2 M 4 VR M M 5 VL 6 access M 1 M 3 pulldown BL Large fraction of the total chip area will be memory 1 Leakage problem Limited by impact of variations FinFETs offer good control of short channel effects 1 Source : Ranganathan, 2000 NTUEE Seminar 2006/04/29 Chung-Hsun Lin -65

66 Static Noise Margin The minimum noise voltage at the storage node needed to flip the state Large SNM is desirable Make pulldown device stronger relative to access transistor Source: Bhavnagarwala, 2001 NTUEE Seminar 2006/04/29 Chung-Hsun Lin -66

67 SNM spread with variations Probability Tsi = 11nm Tsi = 15nm Thicker Si body better Higher performance due to Rs limitations Greater noise immunity (SNM) Lesser spread in SNM SNM (V) Taurus Device Simulation NTUEE Seminar 2006/04/29 Chung-Hsun Lin -67

68 SNM spread with variations Probability T Si = 15nm (100)/ 1fin (110) / 1fin (100 )/ 2 fins To improve SNM a) W pulldown - 2 fins b) L access c) μ eff, pulldown >μ eff, access (100)pulldown device (110) access device SNM (V) Taurus Device Simulation NTUEE Seminar 2006/04/29 Chung-Hsun Lin -68

69 FinFET Circuit design tradeoffs Advantages Excellent SCE control Scalability Double-gates are self-aligned Insensitivity to channel doping Limitations Gate material Contact/Series resistance Area efficiency (fin pitch) Back gate routing NTUEE Seminar 2006/04/29 Chung-Hsun Lin -69

70 Conclusion Unique FinFET physics are introduced. Recent developing effort on FinFET technology are discussed Triple-gate FinFET, Omega FET, Nanowire FinFET, Independent gate, Multi-channel FinFET, Metal- gate/high-k FinFET, Strained FinFET,, Bulk FinFET FinFET based CMOS and memory cells are very promising for sub-32 technology node. NTUEE Seminar 2006/04/29 Chung-Hsun Lin -70

71 Thank you very much for your attention NTUEE Seminar 2006/04/29 Chung-Hsun Lin -71