A 20 nm gate-length ultra-thin body p-mosfet with silicide source/drain

Transcription

1 Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 doi: /spmi Available online at on A 20 nm gate-length ultra-thin body p-mosfet with silicide source/drain JAKUB KEDZIERSKI, PEIQI XUAN, VIVEK SUBRAMANIAN, JEFFREY BOKOR, TSU-JAE KING, CHENMING HU Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720, U.S.A. ERIK ANDERSON Lawrence Berkeley National Laboratory, Berkeley, CA, U.S.A. (Received 9 August 2000) As the scaling of CMOS transistors extends to the sub-20 nm regime, the most challenging aspect of device design is the control of the off-state current. The traditional methods for controlling leakage current via the substrate doping profile will be difficult to implement at these dimensions. A promising method for controlling leakage in sub-20 nm transistors is the reduction in source-to-drain leakage paths through the use of a body region which is significantly thinner then the gate length, with either a single or a double gate. In this paper we present ultra-thin body PMOS transistors with gate lengths down to 20 nm fabricated using a low-barrier silicide as the source and drain. Calixarene-based electron-beam lithography was used to define critical device dimensions. These transistors show 260 µa µm 1 on-current and on/off current ratios of 10 6, for a conservative oxide thickness of 40 Å and V g V t = 1.2 V. Excellent short-channel effect, with only 0.2 V reduction in V t is obtained in devices with gate lengths ranging from 100 to 20 nm. c 2000 Academic Press Key words: ultra-thin body, thin-body, silicide source/drain, Schottky source/drain, nanotransistor, fully depleted SOI, SOI MOSFET, scaled CMOS, MOS devices. 1. Introduction An effective method for controlling leakage current in sub-50 nm gate-length MOSFETs is the use of an ultra-thin body [1]. In ultra-thin body (UTB) transistors, the potential barrier for any path between the source and drain is more strongly coupled to the gate than the drain. This is accomplished by making the body from a thin silicon film with a thickness that is approximately one-half of the source-to-drain spacing. When a transistor is made with such a thin body, the gate potential controls all source-to-drain current paths even ones furthest away from the gate. As the gate modulates the potential of the channel region, it also modulates the potential of all the other sub-surface leakage paths, thus the UTB transistor does not rely on body doping to provide a potential barrier between the source and drain. jakub@eecs.berkeley.edu /00/ $35.00/0 c 2000 Academic Press

2 446 Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 Spacer Poly gate Silicide 100 Å BOX Silicon UTB Fig. 1. Schottky source/drain UTB MOSFET structure. A major problem for many UTB transistor designs is the series resistance caused by the thin silicon film, which is less than 10 nm thick for gate lengths of 20 nm. The traditional method of improving series resistance by siliciding the source and drain with a mid-gap silicide such as TiSi 2 or CoSi 2 is difficult because even a thin silicide would consume the entire source/drain areas, reducing the contact area and thus increasing the contact resistance. The raised source/drain (RSD) [2] design addresses the resistance problem by increasing the thickness of the source/drain regions after spacer formation; however this approach increases gate source capacitance and is technologically complicated. A lowered source/drain (LSD) [3] also has been proposed for increasing the source/drain thickness by extending the source/drain regions into the buried oxide. However, this method relies on solid phase epitaxy, a process that is difficult to control with present-day techniques. Double-gate devices such as the FinFET [4, 5] are also limited by the resistance of the thin-body, source/drain extensions. Thickening the body in the source/drain contact regions presents similar technological challenges and increased Miller capacitance. Other device designs not based on the UTB concept have been proposed to overcome the challenges associated with fabricating high-performance 20 nm gate-length transistors. One novel device design uses a low-barrier silicide as the source/drain of a traditional bulk MOSFET [6]. So far, PMOS devices with a 0.25 V barrier have been made with PtSi, and a complementary NMOS technology using ErSi 2 has been proposed [7]. The advantage of this design is that the difficulties associated with controlling source/drain doping for short gate length transistors are avoided. However, the bulk silicide source/drain (SSD) devices with no body doping have on/off current ratios of only 10 2 at room temperature. Traditional leakage control methods such as halo and body doping can decrease the leakage, but they will also increase the threshold voltage and thus decrease drive current. Simulations of bulk SSD devices show that with currently available silicides it is impossible to control the leakage current by using a uniform body doping, without degrading the device behavior [8]. Nonuniform doping schemes have been proposed to work around this limitation [9], however they would require abrupt doping profiles that are difficult to achieve. In this paper, a new transistor design, which combines the best components of the UTB and SSD concepts, is proposed. The UTBSSD device, shown in Fig. 1, consists of an ultra-thin body transistor that has been silicided in the source/drain regions with a low-barrier silicide, in the case of PMOS: PtSi. The combination of the UTB and SSD components is uniquely symbiotic: the main problem in the SSD device, leakage current, is controlled without the use of doping by the UTB, and the main problem in the UTB device, series resistance, is overcome by using a SSD that is an order of magnitude less resistive than degenerately doped silicon. The UTBSSD device also has low parasitic capacitances, both to the gate and to the substrate. In addition, since the source and drain are defined by the silicide/body boundary, the source and drain junctions are atomically sharp, and can be scaled without considerations of doping abruptness.

3 Superlattices and Microstructures, Vol. 28, No. 5/6, Gate, L =20nm Source/Drain, W =15nm Fig. 2. SEM micrograph of a 20 nm gate-length MOSFET, after gate etch. 2. Device fabrication The fabrication process of the PMOS UTBSSD devices started with SOITEC [10] silicon on insulator (SOI) wafers, thinned down to a silicon thickness of 140 Å using dry oxidation. The silicon film thickness uniformity was measured by ellipsometry and TEM analysis and varied less than 20 Å in the 2 diameter circle at the center of the wafer, where all devices were fabricated. Mesa definition was done with a double resist process that used calixarene-based electron-beam lithography [11] to define fine features and optical g-line lithography to define coarse features. Due to the low sensitivity of calixarene, the use of a single electron-beam exposure to define the entire level would have required a prohibitively long write time. The double resist process started with a standard g-line exposure completed through development, using a resist thickness of 1000 Å. Following development, 400 Å of calixarene resist was spun on to the wafer and exposed with a 100 kev electron beam [12] to a dose of 20 mc cm 2. The calixarene was then developed in xylene and rinsed in water. The combination of the two resists served as a mask for the dry etch used to define the silicon mesa. After the mesa etch, and resist strip in oxygen plasma, a dry oxidation was used to remove 20 Å of silicon and clean up the mesa surface. The gate stack consisted of a 40 Å thermally grown gate oxide, a 550 Å thick n-type polysilicon gate, and a 150 Å SiO 2 hard mask deposited by LPCVD. Gate definition was also accomplished with two exposures. First the oxide hard mask was patterned with calixarene-based electron-beam lithography followed by a dry oxide etch. The calixarene was then stripped and coarse gatelevel features were defined with g-line optical lithography. Both the oxide hard mask and the optical resist were used as a mask in the HBr-based dry gate etch. Figure 2 shows the top-down SEM micrograph of a 20 nm gate-length, 15 nm width device after the gate etch. Following gate patterning, a 200 Å oxide layer was deposited by LPCVD and etched with a dry oxide etch to form the spacers. Wafers were cleaned in an oxygen plasma and given an HF last rinse in 25 : 1 HF, prior to metal evaporation. This clean etched the spacers down to a final thickness of 100 Å. A 75 Å platinum layer was then deposited using an e-beam evaporation system with a base pressure of Torr. PtSi was formed with a three-step anneal at 250, 325, and 400 C for 1 h each, in a nitrogen-purged oven. The Pt reacted with the entire 100 Å of silicon to form a PtSi film with a resistivity of 150 /square. Unreacted Pt was removed in 4 : 3 : 1 H 2 O : HCl : HNO 3 at 80 C for 30 s. Some devices were processed with TiSi 2 instead of PtSi for comparison. For those devices,

4 448 Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 I d (A) E E E E E E E E E E E-06 (V) V g =-0.5 V g =-0.7 V g =-0.9 V g =-1.1 V g =-1.3 V g =-1.5 V g =-1.7 V g =-1.9 Fig. 3. I d behavior of a 20 nm gate-length, 15 nm wide, SSD MOSFET, with an n + polygate. V t = 0.7 V. 100 Å of Ti was deposited by sputtering and was reacted with the Si in a rapid thermal anneal system at 350 and 400 C for 30 s each. Unreacted Ti was then removed with a sulfuric acid etch. 3. Device modeling The presence of the metal semiconductor junction at the source/body boundary adds a device element that is not present in a conventional CMOS device. To better understand the benefits and drawbacks of the SSD design and how the Schottky barrier affects device performance, it is instructive to develop an intuitive model that incorporates the effect of the barrier on transistor behavior. As a first step towards this goal, the dependence of the barrier height, φ b, as a function of electric field can be estimated. The simplest approximation of the barrier height between a semiconductor and metal is a constant that is related to the difference between the work function of the two materials. The Fermi level for most metals falls somewhere in the silicon bandgap, so that there is a positive potential barrier to the flow of both electrons and holes. The effective Schottky barrier height is lowered by two important mechanisms: image charge and tunneling; both of these are only dependent on the electric field perpendicular to the interface, E y. In the SSD structure, E y depends on the oxide field, E x, between the gate and the source, through some geometric factor, G, defined such that E y = G E x. To lower the barrier, either E x or G should be increased. The straightforward way to increase E x is to make the gate oxide as thin as possible. Increasing G involves changing the device geometry. According to our simulations G 0.2 for long-width devices in the subthreshold regime, and drops to 0.1 in strong inversion due to screening. G should be significantly larger for structures such as the wire transistor shown in Fig. 2, where the gate is present on three sides of the barrier and not just on the top, and double-gate structures such as the FinFET. The silicon body can be made sufficiently thin so that the source-to-body potential barrier is primarily determined by the gate and not strongly influenced by the drain. Assuming this is the case, there are two distinct bias regimes. One occurs when the transistor is off and the source-to-body potential is larger than the Schottky barrier height. In this regime, the subthreshold swing of the transistor is 60 mec 1, provided that the minority-carrier current is negligible. As the gate lowers the potential of the body and the device turns on, a flat-band voltage will be reached when the body to source potential is equal to the Schottky-barrier height. As the body potential is lowered past this point, the Schottky barrier becomes significant, and the transistor enters the second bias regime. The subthreshold swing in this regime is mec 1, depending on the efficiency of the gate-induced barrier lowering, which is governed by the oxide thickness

5 Superlattices and Microstructures, Vol. 28, No. 5/6, Log(-I d ) (A) =-0.2 =-0.4 =-0.6 =-0.8 =-1 =-1.2 = V g (V) Fig. 4. I d V g behavior of a 20 nm gate-length, 15 nm wide, SSD MOSFET, with a 100 Å body. S = 105 mec 1. and device geometry. If the Schottky barrier is lowered sufficiently, the transistor will be limited by ballistic carrier transport through the channel. It is instructive to consider the value of the Schottky barrier for which carriers are injected into the channel as readily as for a p n junction. Since the density of available carriers in the metal silicide is about one to two orders of magnitude higher than in doped silicon, lowering the barrier to V might be sufficient to render it equivalent to a silicon junction at room temperature. 4. Results and discussion The I d characteristics of a 20 nm gate-length PtSi UTB p-mosfet are shown in Fig. 3. A 260 µa µm 1 I d is observed at = 1.5 V, V g V t = 1.2 V. The gate-length measurement was made before spacer formation; the actual metallurgical channel length is still smaller. The on-current value is comparable to that of a conventional p-mosfet with the same oxide thickness and bias conditions. In our experiment, there was no metallization past the silicide layer, therefore the series resistance of the devices was large. This is one of the reasons why devices wider than 20 nm showed less on-current per micron then the 15 nm wide device presented here. The other more fundamental reason for this discrepancy is the fact that for wider devices the geometric factor, G, is expected to drop. Therefore, it might be necessary to form wider devices out of several minimum-width devices connected in parallel for optimum performance. The subthreshold characteristics plotted in Fig. 4 show that the device has a V t of 0.7 V and a subthreshold swing of 105 mec 1. This is larger than the ideal swing of 60 mec 1, indicating that for devices of this gate length, the drain has a significant influence on the source barrier. Figures 5 and 6 show the threshold voltage and subthreshold swing for devices of different gate lengths. The V t roll-off is small even down to 20 nm gate lengths, demonstrating that a 100 Å UTB is sufficient to suppress short-channel effects. The long channel V t has the expected value of E g + φ b = 0.85 V (assuming φ b = 0.25), with some variation due to processing. This is the value at which the flat-band condition occurs between the source and body, given the fact that the gate is N-type silicon and the device is PMOS. The difficulty in controlling the threshold voltage is a general problem with UTB devices. Normally, gate work-function engineering is used to adjust V t. With SSD devices, an interesting possibility exists for controlling the V t by varying the source-to-body barrier height. Unfortunately, if the barrier height is increased to change the V t, the on-current is drastically reduced, so gate-material engineering is still the best way to adjust the threshold voltage of the UTBSSD transistor. The threshold voltage of our devices would have

6 450 Superlattices and Microstructures, Vol. 28, No. 5/6, Threshold voltage (V) Drawn gate length (µm) Fig. 5. Threshold voltage as a function of drawn gate length. Physical gate length is 5 nm larger than drawn Swing (ec -1 ) Drawn gate length (µm) Fig. 6. Subthreshold swing as a function of drawn gate length. Physical gate length is 5 nm larger than drawn. shifted to 0.3 V with the use of a mid-gap gate material such as TiN. The swing for long-channel devices is 75 mec 1, a little worse than the ideal 60 mec 1 value. As a verification of the theory presented in this work, devices with TiSi 2 source/drain were also fabricated. Figure 7 shows the behavior of a single 100 nm TiSi 2 SSD device. This device can be biased in either PMOS mode or NMOS mode, since TiSi 2 has a similar Schottky barrier for both electrons and holes. The behavior in both modes is poor, since the barrier height is high. The on-current shows exponential dependence on and V g, and the swing is approximately 300 mec 1. The TiSi 2 device normally operates in the Schottky-barrier limited regime below the flat-band condition for the majority carrier, and as expected the barrier lowering by the gate is significantly worse than the 60 mec 1 seen in the PtSi devices where the subthreshold barrier is formed by the body. A parasitic effect exists for SSD devices that is especially evident when the silicide is mid-gap. When the NMOS device is turned off, the parasitic PMOS device turns on. This is clearly evident in Fig. 7C where the current starts to increase for low gate voltages. Having asymmetrical Schottky barriers decreases the magnitude of this effect, and so it is not visible for the PtSi devices where φ bn = 0.85 V and φ bp = 0.25 V.

7 Superlattices and Microstructures, Vol. 28, No. 5/6, A TiSi 2 SD, W = 100 nm, L = 100 nm, N-mode on-current plot I d 6.00E E E E E-07 V g =0.0 V g =0.2 V g =0.4 V g =0.6 V g =0.8 V g =1.0 V g =1.2 V g = E E B 0.00E+00 TiSi 2 SD, W = 100 nm, L = 100 nm, P-mode on-current plot I d -2.00E E E E-07 V g =-1.6 V g =-1.8 V g =-2.0 V g =-2.2 V g =-2.4 V =-2.6 g V g =-2.8 V g = E C I d TiSi 2 SD, W = 100 nm, L = 100 nm, N-mode subthreshold plot 1.00E-06 V sd =0.2 V sd = E-07 V sd =0.6 V sd = E-08 V sd =1.0 V sd =1.2 V sd = E E E V g Fig. 7. Characteristics of a single TiSi 2 device, W = L = 100 nm, device can be biased in N-mode (A), p-mode (B). The subthreshold behavior of the N-mode is plotted in (C).

8 452 Superlattices and Microstructures, Vol. 28, No. 5/6, Conclusion An UTBSSD p-mosfet is demonstrated to have low leakage current down to 20 nm gate lengths. I on is 260 µa µm 1 for V g V t = 1.2 V. Devices show a swing of mec 1, an on/off current ratio of 10 6, and have the expected threshold voltage of 0.85 V. To improve device behavior, the oxide thickness can be scaled down from 40 to 20 Å. The desired threshold voltage of 0.3 V can be achieved with the use of a gate material that has a work function corresponding to the middle of the bandgap of silicon. Acknowledgement This work is supported by the DARPA AME Program, contract number N References [1] B. Yu, Y. -J. Tung, S. Tang, E. Hui, T. -J. King, and C. Hu, Proceedings of ISDRS 97 (1997) pp [2] Y. K. Choi, K. Asano, N. Lindert, V. Subramanian, T. -J. King, J. Bokor, and C. Hu, Proceedings of IEDM 99 (1999) pp [3] V. Subramanian, J. Kedzierski, N. Lindert, Y. Su, J. McHale, K. Cao, T. -J. King, J. Bokor, and C. Hu, DRC (1999) pp [4] D. Hisamoto, W. -C. Lee, J. Kedzierski, E. Anderson, T. -J. King, J. Bokor, and C. Hu, Proceedings of IEDM 98 (1998) p [5] X. Huang, W. -C. Lee, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, Y. -K. Choi, V. Subramanian, T. -J. King, J. Bokor, and C. Hu, Proceedings of IEDM 99 (1999) p. 67. [6] C. Wang, J. Snyder, and J. R. Tucker, Appl. Phys. Lett. 74, 1174 (1999). [7] J. R. Tucker, Proceedings of the 1997 Advanced Workshop on Frontiers in Electronics (1997) pp [8] M. -K. Ieong, P. M. Solomon, S. E. Laux, H. -S. P. Wong, and D. Chidambarrao, Proceedings of IEDM 98 (1998) p [9] B. Winstead and U. Ravaioli, IEEE Trans. Electron Devices 47, 1241 (2000). [10] A. J. Auberton-Herve, M. Bruel, B. Aspar, C. Malevlle, and H. Moriceau, IEICE Trans. Electron. E80, 358 (1997). [11] J. Fujita, Y. Ohnishi, Y. Ochiai, and S. Matsui, Appl. Phys. Lett. 68, 1297 (1996). [12] E. H. Anderson, V. Boegli, and L. P. Muray, J. Vac. Sci. Technol. B15, 2327 (1997).