Fig The electron mobility for a-si and poly-si TFT.

Transcription

1 Fig The electron mobility for a-si and poly-si TFT. Fig The aperture ratio for a-si and poly-si TFT. 33

2 Fig All kinds defect well. (a) is the Dirac well. (b) is the repulsive Columbic well. (c) is the Columbic well. Fig Schematic illustration of the leakage current mechanisms. (a) thermionic emission. (TE) (b) thermionic field emission. (TFE) (c) pure field emission. (FE) 34

3 Gate Dielectric V Dsat Sourc e - e - h + Drain Depletion region Fig The devices operate in the saturation. 35

4 Fig Cross section of the multiple-gated TFT Fig I D - transfer characteristics as V DS = 1 V for TFT s with one, two, three, five, and six gates. 36

5 Fig Cross section of the offset-gate TFT Fig I D versus characteristics of a offset structure TFT and conventional TFT (L / W = 5 m / 1 m) for various value of V D. 37

6 Fig Schematic cross-section of the offset gated poly-si TFT without as additional offset mask (a) (b) Fig Schematic cross-section of the self-aligned offset gated poly-si TFT. 38

7 Fig The offset lengths of symmetrical device are 1.1 m and those the asymmetric poly-si TFT are 1.5 m and.3 m. Under forward bias the asymmetric poly-si TFT s offset length at the drain region is 1.5 m and that at the source region is.3 m. Fig Schematic cross-section of top gate, coplanar poly-si TFT with lightly doped drain region 39

8 (a) (b) Fig The channel area is defined in (a) and is not affected by subsequent processes. The LDD regions are well defined in (b) by the spacers, and are self-aligned to the channel and the source/drain regions. 4

9 Fig Schematic cross-section of GOLDD TFT 41

10 gate drain source Fig The top view of the T-gate poly-si TFTs. Fig Schematic cross sectional view of devices with conventional top-gate structure. 42

11 TEOS Oxide Gate TEOS Oxide poly-si Buffer oxide (a) TEOS Oxide Gate TEOS Oxide poly-s Buffer oxide (c) TEOS Oxide Gate TEOS Oxide poly-s Buffer oxide (b) TEOS Oxide Gate TEOS Oxide poly-s Buffer oxide (d) implant Gate Gate TEOS Oxide poly-si Buffer oxide n+ TEOS Oxide n- poly-si Buffer oxide n- n+ (e) (f) Fig The fabrication process (a) deposited to the second TEOS layer. (b) used gate mask to define this TEOS layer. (c) side etch the TEOS. (d) formed the raised structure (e) remove oxide about the source and drain. (f) implant to form the n + source and drain regions and n - regions. 43

12 (a) (b) Fig In-line SEM picture (a) short LDD length, (b) long LDD length. 44

13 Drain Current I D ( µ A ) n-tft W = 3µm, L = 5µm = 2 = 4 = 6 = 8 = 1 = Drain Voltage V D (V) Fig The I D -V D characteristics of the ploy-si TFTs. 16 Drain Current I D ( µa ) W = 3 µm, L = 5 µm = 8V = 1V = 12V = 14V = 16V least square fit Drain Voltage V D ( V ) Fig An example of ON resistance measurement in the linear regions of the ploy-si TFT output characteristics. 45

14 25 R on *W ( Ω-cm ) = 8 = 1 = 12 = 14 = 16 least square fit 5 l Rp*W Channel Length L ( µm ) Fig Width -normalized ON resistance as a function of channel length at different gate voltages. The solid lines represent the linear least square fit of the data.the channel width of these devices is fixed at 3 m. 46

15 VD = 5 V Drain current ( A ) LDD doping = 1E18 cm -3 LDD length =.158 µm Gate voltage ( V ) VD =.1 V no-ldd GOLDD Fig I D versus characteristic of non-ldd TFT and GOLDD TFT. Ron*W ( Ω*µm ) X W = 3 µm convention Rp*W l o VG = 8 V VG = 1 V VG VG = 14 V VG = 16 V Channel length ( µm ) (a) 47

16 Ron*W ( Ω*µm ) X W = 3 µm LDD dose = 1E18 cm -3 LDD length =.158 µm Rp*W = 8 V = 1 V = 14 V = 16 V l o Channel length ( µm ) (b) Ron*W ( Ω*µm ) X W = 3 µm LDD dose = 1E18 cm -3 LDD length =.594 µm = 8 V = 1 V = 14 V = 16 V l o.1. Rp*W Channel length ( µm ) (c) Fig Width -normalized ON resistance as a function of channel length at different gate voltages. The solid lines represent the linear least square fit of the data. (a) conventional TFT, (b) LDD length is.158 µm, (c) LDD length is.594 µm. 48

17 l Gate dielectric n + channel n + (a) Gate n + dielectric n - channel n - n + (b) Fig The dopant redistribution for (a) conventional TFTs, (b) GOLDD TFTs. 49

18 Gate n + dielectric channel (a) Gate n + n + dielectric n - channel n - n + (b) Fig The current path for (a) conventional TFTs, (b) GOLDD TFTs. 1 Gate current ( pa ) LDD doping = 1E18 cm -3 VD = 5 V convention GOLDD ( LDD length =.158 µm) Gate voltage ( V ) Fig I G versus V D characteristic of non-ldd TFT and GOLDD TFT. 5

19 3 25 LDD doping = 1E18 cm -3 convention GOLDD ( LDD length =.594 µm ) Drain current ( µa ) V 8 V 6 V 4 V Drain voltage ( V ) Fig I D versus V D characteristic of conventional TFT and GOLDD TFT. Depletion n + undoped poly-si n - n + (drain) current flow Fig The electron current path. 51

20 2.4 Threshold voltage ( V ) W = 3 µm LDD doping = 1E18 cm -3 V D =.1 V convention LDD length =.158 µm LDD length =.594 µm Channel length ( µm ) (a) 1.2 Threshold voltage ( V ) W = 3 µm LDD doping = 1E18 cm -3 V D = 5 V convention LDD length =.158 µm LDD length =.594 µm Channel length ( µm ) (b) Fig The V th -L characteristics for conventional and GOLDD TFTs (a) V D =.1 V, (b) V D =5 V. 52

21 n + Gate Dielectric neutral region (a) depletion Drain Gate depletion Dielectric n + n - neutral region n - Drain (b) Fig The charge share characteristics for (a) conventional TFTs, (b) GOLDD TFTs. 53

22 . Threshold voltage shift ( V TH ) ( V ) conventional TFTs W = 3 µm, V D = 5 V VTH = VTH(short channel)-vth(long channel) / channel length ( cm ) Fig The V th -L -1 characteristics for conventional TFTs. Drain current ( A ) LDD doping = 1E18 cm -3 V D = 5 V GOLDD ( LDD =.158 µm ) GOLDD ( LDD =.594 µm ) Gate voltage ( V ) Fig The I D - characteristics for different LDD length in the GOLDD TFTs. 54

23 ln { I D / [ ( - V FB ) V D ] } ( A / V -2 ) Nt = 3.2 x 117 cm-3 LDD dose = E18cm -3 LDD length =.158 µm VD =.1 V /( - V FB ) 2 ( V -2 ) (a) ln { I D / [ ( - V FB ) V D ] } ( A / V -2 ) Nt = 3.5 x 117 cm-3 LDD dose = E18cm -3 LDD length =.594 µm VD =.1 V /( - V FB ) 2 ( V -2 ) (b) Fig Plotting of ln I D / ( - V FB )V D versus ( - V FB )

24 Drain current ( A ) LDD = 1E18 cm -3 VD =.1 V ).594 µm GOLDD ( LDD =.158 µm ) GOLDD ( LDD =.594 µm ) Gate voltage ( V ) Fig The I D - characteristics for different LDD length in the GOLDD TFTs. Gate Drain Gate Drain Channel region LDD region Fig The energy band for channel and LDD region at V D =.1 V and = -1 V. 56

25 1-2 Average drain current ( A ) LDD doping = 1E18 cm -3 V D = 5 V GOLDD ( LDD =.158 µm ) GOLDD ( LDD =.594 µm ) Gate voltage ( V ) Fig The average I D - characteristics for different LDD length in the GOLDD TFTs. 1-4 Average drain current ( A ) LDD doping = 1E18 cm -3 V D =.1 V GOLDD ( LDD =.158 µm ) GOLDD ( LDD =.594 µm ) Gate voltage ( V ) Fig The average I D - characteristics for different LDD length in the GOLDD TFTs. 57

26 Drain current ( µa ) conventional TFTs = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) 1-3 Drain current ( A ) V D =.1 V V D = 5 V conventional TFTs Gate voltage ( V ) (b) 58

27 Drain current ( µa ) conventional TFTs = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for conventional TFTs : (a) I D -V D, (b) I D - (c) I D -V D. Drain current ( µa ) conventional TFTs stress 315 s ( VG = 5 V, VD = 15 V ) = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) 59

28 1-3, conventional TFTs stress 315 s ( VG = 5 V, VD = 15 V ) Drain current ( A ) V D =.1 V V D = 5 V Gate voltage ( V ) (b) Drain current ( µa ) conventional TFTs stress 315 s ( VG = 5 V, VD = 15 V ) = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for conventional TFTs stressed : (a) I D -V D, (b) I D - (c) I D -V D. 6

29 7 conventional TFTs stress 315 s ( VG = 5 V, VD = 15 V ) Drain current ( µa ) = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) conventional TFTs stress 315 s ( VG = 5 V, VD = 15 V ) 1-6 Drain current ( A ) V D =.1 V V D = 5 V Gate voltage ( V ) (b) 61

30 Drain current ( µa ) conventional TFTs stress 315 s ( VG = 5 V, VD = 15 V ) = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for conventional TFTs stressed and reversed Drain/Source contact : (a) I D -V D, (b) I D - (c) I D -V D. Drain current ( µa ) LDD length =.158 µm = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) 62

31 Drain current ( A ) V D =.1 V V D = 5 V LDD length =.158 µm Gate voltage ( V ) (b) Drain current ( µa ) LDD length =.158 µm = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for GOLDD TFTs which LDD length =.158 µm : (a) I D -V D, (b) I D - (c) I D -V D. 63

32 Drain current ( µa ) LDD length =.158 µm stress 315 s ( VG = 5 V, VD = 15 V ) = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) 1-3 Drain current ( A ) V D =.1 V V D = 5 V LDD length =.158 µm stress 315 s ( = 5 V, V D = 15 V ) Gate voltage ( V ) (b) 64

33 Drain current ( µa ) LDD length =.158 µm stress 315 s ( VG = 5 V, VD = 15 V ) = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for GOLDD TFTs which LDD length =.158 µm and stressed : (a) I D -V D, (b) I D - (c) I D -V D. 18, LDD length =.158 µm stress 315 s ( VG = 5 V, VD = 15 V ) Drain current ( µa ) = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) 65

34 V D =.1 V V D = 5 V Drain current ( A ) LDD length =.158 µm stress 315 s ( = 5 V, V D = 15 V ) Gate voltage ( V ) (b) Drain current ( µa ) LDD length =.158 µm stress 315 s ( VG = 5 V, VD = 15 V ) = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for GOLDD TFTs which LDD length =.158 µm, stressed and Drain/source reversed : (a) I D -V D, (b) I D - (c) I D -V D. 66

35 Drain current ( µa ) LDD length =.594 µm = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) Drain current ( A ) V D =.1 V V D = 5 V LDD length =.594 µm Gate voltage ( V ) (b) 67

36 Drain current ( µa ) LDD length =.594 µm = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for GOLDD TFTs which LDD length =.594 µm : (a) I D -V D, (b) I D - (c) I D -V D. Drain current ( µa ) LDD length =.594 µm stress 315 s ( = 5 V, V D = 15 V ) = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) 68

37 V D =.1 V V D = 5 V Drain current ( A ) LDD length =.594 µm stress 315 s ( = 5 V, V D = 15 V ) Gate voltage ( V ) (b) Drain current ( µa ) LDD length =.594 µm stress 315 s ( = 5 V, V D = 15 V ) = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for GOLDD TFTs which LDD length =.594 µm and streed : (a) I D -V D, (b) I D - (c) I D -V D. 69

38 Drain current ( µa ) LDD length =.594 µm stress 315 s ( = 5 V, V D = 15 V ) = 2 V = 4 V = 6 V = 8 V = 1 V Drain voltage ( V ) (a) V D =.1 V V D = 5 V Drain current ( A ) LDD length =.594 µm stress 315 s ( = 5 V, V D = 15 V ) Gate voltage ( V ) (b) 7

39 Drain current ( µa ) LDD length =.594 µm stress 315 s ( = 5 V, V D = 15 V ) = 8 V = 1 V = 14 V = 16 V Drain voltage ( V ) (c) Fig The typical characteristics for GOLDD TFTs which LDD length =.594 µm, streed and Drain/source reversed : (a) I D -V D, (b) I D - (c) I D -V D. 71

40 Table I Extracted Parasitic Resistance of Standard Devices and Proposed GOLDD Devices with Channel Width = 3um. Table II Extracted Parasitic Resistance of Standard Devices and Proposed GOLDD Devices with Channel Width = 1 um. Table Ш Extracted trap density of Proposed GOLDD Devices with Channel Width = 3um. Nt(1^17cm-3)