The Pennsylvania State University. Kurt J. Lesker Company. North Carolina State University. Taiwan Semiconductor Manufacturing Company 1

Transcription

1 Enhancement Mode Strained (1.3%) Germanium Quantum Well FinFET (W fin =20nm) with High Mobility (μ Hole =700 cm 2 /Vs), Low EOT (~0.7nm) on Bulk Silicon Substrate A. Agrawal 1, M. Barth 1, G. B. Rayner Jr. 2, V. T. Arun 1, C. Eichfeld 1, G. Lavallee 1, S-Y. Yu 1, X. Sang 3, S. Brookes 3, N. Agrawal 1, Y. Zheng 1, Y-J. Lee 4, Y-R. Lin 4, C-H. Wu 4, C-H. Ko 4, J. LeBeau 3, R. Engel-Herbert 1, S. E. Mohney 1, Y-C. Yeo 4 and S. Datta 1 1 The Pennsylvania State University 2 Kurt J. Lesker Company 3 North Carolina State University 4 Taiwan Semiconductor Manufacturing Company 1

2 Outline High Mobility Strained Germanium (s-ge) QW Novel Tri-layer Dielectric Integration on Ge s-ge QW on silicon Buffer Design and Growth s-ge QW FinFET Fabrication and Characterization Benchmarking 2

3 Strain-Enhanced Mobility Mobility [cm 2 /Vs] % strained-ge QWFET (T QW =15nm) 4x Relaxed-Ge MOSFET Strained Si Biaxial Compressive Strain s-ge QW SiGe Buffer Si Substrate 1 10 Hole Density [x10 12 /cm 2 ] *R. Pillarisetty, Nature 2011 r-ge Si Substrate 4x higher hole mobility for s-ge QWFET compared to r-ge MOSFET 3

4 Pt/Ti/ Au Si cap vs. GeOx IL Pd/Au 10 nm Ge QW 5 nm Si 0.3 Ge 0.7 Spacer Boron δ-doping 2x10 18 /cm 3 20nm 5x10 18 /cm 3 Phos Doping Si Substrate Pt/Ti/ Au 250 nm Si 0.3 Ge 0.7 Buffer 500 nm Si 0.7 Ge 0.3 Buffer High-k Cap Layer 10A Si Limits EOT Scaling Capacitance [ F/cm 2 ] Si cap passivation limits EOT scaling 3.0 f=1mhz w/ Si cap 0.5 Planar Gate Voltage [V] Ge QW/10A Si cap/5a Al 2 O 3 /22A HfO 2 4

5 Pt/Ti/ Au Si cap vs. GeOx IL Pd/Au 10 nm Ge QW 5 nm Si 0.3 Ge 0.7 Spacer Boron δ-doping 2x10 18 /cm 3 20nm 5x10 18 /cm 3 Phos Doping Si Substrate Pt/Ti/ Au 250 nm Si 0.3 Ge 0.7 Buffer 500 nm Si 0.7 Ge 0.3 Buffer High-k Cap Layer 10A Si Limits EOT Scaling 6A GeOx Low EOT, low D IT achieved Capacitance [ F/cm 2 ] 3.0 f=1mhz 2.5 GeOx IL X w/ Si cap 0.5 Planar Gate Voltage [V] Ge QW/6A GeOx IL/5A Al 2 O 3 /22A HfO 2 GeOx IL passivation instead of Si cap realized Low EOT of 0.83nm obtained on Ge QW 5

6 Bulk FinFET vs. QW FinFET Biaxial Strain r-ge Si Substrate s-ge QW SiGe Buffer Si Substrate W Fin High-k Cap layer Gate Metal r-ge High-k Cap Layer Gate Metal s-ge T QW r-ge SiGe Buffer Si Substrate Si Substrate Both W fin and T QW determine strain in Ge QW 6

7 S-Ge QW FinFET Highlights Channel Strain Asymmetric Uniaxial strain; μ Hole Enhancement Gate Metal s-ge Ge-Passivation In-situ H-Plasma clean Controlled sub-nm GeO x ; Low D IT Ultrathin EOT Phos Doping SiGe Buffer Si Substrate SiGe Buffer Optimization Retrograde Phos Doping; Eliminate parallel channel Scaled FinFET 20nm Fin Width; E-Mode Operation 7

8 Tri-Layer High-κ Gate Stack GOAL: Sub-1 nm (EOT) Metal 1.5eV p-ge E C E F E V 2.5eV HfO 2 Al 2 O 3 GeO x Reduce gate leakage Prevent HfO 2 -GeO x intermixing Reduce D IT Low temperature process prevent Si- Ge interdiffusion 8

9 GeO x Thickness [A] Tri-Layer Process Flow Native GeO x 30 sec, 100W H-Plasma T=250C Time [mins.] GeO x Thickness [A] O-Plasma 125W, 2 sec Pulse Plasma-OFF Plasma-ON T=250C Time [mins.] Cycle # Removal of native GeO x with low power H- Plasma etch High quality, uniform GeO x IL formed using low power O-Plasma pulse 9

10 Al 2 O 3 Thickness [A] 4 2 Tri-Layer Process Flow Thermal ALD TMA Precursor + H 2 O 6 T=250C Nucleation delay Cycle # HfO 2 Thickness [A] Thermal ALD TDMAH Precursor + H 2 O T=250C No Nucleation delay Cycle # Ultrathin Al 2 O 3 cap layer and HfO 2 high-κ deposited using Thermal ALD 10

11 Tri-Layer High-κ: In-situ GeO x Passivation Ge 17A HfO 2 6A GeO x / 5A Al 2 O 3 2nm Count [a.u.] Ge O Al Hf Depth [nm] In-situ plasma clean and GeO x IL realized for enhanced surface passivation Low power plasma reduces surface roughness 11

12 Capacitance [ F/cm 2 ] Tri-Layer High-κ/Ge C-V Characteristics HfO 2 / 5A Al 2 O 3 / 6A GeO x /p-ge 20A 75kHz to 2MHz 22A 30A HfO 2 Thickness T=300K 17A HfO 2 /3A Al 2 O 3 / 6A GeO x /p-ge D IT [/cm 2 /ev] A 20A E V 22A 30A HfO 2 Thickness Gate Voltage [V] Energy [E-E V ] HfO 2 /5A Al 2 O 3 /6A GeO x /p-ge EOT of ~0.72nm achieved Band-edge D IT from low to /cm 2 /ev in midgap observed 12

13 J G [A/cm 2 ] Gate Leakage Reduction HfO 2 /5A Al 2 O 3 /6A GeO x /p-ge [2] 22A HfO 2 /2A Al 2 O 3 /3A GeO x HfO X Reducing T=300K Gate Voltage [V] J G [A/cm 2 V FB -1V [1] HfO 2 (no IL) HfO 2 /Al 2 O 3 /GeO x [3] 4X This work HfO 2 /Al 2 O 3 /GeO x [4] HfO 2 (w/ IL) [1] Poly Si/SiO 2 [2] Al 2 O 3 /GeO x EOT [nm] Low gate leakage of 10-2 A/cm 2 (V G =V FB -1V) obtained at 0.72nm EOT with Tri-layer gate stack [1] C. Choi et al., EDL 2004 [2] R. Zhang et al., IEDM 2011 [3] R. Zhang et al., IEDM 2013 [4] R. Xie et al., IEDM

14 s-ge QW on Silicon: SiGe Buffer Optimization Si Cap 10 nm Ge QW 5 nm Si 0.3 Ge 0.7 Spacer 3nm Boron Modulation doping Depth=150nm, 250nm Si 0.3 Ge 0.7 Buffer 20nm 5x10 18 /cm 3 Phos Doping 2 μm Si 0.3 Ge 0.7 Buffer 500 nm Si 0.7 Ge 0.3 Buffer Si Substrate I D [ A/ m] mV/dec Planar w/ Si cap Phos Doping Depth No Phos Depth=150nm V DS =-0.5V L G =5 m Depth=250nm Gate Voltage [V] 10 3 X I OFF reduction with deeper Phos doping in SiGe buffer with no degradation in I ON 14

15 I D [ A/ m] QW MOSFET with Tri-layer High-k V DS =-0.05V, -0.5V L G =5 m w/ Si cap 100mV/dec Planar w/ GeOx IL 96mV/dec Gate Voltage [V] Source Current [ A/ m] V G -V T =-1V to 1V V G,Step =0.1V L G =5 m w/ Si Cap Drain Voltage [V] w/ GeOx IL Ge QW/Si Cap or GeO x IL/5A Al 2 O 3 /22A HfO 2 2X higher I ON (V DS =-0.5V) with 96 mv/dec subthreshold slope obtained with Tri-layer high-κ 15

16 Hole Mobility [cm 2 /Vs] 1000 Drift Mobility 100 w/ GeOx IL w/ Si Cap This work 4X Si Universal Unstrained Ge Hole Density [/cm 2 ] Hole Mobility [cm 2 /Vs] [1] IEDM, 2010 [1] IEDM, 2010 This work w/ Si cap 4X [3] IEDM, [2] VLSI, EOT [A] 25 Ns=5x10 12 /cm 2 4X higher hole mobility compared to r-ge achieved [1] R. Pillarisetty et al., IEDM 2010 [2] J. Mitard et al., VLSI 2009 [3] O. Weber et al., IEDM

17 Hole Mobility [cm 2 /Vs] 1000 Drift Mobility 100 w/ GeOx IL w/ Si Cap This work Si Universal 4X Unstrained Ge Hole Density [/cm 2 ] Hole Mobility [cm 2 /Vs] This work w/ GeOx IL [1] IEDM, 2010 [1] IEDM, 2010 This work w/ Si cap 4X [3] IEDM, [2] VLSI, EOT [A] 25 Ns=5x10 12 /cm 2 Highest hole mobility at lowest EOT achieved with GeO x IL [1] R. Pillarisetty et al., IEDM 2010 [2] J. Mitard et al., VLSI 2009 [3] O. Weber et al., IEDM

18 Outline Integrate s-ge QW and Tri-layer high-κ in a FinFET 18

19 Asymmetric Strained FinFET Biaxial Compressive Strain Z Y X Transverse (100) ε XX [%] s-ge QW Phos Doping SiGe Buffer Si Substrate Transverse Strain, XX [%] Phos Doping SiGe Buffer Si Substrate Position Across Fin [nm] Strain relaxation near sidewall results in net uniaxial strain along the channel direction 19

20 Transverse Strain, xx [%] Fin Mobility Fin Width [nm] Longitudinal Strain, YY [%] nm Uniaxial Strain [%] Mobility enhancement due to increasing uniaxial compressive strain with reducing W fin 20 Hole Mobility [cm 2 /Vs] Ns=10 13 /cm (110)Ge Wfin (100)Ge 50nm * M. Chu et al., Annu. Rev. Mater. Res. 2009

21 FinFET Fabrication Flow 1 nm Si Cap 10 nm Ge QW 5 nm Si 0.3 Ge 0.7 Spacer 3nm Boron Modulation doping 250 nm Si 0.3 Ge 0.7 Buffer PR PR 10 nm Ge QW 20nm 5E18 /cm 3 Phos Doping 2 μm Si 0.3 Ge 0.7 Buffer 500 nm Si 0.7 Ge 0.3 Buffer Si Substrate Gate Metal Fin Pattern + Hardmask Deposition Si 0.3 Ge 0.7 Buffer Fin Pattern + Deposit Hardmask Dry RIE Etch 10nm Ge QW B-doping Si 0.3 Ge 0.7 Buffer 20nm 5E18 /cm 3 Phos Doping 500 nm Si 0.7 Ge 0.3 Buffer Si Substrate Tri-Layer High-k + Gate Patterning SiGe Buffer 21 FinFET fabrication using Sidewall Image Transfer (SIT)

22 FinFET Fabrication : SEM Source Gate Fin W fin =20nm Drain W fin =20nm Ge Ge Si 0.3 Ge 0.7 Si 0.3 Ge nm 20 nm Fin Pitch=80nm W fin =20nm; Fin pitch = 80nm; Tri-layer high-κ realized on s-ge QW with SIT process 22

23 FinFET Fabrication : TEM Gate Metal 10nm Ge QW B-doping Si 0.3 Ge 0.7 Buffer 20nm 5E18 /cm 3 Phos Doping 500 nm Si 0.7 Ge 0.3 Buffer W fin =20nm Ge Si 0.3 Ge 0.7 Buffer Al 2 O 3 /GeO x HfO 2 Si Substrate 10nm Vertical fin sidewall profile achieved for W fin =20nm QW FinFET 23

24 I D [ A/ m] Long Channel FinFET Performance 10 3 w/ GeOx IL V DS =-0.05V -0.5V L G =5 m mV/dec W Fin Planar 20nm 96mV/dec Gate Voltage [V] I D [ A m] Planar FinFET (W Fin =20nm) V G -V T =-1V to 1V V G,Step =0.1V L G =5 m Drain Voltage [V] E-Mode (V T =-0.75V); I ON /I OFF ~10 4 ; SS=150mV/dec for W fin =20nm FinFET with Tri-layer high-κ obtained 24

25 V T,SAT [V] E-Mode QW FinFET Operation 0.4 Depletion Mode V DS =-0.5V Enhancement Mode V DS =-0.5V 100 L G =5 m 100 V DS =-0.5V Planar Planar Planar Fin Width [nm] Fin Width [nm] Fin Width [nm] SS [mv/dec] Peak Gm [ S/ m] W fin =20nm; L G =5μm; 10 fins/μm E-Mode operation for W fin =45nm and 20nm Degradation in SS (36%) and peak Gm (60%) with reducing W fin 25

26 Hole Mobility [cm 2 /Vs] Fin Mobility Planar W Fin =70nm W Fin =45nm W Fin =20nm Unstrained Ge Si Universal T=300K 2.6X 2X Hole Density [/cm 2 ] Peak Mobility [cm 2 /Vs] Planar Fin Width [nm] 2.6X higher μ Peak obtained with s-ge QW 26 FinFET (W fin =20nm) compared to unstrained-ge

27 FinFET Hole Transport Highlights Hole Mobility [cm 2 /Vs] Planar FinFET Hole Density [/cm 2 ] Reducing sidewall D IT and sidewall roughness key to achieving higher fin mobility 27

28 Transport Degradation Hole Mobility [cm 2 /Vs] Planar N S N -1 S N -1 S 77K 150K 300K FinFET (W Fin =20nm) N S N -1 S N -2 S Hole Density [/cm 2 ] Scattering Mechanism Acoustic Phonon Ns and T Dependence Ns -1/3 T Sidewall Roughness Ns -2 T 0 Remote Charge Scattering Ns 3/2 T 0 Strong Ns dependence for FinFET at 77K indicates sidewall roughness scattering 28

29 Transport Degradation Hole Mobility [cm 2 /Vs] Planar W Fin =70nm Scattering Mechanism Acoustic Phonon W Fin =45nm W Fin =20nm Ns=10 13 /cm 2 T -1 T Temperature [K] Ns and T Dependence Ns -1/3 T Sidewall Roughness Ns -2 T 0 Remote Charge Scattering Ns 3/2 T 0 Reduced temperature dependence of mobility for FinFET is indicative of sidewall roughness 29

30 Short Channel Ge QW FinFET Gate Fin Source Drain Al Gate 100nm L G 10nm s-ge QW GeO x /Al 2 O 3 HfO 2 100nm 20nm Si 0.3 Ge 0.7 Buffer Short channel FinFET with gate length of 100nm and Tri-layer high-κ fabricated using SIT 30

31 I D [ A/ m] Short Channel FinFET Performance V DS =-0.05V V DS =-0.5V 130 mv/dec Tri-Layer High-k/s-Ge QW FinFET Gate Voltage [V] I D [ A m] Tri-Layer High-k/s-Ge QW FinFET V G -V T =-1V to 1V Drain Voltage [V] W fin =20nm; L G =100nm; 10 fins/μm V G,Step =0.1V E-Mode L G =100nm QW FinFET (W fin =20nm) with with I ON =90μA/μm (V G -V T =-0.5V) and SS=130 mv/dec 31

32 G m [ S/ m] Transconductance Tri-Layer High-k/s-Ge QW FinFET W Fin =20nm V DS =-0.5V 1.6X L G =100nm L G =5 m Gate Voltage [V] R SD-Linear [ m] 7x10 4 6x10 4 5x10 4 4x10 4 3x10 4 2x10 4 1x FinFET W Fin =20nm L G =100nm R Ext = 6.4k - m V G -V T =0V V G -V T =-0.2V V G -V T =-0.8V Gate Length [ m] Peak G m enhancement of 1.6X observed for L g =100nm QW FinFET High R access =6.4kΩ-μm limits short channel performance 32

33 I D [ A/ m] Benchmarking [1] Intel 22nm pmos FinFET W Fin =20nm L G =100nm V DS =-0.5V V G -V T [V] 3D simulation model calibration to experiment performed using self-consistent Poisson- Schrodinger solver for QW FinFET [1] C. Auth et al., VLSI

34 I D [ A/ m] Performance Projection X [1] Intel 22nm pmos FinFET W Fin =20nm L G =100nm V DS =-0.5V V G -V T [V] Channel Position [nm] v inj estimated at 8x10 6 cm/s for s-ge QW short channel FinFET at L G =100nm v eff [x10 6 cm/s] 10 5 v inj =8x10 6 virtual source cm/s 3x10 6 cm/s Intel 22nm pmos FinFET R ext = 6.4 kω-μm -> 200 Ω-μm [1] C. Auth et al., VLSI 2012 V GS =V DS =-0.5V L G =100nm 34

35 Conclusion Asymmetric uniaxial strain along fin (1.8%) results in high hole mobility in s-ge QW FinFET In-situ H-plasma clean and Tri-layer High-k gate stack developed: Low leakage (10-2 A/cm 2 ), low D IT at ultrathin EOT (0.72nm) obtained Mobility of 770 cm 2 /Vs at 0.83nm EOT achieved with s-ge QW MOSFETs E-Mode 1.3% s-ge QW FinFET with W fin =20nm and μ Hole =700 cm 2 /Vs (2.6X over r-ge) achieved with Trilayer high-k s-ge QW FinFET shows 8x10 6 cm/s v inj (simulation) with lower R access 35

36 Acknowledgements TSMC o Exploratory Technology Development Kurt J. Lesker Co. Penn State Nanofab National Science Foundation THANK YOU 36